CN213521848U - I/O port circuit and electronic equipment - Google Patents
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Abstract
The utility model discloses a IO port circuit and electronic equipment. The I/O port circuit includes: the device comprises a signal receiving module, a driving signal module and a signal output module; the signal receiving module is used for receiving a control electric signal and carrying out logic conversion on the control electric signal so as to generate a logic electric signal; the driving signal module is used for performing signal conversion according to the logic electric signal to generate a driving electric signal and outputting the driving electric signal to the signal output module; and the signal output module is used for inverting the driving electric signal to generate and output driving voltage. The working mode is switched based on different logic electricity corresponding to the external port pins, corresponding driving signals are output, multiple I/O output modes are achieved, the I/O output modes are flexible, multiple I/O structure circuits of various types are prevented from being arranged in the same controller, register and the like, and design and production cost is reduced.
Description
Technical Field
The utility model relates to a port circuit technical field especially relates to a IO port circuit and electronic equipment.
Background
The I/O port circuit in the prior art is simple in type, cannot be switched to different modes to work, different I/O interface circuits need to be configured when a controller and a register need to support various types of I/O, the circuit flexibility is low, and the design and production costs of the controller and the register are high.
SUMMERY OF THE UTILITY MODEL
A primary object of the present invention is to provide an io port circuit and an electronic device, which can solve the technical problem of the prior art that the io port can not switch the operating modes flexibly.
To achieve the above object, the present invention provides an I/O port circuit, which includes: the device comprises a signal receiving module, a driving signal module and a signal output module; the first output end of the signal receiving module is connected with the first input end of the driving signal module, the second output end of the signal receiving module is connected with the second input end of the driving signal module, and the output end of the driving signal module is connected with the input end of the signal output module; wherein,
the signal receiving module is used for receiving a control electric signal and carrying out logic conversion on the control electric signal so as to generate a logic electric signal;
the driving signal module is used for performing signal conversion according to the logic electric signal to generate a driving electric signal and outputting the driving electric signal to the signal output module;
and the signal output module is used for inverting the driving electric signal to generate and output driving voltage.
Optionally, the signal receiving module includes a first inverting unit and a logic converting unit; the input end of the first phase inverter unit receives the control electric signal; a first output end of the first phase inverter unit is connected with a first input end of the logic conversion unit; and a second output end of the first phase inverter unit is connected with a second input end of the logic conversion unit, and an output end of the logic conversion unit is connected with an input end of the driving signal module.
Optionally, the signal output module includes a second inverting unit and a port pin, an input end of the second inverting unit is connected to the port pin, and an input end of the second inverting unit is further connected to an output end of the driving signal module.
Optionally, the first inverter unit includes a first inverter and a second inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the first phase inverter is also connected with the second input end of the logic conversion unit;
and the output end of the second inverter is connected with the first input end of the logic conversion unit.
Optionally, the logic conversion unit includes a clock delay module and an or gate; the input end of the clock delay module is connected with the output end of the second inverter, the output end of the clock delay module is connected with one input end of the or gate, the other input end of the or gate is connected with the output end of the first inverter, and the output end of the or gate is connected with the input end of the driving signal module.
Optionally, the driving signal module includes a first transistor, a second transistor, and a third transistor; wherein,
a base of the first transistor is connected to an output terminal of the or gate, an emitter of the first transistor is connected to an emitter of the second transistor, an emitter of the second transistor is connected to an emitter of the third transistor, and an emitter of the third transistor is connected to the port pin;
a base of the second transistor is connected to an output terminal of the first inverter, and a collector of the first transistor, a collector of the second transistor, and a collector of the third transistor are connected to a power supply voltage terminal.
Optionally, the driving signal module further includes a fourth transistor, a base of the fourth transistor is connected to the output terminal of the first inverter, an emitter of the fourth transistor is grounded, and a collector of the fourth transistor is connected to the emitter of the first transistor.
Optionally, the second inverting unit includes a third inverter and a fourth inverter; the input end of the third inverter is connected with the port pin, the output end of the third inverter is connected with the input end of the fourth inverter, and the input end of the fourth inverter is further connected with the base electrode of the third transistor.
Optionally, the first transistor, the second transistor, and the third transistor are P-type transistors; the fourth transistor is an N-type transistor.
In addition, in order to achieve the above object, the present invention also provides an electronic device including the I/O port circuit as described above.
The utility model discloses a set up IO port circuit and include: the device comprises a signal receiving module, a driving signal module and a signal output module; the first output end of the signal receiving module is connected with the first input end of the driving signal module, the second output end of the signal receiving module is connected with the second input end of the driving signal module, and the output end of the driving signal module is connected with the input end of the signal output module; the signal receiving module is used for receiving a control electrical signal and performing logic conversion on the control electrical signal to generate a logic electrical signal; the driving signal module is used for performing signal conversion according to the logic electric signal to generate a driving electric signal and outputting the driving electric signal to the signal output module; and the signal output module is used for inverting the driving electric signal to generate and output driving voltage. The working mode is switched based on different logic electricity corresponding to the external port pins, corresponding driving signals are output, multiple I/O output modes are achieved, the I/O output modes are flexible, multiple I/O structure circuits of various types are prevented from being arranged in the same controller, register and the like, and design and production cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of a first embodiment of an I/O port circuit according to the present invention;
fig. 2 is a circuit diagram of a second embodiment of the I/O port circuit of the present invention.
The reference numbers illustrate:
| reference numerals | Name (R) | Reference numerals | Name (R) | Reference numerals | Name (R) |
| 10 | |
11 | |
111 | |
| 20 | |
12 | |
112 | |
| 30 | Signal output module | Q1～Q4 | First to |
321 | |
| 31 | |
32 | |
322 | |
| 121 | |
122 | OR gate |
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the invention.
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
It should be noted that all the directional indicators (such as upper, lower, left, right, front and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the motion situation, etc. in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit ly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, it should be considered that the combination of the technical solutions does not exist, and is not within the protection scope of the present invention.
It should be noted that, in the practical application of the present invention, the software program is inevitably applied to the software program, but the applicant states here that the software program applied in the embodiment of the present invention is the prior art, and in the present application, the modification and protection of the software program are not involved, but only the protection of the hardware architecture designed for the purpose of the invention.
The utility model provides a IO port circuit, refer to fig. 1, fig. 1 is the utility model discloses the structure schematic diagram of IO port circuit first embodiment.
The I/O port circuit includes: the signal receiving module 10, the driving signal module 20 and the signal output module 30; a first output end of the signal receiving module 10 is connected to a first input end of the driving signal module 20, a second output end of the signal receiving module 10 is connected to a second input end of the driving signal module 20, and an output end of the driving signal module 20 is connected to an input end of the signal output module 30.
It should be understood that the I/O port circuit described in this embodiment may be used as both an input and an output. The signal receiving module 10 is configured to receive a control electrical signal and perform logic conversion on the control electrical signal to generate a logic electrical signal.
It is easy to understand that the control electrical signal is input by a superior circuit, which may be a latch, and latches and sets the input end of the signal receiving module 10; the signal receiving module 10 receives the control electrical signal input by the latch, and performs logic conversion to generate a logic electrical signal. The mode of the driving signal module 20 for converting the driving signal can be controlled according to the logic electrical signal, and various operating modes of the I/O interface can be correspondingly switched according to the input control electrical signal, including but not limited to: a "weak pull-up" mode, a "strong pull-up" mode, a push-pull output mode, a high impedance mode, and an open-drain output configuration.
The driving signal module 20 is configured to perform signal conversion according to the logic electrical signal to generate a driving electrical signal, and output the driving electrical signal to the signal output module 30.
It should be understood that the driving signal module 20 includes transistors, at least one N-type transistor and a plurality of P-type transistors, and the transistors receive the electrical signal after the signal receiving module 10 performs logic conversion, perform corresponding switching according to the level, and generate corresponding driving electrical signals.
The signal output module 30 is configured to invert the driving electrical signal to generate a driving voltage and output the driving voltage.
It should be understood that the signal output module 30 includes a port pin, which may be a general I/O pin, and generates and outputs a driving voltage according to a driving electrical signal and a setting signal received by the port pin. The signal output module 30 can receive various I/O output modes of different logic television lines through the port pins, and the I/O output modes are flexible.
Through the circuit, the logic conversion unit is arranged in the signal receiving module, so that the driving signal module can generate driving voltage according to different logic electricity output by the logic conversion unit and by combining a setting signal received by a port pin in the signal output module; the circuit can switch the working modes based on different logic electricity corresponding to the external port pins, output corresponding driving signals, realize multiple I/O output modes, is flexible in I/O output modes, avoids arranging multiple I/O structure circuits of various types in the same controller, register and the like, and reduces design and production cost.
Based on the first embodiment of the present invention, the second embodiment of the I/O port circuit of the present invention is proposed, referring to fig. 2. Fig. 2 is a circuit diagram of a second embodiment of the I/O port circuit of the present invention.
The signal receiving module 10 includes a first inverter unit 11 and a logic converting unit 12; the input end of the first phase inverter unit 11 receives the control electrical signal; a first output terminal of the first inverter unit 11 is connected to a first input terminal of the logic converting unit 12; a second output end of the first inverter unit 11 is connected to a second input end of the logic converting unit 12, and an input end of the logic converting unit 12 is connected to an input end of the driving signal module 20.
The first inverter unit 11 includes a first inverter 111, a second inverter 112; wherein, the output end of the first inverter 111 is connected with the input end of the second inverter 112, and the output end of the first inverter 111 is further connected with the second input end of the logic conversion unit 12; the output of the second inverter 112 is connected to the first input of the logic converting unit 12.
It is easy to understand that, the inverters may invert the phase of the input signal, the input terminal of the first inverter 111 is the input terminal of the I/O interface circuit, when the input terminal is set to 1, the first inverter 111 outputs 0, outputs a 0 signal to the second inverter 112, and the second inverter 121 outputs a 1 signal to an input terminal of the logic conversion unit 12; meanwhile, the first inverter 111 outputs a 0 signal to the other input terminal of the logic conversion unit 12.
The logic conversion unit 12 includes a clock delay module 121 and an or gate 122; an input end of the clock delay module 121 is connected to an output end of the second inverter 112, an output end of the clock delay module 121 is connected to an input end of the or gate 122, another input end of the or gate 122 is connected to an output end of the first inverter 111, and an output end of the or gate 122 is connected to an input end of the driving signal module 20.
It should be understood that the or gate outputs a 1 (high) when all inputs are logic 1 and a 0 (low) when all inputs are not logic 1. The clock delay module 121 delays the inverted logic signal and outputs the delayed signal to an input terminal of the or gate 122, and another input terminal of the or gate 122 is connected to the output terminal of the first inverter 111. The or gate 122 outputs a high signal to the driving signal module 20 due to the phase inversion of the second inverter 112 and the delay of the clock delay module 121.
The driving signal module 20 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3; wherein the base of the first transistor Q1 is connected to the output of the or gate 122, the emitter of the first transistor Q1 is connected to the emitter of the second transistor Q2, the emitter of the second transistor Q2 is connected to the emitter of the third transistor Q3, and the emitter of the third transistor Q3 is connected to the port pin 31; the base of the second transistor Q2 is connected to the output terminal of the first inverter 111, and the collector of the first transistor Q1, the collector of the second transistor Q2, and the collector of the third transistor Q3 are connected to a power supply voltage terminal VDD. The driving signal module 20 further includes a fourth transistor Q4, a base of the fourth transistor Q4 is connected to the output terminal of the first inverter 111, an emitter of the fourth transistor Q4 is grounded, and a collector of the fourth transistor Q4 is connected to the emitter of the first transistor Q1.
The first transistor Q1, the second transistor Q2, and the third transistor Q3 are P-type transistors; the fourth transistor Q4 is an N-type transistor.
The signal output module 30 includes a second inverting unit 32 and a port pin 31, an input end of the second inverting unit 32 is connected to the port pin 31, and an input end of the second inverting unit 32 is further connected to an output end of the driving signal module 20.
The second inverting unit 32 includes a third inverter 321 and a fourth inverter 322; the input terminal of the third inverter 321 is connected to the port pin 31, the output terminal of the third inverter 321 is connected to the input terminal of the fourth inverter 322, and the input terminal of the fourth inverter 322 is further connected to the base of a third transistor Q3.
It should be noted that, the first inverter 111 receives a high level, the base of the first transistor Q1 receives a high level through the second inverter 112, the clock delay module 121 and the or gate 122, and the first transistor Q1 is turned on; the base levels of the second transistor Q2 and the fourth transistor Q4 are the same, the bases of the second transistor Q2 and the fourth transistor Q4 are at a low level due to the action of the first inverter 111, and the base of the third transistor Q3 is at a low level when the output terminal of the third inverter 321 is connected to the base of the third transistor Q3 and the input of the third inverter 321 is at a high level. The first transistor Q1 is turned on, and outputs a corresponding driving voltage according to the setting of the port pin.
It should be understood that the first inverter 111 receives a low level, the base of the first transistor Q1 receives a low level through the second inverter 112 and the clock delay module 121 and the or gate 122, and the first transistor Q1 is turned off; the base levels of the second transistor Q2 and the fourth transistor Q4 are the same, the base levels of the second transistor Q2 and the fourth transistor Q4 are high due to the action of the first inverter 111, the base level of the third transistor Q3 is low due to the fact that the output end of the third inverter 321 is connected with the base level of the third transistor Q3, and the input of the third inverter 321 is high, the base level of the first transistor Q1 is conductive, and corresponding driving voltage is output according to the setting of the port pin.
In a specific implementation, the I/O port circuit can be used as both an input and an output, if the output logic level of the port pin is a high level, the driving capability is weak, and at this time, the external device is allowed to pull down the level, and if the level of the port pin is pulled down, the driving capability is strong, and the current absorption is increased. There are three pull-up modes in the present I/O port circuit that are applicable to different scenarios, including weak pull-up, strong pull-up, and extra weak pull-up.
In specific implementation, when the input end of the I/O port circuit is locked at logic 1 by a latch, the I/O port circuit is switched to an ultra-weak pull-up mode, and the level of a port pin is pulled up by a small current; and when the port pin is in logic 1, the I/O port circuit is switched to a weak pull-up mode, and if the port pin is pulled down by an external device and is not set to be logic 1 any more, the weak pull-up mode is switched to an ultra-weak pull-up mode. When the voltage of the port pin is lower than the threshold voltage due to the sink current (passively input current) of the external device, the weak pull-up mode is converted into the ultra-weak pull-up mode. When the port pin is converted from logic 0 to logic 1, the I/O port circuit is in a strong pull-up mode, and after the port pin is set to logic 1, the strong pull-up mode is converted into a weak pull-up mode and an ultra-weak pull-up mode.
In one embodiment, the port pin is locked to 1 and continues to be in the pull-up mode. The push-pull output mode is applied to a scene that the output current of a port is large. The high impedance mode may reduce current consumption at logic 0, requiring a certain level to be provided by an external device. The open-drain output configuration turns off all internal pull-up modes, and only turns on the fourth transistor Q4 when the port pin is locked to logic 0, where the fourth transistor Q4 is a pull-down transistor. If a logic 1 is output in open-drain output configuration, an external device is required to provide a determined level.
The utility model discloses a set up above-mentioned circuit, can generate corresponding driving voltage when external port pin self is in different logic electricity, realize multiple IO output mode, IO output mode is nimble, avoids setting up many each type's IO structure circuit at same controller, register etc. and reduction design and manufacturing cost.
Furthermore, to achieve the above object, the present invention also provides an electronic device including the I/O port circuit as described above.
Since the electronic device adopts all technical solutions of all the embodiments, at least all the beneficial effects brought by the technical solutions of the embodiments are achieved, and no further description is given here.
It should be understood that the above is only an example, and the technical solution of the present invention is not limited in any way, and in the specific application, those skilled in the art can set the solution as required, and the present invention is not limited thereto.
It should be noted that the above-described work flow is only illustrative, and does not limit the scope of the present invention, and in practical applications, a person skilled in the art may select some or all of them to achieve the purpose of the solution of the embodiment according to practical needs, and the present invention is not limited herein.
In addition, the technical details that are not elaborated in this embodiment can be referred to the I/O port circuit provided in any embodiment of the present invention, and are not described herein again.
Further, it is to be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The above embodiment numbers of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.
The above is only the preferred embodiment of the present invention, and not the scope of the present invention, all the equivalent structures or equivalent flow changes made by the contents of the specification and the drawings or the direct or indirect application in other related technical fields are included in the patent protection scope of the present invention.
Claims (10)
1. An I/O port circuit, comprising: the device comprises a signal receiving module, a driving signal module and a signal output module; the first output end of the signal receiving module is connected with the first input end of the driving signal module, the second output end of the signal receiving module is connected with the second input end of the driving signal module, and the output end of the driving signal module is connected with the input end of the signal output module; wherein,
the signal receiving module is used for receiving a control electric signal and carrying out logic conversion on the control electric signal so as to generate a logic electric signal;
the driving signal module is used for performing signal conversion according to the logic electric signal to generate a driving electric signal and outputting the driving electric signal to the signal output module;
and the signal output module is used for inverting the driving electric signal to generate and output driving voltage.
2. The I/O port circuit of claim 1, wherein the signal receiving module comprises a first inverting unit and a logic converting unit; the input end of the first phase inverter unit receives the control electric signal; a first output end of the first phase inverter unit is connected with a first input end of the logic conversion unit; and a second output end of the first phase inverter unit is connected with a second input end of the logic conversion unit, and an output end of the logic conversion unit is connected with an input end of the driving signal module.
3. The I/O port circuit of claim 2, wherein the signal output module comprises a second inverting unit and a port pin, an input of the second inverting unit being connected to the port pin, an input of the second inverting unit being further connected to an output of the driving signal module.
4. The I/O port circuit of claim 3, wherein the first inverter unit comprises a first inverter, a second inverter; the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the first phase inverter is also connected with the second input end of the logic conversion unit;
and the output end of the second inverter is connected with the first input end of the logic conversion unit.
5. The I/O port circuit of claim 4, wherein the logic conversion unit comprises a clock delay module and an OR gate; the input end of the clock delay module is connected with the output end of the second inverter, the output end of the clock delay module is connected with one input end of the or gate, the other input end of the or gate is connected with the output end of the first inverter, and the output end of the or gate is connected with the input end of the driving signal module.
6. The I/O port circuit of claim 5, wherein the driving signal module comprises a first transistor, a second transistor, and a third transistor; wherein,
a base of the first transistor is connected to an output terminal of the or gate, an emitter of the first transistor is connected to an emitter of the second transistor, an emitter of the second transistor is connected to an emitter of the third transistor, and an emitter of the third transistor is connected to the port pin;
a base of the second transistor is connected to an output terminal of the first inverter, and a collector of the first transistor, a collector of the second transistor, and a collector of the third transistor are connected to a power supply voltage terminal.
7. The I/O port circuit of claim 6, wherein the drive signal module further comprises a fourth transistor, a base of the fourth transistor connected to the output of the first inverter, an emitter of the fourth transistor connected to ground, and a collector of the fourth transistor connected to the emitter of the first transistor.
8. The I/O port circuit of claim 7, wherein the second inverter unit comprises a third inverter and a fourth inverter; the input end of the third inverter is connected with the port pin, the output end of the third inverter is connected with the input end of the fourth inverter, and the input end of the fourth inverter is further connected with the base electrode of the third transistor.
9. The I/O port circuit of claim 8, wherein the first transistor, the second transistor, and the third transistor are P-type transistors; the fourth transistor is an N-type transistor.
10. An electronic device comprising the I/O port circuit of any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022233113.XU CN213521848U (en) | 2020-10-09 | 2020-10-09 | I/O port circuit and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022233113.XU CN213521848U (en) | 2020-10-09 | 2020-10-09 | I/O port circuit and electronic equipment |
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| CN213521848U true CN213521848U (en) | 2021-06-22 |
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