CN213459001U

CN213459001U - Control system and receiving card of display screen

Info

Publication number: CN213459001U
Application number: CN202022483992.1U
Authority: CN
Inventors: 段敏杰; 韦桂锋
Original assignee: Xian Novastar Electronic Technology Co Ltd
Current assignee: Xian Novastar Electronic Technology Co Ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2021-06-15
Anticipated expiration: 2030-10-30

Abstract

The utility model discloses a control system and receiving card of display screen. Wherein, this system includes: the field editable gate array comprises a plurality of first ports which are connected with a plurality of first lamp panel unit groups in the display screen in a one-to-one correspondence manner; the target device is connected with the field editable gate array through a first data line, and a plurality of second ports of the target device are correspondingly connected with a plurality of second lamp panel unit groups in the display screen one by one; the first data line is used for transmitting a first control signal and a second control signal sent by the field editable gate array to the target device, and the target device is used for controlling the plurality of second lamp panel unit groups based on the first control signal and performing online upgrading based on the second control signal. The utility model provides an area of receiving card carries the size limitedly among the correlation technique, can't satisfy the technical problem that the data set expands the demand.

Description

Control system and receiving card of display screen

Technical Field

The utility model relates to a LED display screen field particularly, relates to a control system and receiving card of display screen.

Background

With the smaller dot pitch of the LED display screen, the receiving card of the LED display screen has larger and larger loading, but the number of IO of the current receiving card is limited, and the loading of the current mainstream receiving card is 32 parallel groups (R/G/B uses 1 channel signal respectively, and 3 channels of signals are called parallel) or 64 serial groups (R/G/B shares 1 channel signal, and the R/G/B is represented by time division multiplexing), so that the loading is limited, and the above requirements cannot be met.

For the purpose of data group expansion of the receiving card, a DCLK double clock expansion method may be adopted, wherein DCLK double clock expansion means that DCLK output is expanded into 2 paths, and the 2 nd path is a 180 ° phase-shifted clock of the 1 st path. Because the DCLK clock only samples data at the rising edge, the R/G/B can output different image information at the rising edge and the falling edge, at the moment, the same group of R/G/B is distributed to 2 different LED lamp panel units, 2 paths of different DCLK are connected to the different LED lamp panel units, and at the moment, the LED lamp panel units obtain respective R/G/B information at the respective DCLK rising edge, so that the purpose of expanding one path of clock into 2 paths is achieved.

However, since only the number of clocks is expanded, but the number of R/G/B is not expanded, but the transmission rate of R/G/B data is increased by 2 times, which results in an increase of 2 times of data output frequency, at this time, the requirement on the signal wiring quality of the LED lamp panel unit group is high, and it is difficult to satisfy the data group expansion in practical significance.

SUMMERY OF THE UTILITY MODEL

The embodiment of the utility model provides a control system and receiving card of display screen to it is limited to solve the area year size of receiving the card in the correlation technique at least, can't satisfy the technical problem that the data set expanded the demand.

According to an aspect of the embodiments of the present invention, there is provided a control system of a display screen, including: the field editable gate array comprises a plurality of first ports which are connected with a plurality of first lamp panel unit groups in the display screen in a one-to-one correspondence manner; the target device is connected with the field editable gate array through a first data line, and a plurality of second ports of the target device are correspondingly connected with a plurality of second lamp panel unit groups in the display screen one by one; the first data line is used for transmitting a first control signal and a second control signal sent by the field editable gate array to the target device, and the target device is used for controlling the plurality of second lamp panel unit groups based on the first control signal and performing online upgrading based on the second control signal.

Optionally, the field-editable gate array comprises: the first transmission module is connected with the first data line and used for sending a first control signal and a second control signal based on a preset protocol, and the preset protocol comprises one of the following protocols: a low voltage differential signal protocol, a serial peripheral interface protocol, a gigabit media independent interface protocol, a reduced gigabit media independent interface protocol; the target device includes: and the second transmission module is connected with the first data line and used for receiving the first control signal and the second control signal based on a preset protocol.

Optionally, the field-editable gate array further comprises: the data receiving module is used for receiving the image data and the upgrading data; the data processing module is connected with the data receiving module and used for analyzing the image data and upgrading the data; and the first control module is connected with the data processing module and the first transmission module and used for generating a first control signal based on the analyzed image data and generating a second control signal based on the analyzed upgrading data.

Optionally, the control system further comprises: the memory, the field-editable gate array further comprises: and the third control module is connected with the data processing module and the memory and used for storing the analyzed image data into the memory.

Optionally, the field-editable gate array comprises: and the first control module is connected with the first ports and used for controlling the first lamp panel unit groups.

Optionally, the field-editable gate array is connected to the target device via a second data line, wherein the second data line is used for transmitting the state data of the target device to the field-editable gate array.

Optionally, the target device comprises: the second transmission module is connected with the second data line and used for sending the state data through a preset protocol; the field-editable gate array comprises: and the first transmission module is connected with the second data line and used for receiving the state data through a preset protocol. Optionally, the target device is a complex programmable logic device.

Optionally, the target device is disposed at a position of one of: the receiving card connected with the display screen, the lamp panel of the display screen and the multiport transponder between the receiving card and the lamp panel.

According to the utility model discloses on the other hand, still provide a receiving card, be applied to the control system of foretell display screen.

The embodiment of the utility model provides an in, the control system of display screen includes: the FPGA and the target device transmit a first control signal and a second control signal through a first data line, so that the target device can control the second lamp panel unit group according to the first control signal and perform online upgrading according to the second control signal. Compared with the prior art, the target device is introduced, the IO port of the target device is connected with the lamp panel unit group, the target device controls the lamp panel unit group to display images, the number of the lamp panel unit groups which can be controlled by the whole control system is expanded, in addition, a new configuration file written into the target device is received through the FPGA, the new configuration file is sent to the target device, the target device is controlled to be upgraded on line, the number of data groups of the LED display unit is expanded, the LED lamp panel display resolution ratio is expanded, the technical effect of on-line upgrading of the device is achieved, and the technical problem that the loading size of a receiving card in the related technology is limited and the data group expansion requirement cannot be met is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the invention without undue limitation to the invention. In the drawings:

FIG. 1 is a schematic diagram of a receiving card according to the prior art;

fig. 2 is a schematic diagram of a control system for a display screen according to an embodiment of the present invention;

fig. 3 is a schematic diagram of an alternative receiving card according to an embodiment of the present invention; and

fig. 4 is a schematic diagram of internal modules of an alternative FPGA and CPLD according to an embodiment of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood, the technical solution of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts shall belong to the protection scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a system, article, or apparatus that comprises a list of elements is not necessarily limited to those elements explicitly listed, but may include other elements not expressly listed or inherent to such system, article, or apparatus.

First, the technical names and technical terms in the present invention are explained as follows:

the lamp panel unit group: also called as an LED driving unit, an LED module unit, can drive R, G, B three LEDs to be turned on or off.

Low voltage differential signaling: Low-Voltage Differential Signaling, abbreviated as LVDS, has a transmission rate generally above 155Mbps (approximately 77MHz), so that signals and the like are transmitted at a rate of several hundreds of Mbps on Differential PCB line pairs or balanced cables, and its Low Voltage amplitude and Low current drive output achieve Low noise and Low power.

Serial peripheral interface: a Serial Peripheral Interface, abbreviated as SPI, enables a single chip to communicate with various Peripheral devices in a Serial manner to exchange information.

Gigabit media independent interface: the Gigabit Media Independent Interface, GMII for short, adopts 8-bit data Interface, and has work clock of 125MHz, so that the transmission rate may reach 1000 Mbps.

Reduced gigabit media independent interface: reduced Gigabit Media Independent Interface, abbreviated as RGMII, adopts a 4-bit data Interface, has an operating clock of 125MHz, and transmits data simultaneously on a rising edge and a falling edge, so that the transmission rate can reach 1000 Mbps.

Complex programmable logic device: a Complex program Logic Device, CPLD for short, is mainly composed of three parts, namely a Logic block, a programmable interconnection channel and an I/O block.

Port physical layer: the Port Physical Layer, abbreviated as PHY, is a low-level hardware device for network communication and is responsible for gigabit network transceiving.

As shown in fig. 1, a core device for display control of a conventional receiving card 10 is composed of two PHYs 11, an MCU (micro controller Unit) 12, a Flash 13, and an FPGA (Field Programmable Gate Array) 21. The receiving card 10 can be connected with the LED display controller 20 through a gigabit network cable, the LED display controller 20 is connected with the upper computer 00, the upper computer 00 can transmit image data to be displayed to the PHY11 through the gigabit network cable through the LED display controller 20, the PHY11 transmits the received data to the MCU 12, and the MCU 12 writes the received image data into the Flash 13. When image data needs to be displayed, the MCU 12 reads data in the Flash 13, sends the read data to the FPGA 21, the FPGA 21 analyzes and caches the image data to an SDRAM (Synchronous Dynamic Random-Access Memory) 14, and finally transmits the image data to a first lamp panel unit group 31 in the LED display screen 30 through an R/G/B interface 15.

As can be seen from the above, the interface for outputting one group of R/G/B data signals is referred to as 1 group of data, 1 group of data can transmit independent R/G/B display control signals (image data), and 1 group of R/G/B display control signals can drive one lamp panel unit group, so that the more R/G/B data groups, the more lamp panel unit groups are driven.

According to the utility model provides an embodiment provides a control system of display screen.

Fig. 2 is a schematic diagram of a control system of a display screen according to an embodiment of the present invention, and as shown in fig. 2, the system includes:

the field editable gate array 21 is characterized in that a plurality of first ports 15 of the field editable gate array 21 are connected with a plurality of first lamp panel unit groups 31 in the display screen 30 in a one-to-one correspondence manner;

the target device 22 is connected with the field editable gate array 21 through a first data line 23, and the plurality of second ports 16 of the target device 22 are correspondingly connected with the plurality of second lamp panel unit groups 32 in the display screen 30 one by one;

the first data line 23 is configured to transmit a first control signal and a second control signal sent by the field editable gate array 21 to the target device 22, and the target device 22 is configured to control the plurality of second lamp panel unit groups based on the first control signal and perform online upgrade based on the second control signal.

The target device 22 may be any device with more extended I/O and is low in cost, and optionally, a CPLD is exemplified in the present invention. Furthermore, the CPLD may be located at one of the following positions: the receiving card connected with the display screen, the lamp panel of the display screen, and the multiport repeater (HUB) between the receiving card and the lamp panel, but the receiving card and the lamp panel are not limited to this, and can be arranged at other positions.

The first lamp panel unit group 31 and the second lamp panel unit group 32 may be different lamp panel unit groups in the LED display screen 30, the first lamp panel unit group 31 is connected to the FPGA 21, and is controlled by the FPGA 21, and may be regarded as an original lamp panel unit group, and the second lamp panel unit group 32 is connected to the CPLD22, and is controlled by the CPLD22, and may be regarded as a newly extended lamp panel unit group.

The first port 15 and the second port 16 may be R/G/B ports, each R/G/B port is connected to one lamp panel unit group, and the received display control signal may be transmitted to the lamp panel unit group to control the LEDs in the lamp panel unit group to emit light or stop emitting light.

The first data line 23 may be a data line used for transmitting a control signal between the FPGA 21 and the CPLD22, the first control signal may be a display control signal used for controlling the second lamp panel unit group 32, and the second control signal may be a control signal used for controlling updating of a configuration file of the CPLD22 itself, so as to ensure online updating of a program of the CPLD 22.

It should be noted that the FPGA 21 may not output the display control signal, that is, the FPGA 21 does not control the first lamp panel unit group 31, and only sends the first control signal and the second control signal.

In an optional embodiment, when the LED display screen 30 needs to be controlled to display an image, the FPGA 21 may receive the image that needs to be displayed, and divide the image that needs to be displayed into two sub-images based on the layout positions of the first lamp panel unit group 31 and the second lamp panel unit group 32 in the LED display screen 30, where the sub-image 1 is displayed by the first lamp panel unit group 31, and the sub-image 2 is displayed by the second lamp panel unit group 32. The FPGA 21 may generate two display control signals, i.e. the display control signal 1 and the display control signal 2 (i.e. the first control signal mentioned above), respectively, according to the two sub-images. The FPGA 21 transmits the display control signal 1 to the first lamp panel unit group 31 through the first port 15, and controls the first lamp panel unit group 31 to display the corresponding sub-image 1; the FPGA 21 transmits the display control signal 2 to the CPLD22, and after receiving the display control signal 2, the CPLD22 directly transmits the display control signal to the second lamp panel unit group 32 through the second port 16, so as to control the second lamp panel unit group 32 to display the corresponding sub-image 2.

In another optional embodiment, when the CPLD22 needs to be upgraded online, that is, a new configuration file needs to be written into the CPLD22 to update the configuration file of the CPLD22, the FPGA 21 may receive the upgrade program, that is, receive the new configuration file that needs to be written into the CPLD22, and send the second control signal carrying the new configuration file to the CPLD 22. After receiving the second control signal, the CPLD22 may determine that the configuration file needs to be updated, store the new configuration file carried in the second control signal into the corresponding storage space, and further automatically configure the CPLD22 based on the new configuration file, thereby implementing online upgrade of the CPLD 22.

Through the utility model discloses above-mentioned embodiment, the control system of display screen includes: the FPGA and the target device transmit a first control signal and a second control signal through a first data line, so that the target device can control the second lamp panel unit group according to the first control signal and perform online upgrading according to the second control signal. Compared with the prior art, the target device is introduced, the IO port of the target device is connected with the lamp panel unit group, the target device controls the lamp panel unit group to display images, the number of the lamp panel unit groups which can be controlled by the whole control system is expanded, in addition, a new configuration file written into the target device is received through the FPGA, and the new configuration file is sent to the target device, so that the target device is controlled to be upgraded on line, the technical effects of expanding the number of the data groups of the LED display units and expanding the display resolution of the LED lamp panel are achieved, the technical effect of upgrading the device on line is achieved, and the technical problems that the carrying size of a receiving card in the related art is limited and the data group expansion requirements cannot be met are solved.

Optionally, in the above embodiments of the present invention, the field-editable gate array 21 includes: the first transmission module is connected with the first data line and used for sending a first control signal and a second control signal based on a preset protocol, and the preset protocol comprises one of the following protocols: a low voltage differential signal protocol, a serial peripheral interface protocol, a gigabit media independent interface protocol, a reduced gigabit media independent interface protocol; the target device 22 includes: and the second transmission module is connected with the first data line and used for receiving the first control signal and the second control signal based on a preset protocol.

The preset protocols include, but are not limited to: LVDS protocol, SPI protocol, GMII protocol, RGMII protocol, etc., or may be other custom protocols. And the FPGA 21 and the CPLD22 carry out data transmission through a preset protocol.

For the FPGA 21, the first transmission module is configured to send the first control signal and the second control signal, and thus, the first transmission module may be a sending module; for the CPLD22, the second transmission module is used to receive the first control signal and the second control signal, and thus, the second transmission module may be a receiving module.

Optionally, in the above embodiments of the present invention, the field-editable gate array 21 further includes: the data receiving module is used for receiving the image data and the upgrading data; the data processing module is connected with the data receiving module and used for analyzing the image data and upgrading the data; and the first control module is connected with the data processing module and the first transmission module and used for generating a first control signal based on the analyzed image data and generating a second control signal based on the analyzed upgrading data.

The image data may be data sent to the receiving card 10 to control a lamp panel unit group in the LED display screen 30, and the upgrade data may be data for performing program update and upgrade on target data. The receiving card 10 obtains the image data and the upgrade data through the PHY11, that is, the image data and the upgrade data received by the FPGA 21 are sent according to a specific protocol, and therefore, a data processing module may be disposed inside the FPGA 21 for analyzing the received image data and the upgrade data.

It should be noted that the image processing may be realized not only by an image data processing module inside the FPGA 21, but also by an image data processing module outside the FPGA 21.

Optionally, in the above embodiment of the present invention, the control system further includes: the memory, field-editable gate array 21 further comprises: and the third control module is connected with the data processing module and the memory and used for storing the analyzed image data into the memory.

The memory may be, but is not limited to, the SDRAM 14 shown in fig. 1, and may be other memory devices. The third control module may be a memory control module inside the FPGA 21, and the module may cache the analyzed image data to the memory.

Optionally, in the above embodiments of the present invention, the field-editable gate array 21 includes: the first control module is connected with the first ports 15 and used for controlling the first lamp panel unit groups 31.

The original FPGA 21 on the receiving card may only transmit the first control signal and the second control signal, and may also control the opening and closing of the first lamp panel unit group 31 based on the analyzed image data, that is, the FPGA 21 may still output R/G/B.

Optionally, in the above embodiments of the present invention, as shown in fig. 3, the field-editable gate array 21 is connected to the target device 22 through the second data line 24, wherein the second data line 24 is used to transmit the state data of the target device to the field-editable gate array.

The second data line 24 may be a data line between the FPGA 21 and the CPLD22 for transmitting status data back to the CPLD 22. The state data may be data of the current state of the CPLD22, such as an operating state, a state of a controlled lamp panel unit group, and the like.

Optionally, in the above embodiments of the present invention, the target device 22 includes: the second transmission module is connected with the second data line 24 and used for sending the state data of the target device based on a preset protocol; the field-editable gate array 21 includes: and a first transmission module connected to the second data line 24 for receiving the status data based on a predetermined protocol.

For the CPLD22, the second transmission module is used to transmit the status data of the CPLD22, and thus, the second transmission module may be a transmission module; for the FPGA 21, the first transmission module is used to receive status data, and thus the first transmission module may be a receiving module.

A preferred embodiment of the present invention will be described in detail with reference to fig. 3 and 4, wherein the target device 22 is illustrated as a CPLD 22.

As shown in fig. 3, 1 CPLD22 may be added to the receiving card 10, but the invention is not limited thereto, and any device with more expansion I/O with low cost may be provided. Moreover, the CPLD22 may be disposed not only on the receiving card 10 but also on the lamp panel, and may also be disposed on the HUB between the receiving card and the lamp panel. The FPGA 21 and the CPLD22 are connected through a first data line 23 and a second data line 24. The original FPGA 21 can still output R/G/B through the R/G/B interface 15 to control the first lamp panel unit group 31 in the LED display screen 30 to work, but not limited thereto, the FPGA 21 itself may not output R/G/B, and only transmits a "specific signal" to the CPLD22, where the "specific signal" may use the following protocol for data transmission: LVDS transmission, SPI transmission, RGMII transmission, GMII transmission, etc., or a custom protocol, wherein the "specific signal" includes a display control signal that the CPLD22 controls the second lamp panel unit group 32, an upgrade control signal that the CPLD22 itself updates configuration information, and a return signal that reads back the status of the CPLD 22. After receiving the display control signal, the CPLD22 may output R/G/B through the R/G/B interface 16 to control the second lamp panel unit group 32 in the LED display screen 30 to work; after receiving the upgrade control signal, the CPLD22 may perform online program upgrade based on the upgrade control signal; after receiving the return signal, the CPLD22 may acquire the current state and return it to the FPGA 21.

It should be noted that, as in the prior art, the receiving card 10 may be connected to the LED display controller 20 through a gigabit network cable, the LED display controller 20 is connected to the upper computer 00, the upper computer 00 may transmit image data to be displayed to the PHY11 through the gigabit network cable through the LED display controller 20, the PHY11 transmits the received data to the MCU 12, and the MCU 12 writes the received image data into the Flash 13. When image data needs to be displayed, the MCU 12 reads the data in the Flash 13, sends the read data to the FPGA 21, the FPGA 21 analyzes the image data and buffers the image data to the SDRAM 14, and finally the FPGA 21 controls the first lamp panel unit 31 and the CPLD22 controls the second lamp panel unit 32.

As shown in fig. 4, the FPGA 21 may include therein: data reception 211, image data processing 212, first output control 213, transmission/reception 214, and memory control 215, wherein the data reception 211, the image data processing 212, the first output control 213, and the transmission/reception 214 are connected in this order, and the memory control 215 is connected to the image data processing 212 and the SDRAM 14. CPLD22 may include internally: a receive/backhaul 221 and a second output control 222, wherein the transmit/receive 214 is coupled to the receive/backhaul 221 and the receive/backhaul 221 is coupled to the second output control 222. The data reception 211 receives image data transmitted by the PHY 11; the image data processing 212 parses the received image data and caches it to the SDRAM 14 through the memory control 215, and may send the image data to the CPLD22 through the transmit/receive 214; the first output control 213 and the second output control 222 are respectively used for controlling the lamp panel unit groups connected with the FPGA 21 and the CPLD 22; the data receiver 211 can also receive an upgrade program transmitted by the PHY11, and transmit a control signal for controlling the CPLD22 to perform online upgrade to the CPLD22 through the transmitter/receiver 214; the receive/return 221 may also send the collected status data of the CPLD22 to the FPGA 21.

It should be noted that both reception and transmission may exist, or only 1 of them may exist, where the FPGA 21 may only have transmission, the CPLD22 may only have reception, the FPGA 21 may also have 2, and the CPLD22 may also have 2.

By the scheme, the hardware form of the data group number of the receiving card can be expanded through the CPLD or other devices, the function on-line upgrade of the CPLD is realized through the FPGA, and the signal is output to drive the opposite-end device in the mode of LVDS/SPI/UART/RGMII/GMII, so that the data group number of the LED display unit is expanded, and the display resolution of the LED lamp panel is expanded finally.

According to the utility model provides an embodiment provides a receive card. The receiving card is applied to the control system of the display screen in the above embodiment.

Note that, in this embodiment, the target device is provided only on the receiving card.

In the above embodiments of the present invention, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A control system for a display screen, comprising:

the field editable gate array comprises a plurality of first ports which are connected with a plurality of first lamp panel unit groups in the display screen in a one-to-one correspondence manner;

the target device is connected with the field editable gate array through a first data line, and a plurality of second ports of the target device are connected with a plurality of second lamp panel unit groups in the display screen in a one-to-one correspondence manner;

the first data line is used for transmitting a first control signal and a second control signal sent by the field editable gate array to the target device, and the target device is used for controlling the plurality of second lamp panel unit groups based on the first control signal and carrying out online upgrading based on the second control signal.

2. The system of claim 1,

the field-editable gate array comprises: a first transmission module, connected to the first data line, configured to send the first control signal and the second control signal based on a preset protocol, where the preset protocol includes one of the following: a low voltage differential signal protocol, a serial peripheral interface protocol, a gigabit media independent interface protocol, a reduced gigabit media independent interface protocol;

the target device includes: and the second transmission module is connected with the first data line and used for receiving the first control signal and the second control signal based on the preset protocol.

3. The system of claim 2, wherein the field-editable gate array further comprises:

the data receiving module is used for receiving the image data and the upgrading data;

the data processing module is connected with the data receiving module and used for analyzing the image data and the upgrading data;

and the first control module is connected with the data processing module and the first transmission module and used for generating the first control signal based on the analyzed image data and generating the second control signal based on the analyzed upgrading data.

4. The system of claim 3, wherein the control system further comprises: a memory, the field-editable gate array further comprising:

and the third control module is connected with the data processing module and the memory and is used for storing the analyzed image data to the memory.

5. The system of claim 1, wherein the field-editable gate array comprises:

and the first control module is connected with the first ports and used for controlling the first lamp panel unit groups.

6. The system of claim 1, wherein the field-editable gate array is connected to the target device via a second data line, wherein the second data line is configured to transmit the state data of the target device to the field-editable gate array.

7. The system of claim 6,

the target device includes: the second transmission module is connected with the second data line and used for transmitting the state data through a preset protocol;

the field-editable gate array comprises: and the first transmission module is connected with the second data line and used for receiving the state data through the preset protocol.

8. The system of claim 1, wherein the target device is a complex programmable logic device.

9. The system of claim 1, wherein the target device is disposed at a location that is one of: and the receiving card is connected with the display screen, the lamp panel of the display screen, and the multi-port transponder between the receiving card and the lamp panel.

10. A receiving card, characterized in that it is applied to a control system of a display screen according to any one of claims 1 to 8.