CN213305379U - Coupler and signal transmission system - Google Patents

Abstract

The application provides a coupler and a signal transmission system, and relates to the technical field of isolated signal transmission. The coupler comprises a first voltage domain, a second voltage domain and isolation devices, wherein the first voltage domain and the second voltage domain are connected through the isolation devices, the first voltage domain comprises a plurality of first signal ports, the second voltage domain comprises a plurality of second signal ports, and the number of the isolation devices is smaller than that of the first signal ports or the second signal ports; the first voltage domain is used for generating an encoding signal according to data of part or all of the first signal ports and transmitting the encoding signal to the second voltage domain; the second voltage domain is used for receiving the coded signal and decoding the coded signal so as to output the decoded signal through the second signal port. The coupler and the signal transmission system have the advantage of low cost.

Description

Coupler and signal transmission system

Technical Field

The application relates to the technical field of isolated signal transmission, in particular to a coupler and a signal transmission system.

Background

The digital isolator adopts a transformer or a capacitor integrated with a chip as an isolating device to transmit data. Compared with the traditional optical coupler, the digital isolator has the advantages of low power consumption, long service life, stable performance and the like.

However, in systems where isolation is required, there are typically multiple isolated signal paths that carry control signals from the low-voltage side to the high-voltage side, or from the high-voltage side to the low-voltage side. On this basis, when the digital isolator is used for isolation, each signal channel needs a set of isolation devices (such as capacitors or transformers), and due to the fact that the number of channels is large, the transceiver circuit and the isolation devices occupy large areas and the number of the isolation devices is large, and the cost of the digital isolator is high.

In summary, the digital isolator provided in the prior art has a high cost and a large area.

SUMMERY OF THE UTILITY MODEL

The present application aims to provide a coupler and a signal transmission system, so as to solve the problems of high cost and large area of a digital isolator in the prior art.

In order to achieve the above purpose, the embodiments of the present application employ the following technical solutions:

in one aspect, embodiments of the present application provide a coupler, where the coupler includes a first voltage domain, a second voltage domain, and an isolation device, where the first voltage domain and the second voltage domain are connected by the isolation device, the first voltage domain includes a plurality of first signal ports, the second voltage domain includes a plurality of second signal ports, and the number of the isolation devices is less than the number of the first signal ports or the second signal ports; the first voltage domain is used for generating an encoded signal according to data of part or all of the plurality of first signal ports and transmitting the encoded signal to the second voltage domain; and the second voltage domain is used for receiving the coded signal and decoding the coded signal so as to output the decoded signal through part or all of the second signal ports.

Optionally, the first voltage domain is further configured to generate a trigger signal before sending the encoded signal, and send the trigger signal to the second voltage domain, and the second voltage domain is configured to reset a clock of the second voltage domain after receiving the trigger signal, so that the clock of the second voltage domain is aligned with the clock of the first voltage domain.

Optionally, the second voltage domain includes a receiver and a decoding circuit, the receiver is respectively connected to the isolation device and the decoding circuit, the receiver further includes a first threshold comparator and a second threshold comparator, both of which are respectively connected to the isolation device and the decoding circuit, wherein a threshold of the first threshold comparator is greater than a threshold of the second threshold comparator; the first threshold comparator and the second threshold comparator are both used for receiving a differential signal transmitted by the isolation device, and the decoding circuit is used for determining that the differential signal is the trigger signal when the differential signal is greater than the second threshold and smaller than the first threshold.

Optionally, the second voltage domain includes a decoding circuit, the decoding circuit includes a nand gate, a first not gate and a second not gate, a first input of the nand gate is configured to receive a trigger signal, a second input of the nand gate is connected to an output of the second not gate, an output of the nand gate is connected to an input of the first not gate, and an output of the first not gate is connected to an input of the second not gate, so that a ring oscillator is formed by the nand gate, the first not gate and the second not gate, and the ring oscillator is used for resetting a clock.

Optionally, the first voltage domain includes an encoding circuit and a transmitter, the second voltage domain includes a decoding circuit and a receiver, an input terminal of the encoding circuit is connected to some or all of the plurality of first signal ports, and an output terminal of the encoding circuit is connected to the isolation device; the input end of the receiver is connected with the isolation device, the output end of the receiver is connected with the input end of the decoding circuit, and the output end of the decoding circuit is connected with part or all of the second signal ports.

Optionally, the encoding circuit and the transmitter are integrated on the same chip, and the decoding circuit and the receiver are integrated on another chip.

Optionally, the second voltage domain is further configured to generate an encoded signal according to data of some or all of the second signal ports, and transmit the encoded signal to the first voltage domain; the first voltage domain is used for receiving the coded signal and decoding the coded signal so as to output the decoded signal through the first signal port.

Optionally, the first voltage domain includes a first codec circuit and a first transceiver, the second voltage domain includes a second codec circuit and a second transceiver, the first codec circuit is connected to the first transceiver and some or all of the first signal ports, the second codec circuit is connected to the second transceiver and some or all of the second signal ports, and the first transceiver is connected to the second transceiver through the isolation device.

Optionally, the first voltage domain comprises a first codec circuit, a first receiver and a first transmitter, the second voltage domain comprises a second codec circuit, a second receiver and a second transmitter, and the isolation device comprises a first isolation device and a second isolation device; the first codec circuit is connected to some or all of the plurality of first signal ports, the first receiver, and the first transmitter, the second codec circuit is connected to some or all of the plurality of second signal ports, the second receiver, and the second transmitter, the first transmitter is connected to the second receiver through the first isolation device, and the second transmitter is connected to the first receiver through the second isolation device.

In another aspect, an embodiment of the present invention further provides a signal transmission system, where the signal transmission system includes a first power source, a second power source, and the coupler, where the first power source is connected to the first voltage domain and is configured to supply power to the first voltage domain, and the second power source is connected to the second voltage domain and is configured to supply power to the second voltage domain.

Compared with the prior art, the method has the following beneficial effects:

the embodiment of the application provides a coupler and a signal transmission system, wherein the coupler comprises a first voltage domain, a second voltage domain and an isolation device, the first voltage domain is connected with the second voltage domain through the isolation device, the first voltage domain comprises a plurality of first signal ports, the second voltage domain comprises a plurality of second signal ports, and the number of the isolation device is smaller than that of the first signal ports or the second signal ports; the first voltage domain is used for generating an encoding signal according to data of part or all of the first signal ports and transmitting the encoding signal to the second voltage domain; the second voltage domain is used for receiving the coded signal and decoding the coded signal so as to output the decoded signal through the second signal port. In the coupler provided by the application, the number of the isolation devices is smaller than that of the first signal ports or that of the second signal ports, so that the isolation devices can be shared by a plurality of signal ports, the occupied area and the number of the isolation devices are reduced, and the manufacturing cost of the coupler is reduced.

In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and it will be apparent to those skilled in the art that other related drawings can be obtained from the drawings without inventive effort.

FIG. 1 is a schematic diagram of a digital isolator having 4 isolated signal paths.

FIG. 2 is another schematic diagram of a digital isolator having 4 isolated signal paths.

Fig. 3 is a first schematic diagram of a coupler according to an embodiment of the present disclosure.

Fig. 4 is a second schematic diagram of a coupler according to an embodiment of the present disclosure.

FIG. 5 is a timing diagram of clocks in the first and second voltage domains.

Fig. 6 is a schematic diagram illustrating a timing relationship between clocks in a first voltage domain and a second voltage domain after a trigger signal is set according to an embodiment of the present disclosure.

Fig. 7 is a block diagram of a receiver according to an embodiment of the present disclosure.

Fig. 8 is a timing diagram of a receiver according to an embodiment of the present application.

Fig. 9 is another timing diagram of a receiver according to an embodiment of the present application.

Fig. 10 is a schematic diagram of a timing resetting scheme according to an embodiment of the present application.

Fig. 11 is a timing diagram of a timing resetting scheme according to an embodiment of the present application.

Fig. 12 is a third schematic diagram of a coupler according to an embodiment of the present application.

Fig. 13 is a timing diagram of fig. 12 according to an embodiment of the present application.

Fig. 14 is a fourth schematic diagram of a coupler according to an embodiment of the present application.

In the figure: 100-a coupler; 110 — a first voltage domain; 111-an encoding circuit; 112-a transmitter; 113-a first codec circuit; 114-a first transceiver; 115-a first transmitter; 116-a first receiver; 120-a second voltage domain; 121-a decoding circuit; 122-a receiver; 123-a second codec circuit; 124-a second transceiver; 135-a second receiver; 136-a second transmitter; 130-an isolation device; 131-first isolation devices; 132-second isolation devices.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found in use of products of the application, and are used only for convenience in describing the present application and for simplification of description, but do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present application.

In the description of the present application, it is also to be noted that, unless otherwise explicitly specified or limited, the terms "disposed" and "connected" are to be interpreted broadly, e.g., as being either fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

As described in the background, digital isolators employ a chip-integrated transformer or capacitor as the isolation device to transmit data. Compared with the traditional optical coupler, the digital isolator has the advantages of low power consumption, long service life, stable performance and the like.

However, in systems where isolation is required, there are typically multiple isolated signal paths that carry control signals from the low-voltage side to the high-voltage side, or from the high-voltage side to the low-voltage side. When the optical coupler is used, each channel corresponds to one optical coupler generally, and each optical coupler is packaged by using a separate plastic package body. When using a digital isolator, a single plastic package is typically used, but the integrated circuit chip in the plastic package typically contains multiple independent isolation channels, e.g., 4-6 independent isolation channels can typically be placed in a single plastic package of SOP 16.

Because the number of channels is large, the transceiver circuit and the isolation devices in the digital isolator occupy larger areas and the number of the isolation devices is large, so that the digital isolator is higher than an optical coupler in cost.

For example, referring to fig. 1 and 2, a digital isolator having 4 isolated signal channels is shown, wherein TX is Transmit (TX) Data, i.e., transmit Data, and RX is Receive (RX) Data, i.e., receive Data. As can be seen from the figure, when the digital isolator includes 4 isolation signal channels, no matter whether a transformer or a capacitor is used as the isolation device, 4 isolation devices are required. On one hand, the number of the isolation devices is large, so that the cost of the digital isolator is high; on the other hand, the area occupied by the isolation device is large, and further layout cost is increased during circuit layout.

Similarly, when the number of the isolation signal channels is 6, the number of the isolation devices is also 6, and when the number of the isolation signal channels is 8, the number of the isolation devices is also 8.

It can be seen that as the number of isolated signal channels increases, the number of isolation devices increases, resulting in an increase in the cost of the digital isolator.

In view of the above, in order to solve the above problems, the present application provides a coupler, which achieves the purpose of reducing isolation devices by sharing one isolation device for two or more isolation signal paths, thereby achieving the effect of reducing the cost of the coupler.

The following is an exemplary description of the coupler provided in the embodiments of the present application:

as an alternative implementation, referring to fig. 3, the coupler 100 includes a first voltage domain 110, a second voltage domain 120, and an isolation device 130, where the first voltage domain 110 and the second voltage domain 120 are connected by the isolation device, the first voltage domain 110 includes a plurality of first signal ports, the second voltage domain 120 includes a plurality of second signal ports, and the number of the isolation device 130 is smaller than the number of the first signal ports or the number of the second signal ports. The first voltage domain 110 is configured to generate an encoded signal according to data of some or all of the plurality of first signal ports, and transmit the encoded signal to the second voltage domain 120, and the second voltage domain 120 is configured to receive the encoded signal and decode the encoded signal, so as to output the decoded signal through the second signal port.

As an implementation manner, the first voltage domain 110 is one end for transmitting a signal, and the second voltage domain 120 is one end for receiving a signal. And in the whole signal transmission system, two power supply voltages are further included, which are the first power supply voltage VDD1 and the second power supply voltage VDD2, respectively. The first power supply voltage VDD1 supplies power to the first voltage domain 110, so that the first voltage domain 110 realizes signal input and encoding, and the second power supply voltage VDD2 supplies power to the second voltage domain 120, so that the second voltage domain 120 realizes signal encoding and output. On the basis, the first signal port is a digital input port, and the second signal port is a digital output port. Generally, the number of first signal ports is equal to the number of second signal ports.

As an implementation manner, when the first voltage domain 110 performs signal encoding, all the first signal ports are sampled, and the sampled signals are encoded into a serial signal. The serial signal is a signal obtained by integrating signals of a plurality of ports into a serial signal and transmitting the serial signal bit by bit through the isolation device 130. For example, when the number of the first signal ports is 4, wherein a signal to be transmitted by the first signal port is "1", a signal to be transmitted by the second signal port is "0", a signal to be transmitted by the third signal port is "1", and a signal to be transmitted by the fourth signal port is "0", after encoding, the signals of the four signal ports may be encoded into a serial signal "1010", and then transmitted to the second voltage domain 120.

It should be noted that the encoded serial signal may be transmitted to the second voltage domain 120 through a single isolated signal channel, and at the same time, after receiving the serial signal, the second voltage domain 120 decodes the serial signal and outputs the decoded signal through the second signal port.

In this embodiment, the number of the isolation devices 130 may be smaller than the number of the first signal ports or the second signal ports, in other words, the number of the isolation signal channels may be smaller than the number of the first signal ports or the second signal ports, so as to achieve the effect of reducing the cost. For example, when the number of the first signal ports and the second signal ports is 8, the number of the isolation devices 130 may be only 5, or 3, or 1, etc. When the number of the isolation devices 130 is one, the serial signal generated by the first voltage domain 110 after sampling and encoding the 8 first signal ports may be transmitted to the second voltage domain 120 through the isolation devices 130. When the number of the isolation devices 130 is greater than one, for example, 3, serial signals generated by the first voltage domain 110 after sampling and encoding 8 first signal ports may be transmitted to the second voltage domain 120 through any one of the isolation devices 130, or the serial signals are transmitted to the second voltage domain 120 through the first isolation device 130 in one period and transmitted to the second voltage domain 120 through the second isolation device 130 in another period, which is not particularly limited.

The isolation device 130 described in this embodiment may be an isolation device 130 such as a transformer or a capacitor.

As an implementation manner, referring to fig. 4, the first voltage domain 110 includes an encoding circuit 111 and a transmitter 112, the second voltage domain 120 includes a decoding circuit 121 and a receiver 122, an input terminal of the encoding circuit 111 is connected to some or all of the plurality of first signal ports, and an output terminal of the encoding circuit 111 is connected to the isolation device 130; an input terminal of the receiver 122 is connected to the isolation device 130, an output terminal of the receiver 122 is connected to an input terminal of the decoding circuit 121, and an output terminal of the decoding circuit 121 is connected to some or all of the plurality of second signal ports. Optionally, the output of the encoding circuit 111 is connected to a first terminal of the isolation device 130, and the input of the receiver 122 is connected to a second terminal of the isolation device 130.

By this arrangement, the codec circuit 121 of the first voltage domain 110 can sample each first signal port and encode it into a serial signal, and then transmit the serial signal to the receiver 122 of the second voltage domain 120 through the transmitter 112 circuit via a single isolation channel, and then restore the serial signal to the second signal port of the second voltage domain 120 through the decoder circuit 121.

Optionally, in the isolated signal transmission system, since there are the first voltage domain 110 and the second voltage domain 120 that need to be electrically isolated, in order to ensure the electrical isolation between the two voltage domains, the encoding circuit 111 and the transmitter 112 are integrated on the same chip, and the decoding circuit 121 and the receiver 122 are integrated on another chip.

It can be understood that the working environments of the two chips are very different, and on one hand, the supply voltages of the two chips cannot be completely equal due to the different voltage domains; on the other hand, the operating temperatures of the two chips may also be different, which may cause different critical performances of the two chips, such as different signal transmission delays and different clock frequencies.

For example, referring to fig. 5, the clock signal of the chip in the first voltage domain 110 at the power supply voltage and temperature has a period T1, and the clock signal of the chip in the second voltage domain 120 at the power supply voltage and temperature has a period T2. The signals transmitted by the first voltage domain 110 are on the same chip, so the clocks have a definite timing relationship.

For example, on the transmitter 112 chip, the rising edge of the clock is designed to be aligned with the center of the transmitted signal (as indicated by the open arrow). The clock period of the second voltage domain 120 is different from the clock period of the first voltage domain 110, e.g., T2 is 10% greater or 10% less than T1, etc., and the receiver 122 also receives signals on the rising edge of the clock of the second voltage domain 120 (as indicated by the solid arrows). In the first few bits, the solid arrow can still receive near the center of the transmitted signal, but as the transmission data increases, the phase error starts to accumulate, and reaches a certain number of bits, the timing of the receiving time is mismatched with the transmitted signal, resulting in signal transmission errors. Although the difference between T1 and T2 can be minimized by optimizing the circuit design, the difference between the operating environments determines that perfect matching of the two clocks is impossible due to the fact that the two circuits are in electrically isolated voltage domains, and errors are accumulated to a level that causes errors.

In other words, since the first voltage domain 110 and the second voltage domain 120 have different environments, the periods T1 and T2 cannot be completely the same all the time, and therefore, when one bit of data is transmitted, the phase error between the two is | T2-T1 |; after passing through two bits of data, the error of the two phases is 2| T2-T1|, and after passing through three bits of data, the error of the two phases is 3| T2-T1| …, and so on, the errors are gradually accumulated.

In addition to the problem of unequal clock periods caused by the environments such as the supply voltages and temperatures of the first voltage domain 110 and the second voltage domain 120, the supply voltages of the first voltage domain 110 and the second voltage domain 120 may change with time during the operation process, thereby causing clock changes, which results in a larger difference between the period T1 of the first voltage domain 110 and the period T2 of the second voltage domain 120.

For example, if the first voltage domain 110 is always operating at 5V with a clock period of 10ns, and the second voltage domain 120 is always operating at 3V with a clock period of 11ns, then the period of the second voltage domain 120 is definitely longer (slower) than that of the first voltage domain 110. However, it may also happen that the supply voltage of the first voltage domain 110 fluctuates randomly between 3-5V, and the supply voltage of the second voltage domain 120 also fluctuates randomly between 3-5V, which in turn results in that there is no definite fast-slow relationship between the clock T1 of the first voltage domain 110 and the clock T2 of the second voltage domain 120, so that the phase error is large, which in turn results in errors.

In view of this, as an implementation manner, the first voltage domain 110 can further generate a trigger signal before sending the encoded signal and send the trigger signal to the second voltage domain 120, and the second voltage domain 120 is configured to reset the clock of the second voltage domain 120 after receiving the trigger signal, so that the clock of the second voltage domain 120 is aligned with the clock of the first voltage domain 110.

In other words, the turning on of the clock of the second voltage domain 120 is controlled by the trigger signal of the first voltage domain 110. Since the error between the first voltage domain 110 and the second voltage domain 120 is gradually accumulated, that is, the error is larger and larger until the error is larger than a certain value, finally causing an error. By setting the trigger signal and resetting the clock after the second voltage domain 120 receives the trigger signal, the clocks of the second voltage domain 120 and the second voltage domain 120 are aligned at one time, and the error of the clocks of the first voltage domain 110 and the second voltage domain 120 is cleared, so that the coupler 100 can work continuously and cannot make mistakes.

For example, referring to fig. 6, taking transmission of a 4-bit signal as an example, at a specified time of the clock of the first voltage domain 110, the transmitter 112 of the first voltage domain 110 sends a trigger signal, and the second voltage domain 120 resets the clock of the second voltage domain 120 after receiving the trigger signal, at this time, the clock of the second voltage domain 120 is aligned with the clock of the first voltage domain 110 once, and an error accumulated due to a difference between two clock periods is cleared after the clock is reset, so that the coupler 100 is ensured not to have an error during continuous operation.

After the first voltage domain 110 transmits the trigger signal, normal data bits, such as the illustrated 4 bits, begin to be transmitted, and the clock phase of the second voltage domain 120 is no longer important after the data transmission is completed, entering an inactive period. Since the number of bits transmitted is known, the point in time to enter the inactive period is determined, e.g. 4 bits are transmitted, i.e. 4 × T2 after the trigger signal. Here, it should be noted that the number of bits to be transmitted is related to the number of first signal ports, that is, when the number of first signal ports is 4, the number of bits to be transmitted after the trigger signal is 4, and when the number of first signal ports is 8, the number of bits to be transmitted after the trigger signal is 8.

And, optionally, during the inactive period, the clock of the second voltage domain 120 has two processing methods, one is to turn it off to reduce power consumption; the other is to make it continue to work, but reset the next time the trigger signal comes, which is not limited herein.

It will be appreciated that in the above implementation, at some point in time corresponding to the clock of the first voltage domain 110, the trigger signal of the transmitter 112 is sent and transmitted through the isolation device 130 to the receiver 122, and the clock is reset (restarted from an off state or reset edge timing) by the receiver 122 upon receiving the trigger signal. After sending the trigger signal, the transmitter 112 starts to transmit data bits, and since the isolated signal transmission system needs to transmit a few bits, for example, 2-10 bits, a certain error between T2 and T1 can be allowed, and as long as the size of the error N x (T2-T1) does not exceed a certain proportion of a single bit, for example, 0.3 × T1, the timing of the transmission can be guaranteed to be correct, where N represents the number of bits. Alternatively, the clock error can be controlled to within 5% by appropriate circuit design.

That is, in the present embodiment, with the clock of the first voltage domain 110 as a reference, the time when the first voltage domain 110 sends the trigger signal and the time when the data bit is subsequently transmitted are determined, and the accuracy of data transmission can be ensured only by controlling the clock error between the clock of the second voltage domain 120 and the clock error of the first voltage domain 110 within a range that can be realized by design. Therefore, the first voltage domain 110 sends the trigger signal to the second voltage domain 120, and the second voltage domain 120 resets the clock after receiving the trigger signal, so that the transmission timing sequence of the first voltage domain 110 and the second voltage domain 120 can be always correct, and the stable operation of the coupler 100 is further ensured. Meanwhile, the digital circuit can work at a very high frequency, the width of each bit is in ns level, so that the delay caused by coding is smaller than that of the traditional optical coupler, and the transmission characteristic of the system cannot be degraded when the traditional optical coupler is replaced.

Meanwhile, it should be noted that the form and the type of the trigger signal are many, and the embodiment of the present application does not limit the specific form and the type of the trigger signal as long as the trigger signal has a predetermined characteristic and can be recognized by the receiver 122 of the second voltage domain 120.

For example, a specific identification code can be used as a start bit for calibration, so as to achieve the purpose of transmitting the trigger signal. As is common in the art, a fixed bit string "0110" is transmitted as a scaling of the start bit, using the digital signal as a scaling. This approach can result in significant waste of bandwidth. For example, if the bits to be transmitted are only 4 bits and the start marker bit is also 4 bits, half of the available bandwidth of the system is wasted.

Thus, as an alternative implementation, the present application uses a combination of an analog signal and a digital signal as a scaling of the start bit. Referring to fig. 7, the receiver 122 further includes a first threshold comparator and a second threshold comparator, both of which are respectively connected to the isolation device 130 and the decoding circuit 121, wherein the threshold of the first threshold comparator is greater than the threshold of the second threshold comparator; the first threshold comparator and the second threshold comparator are both configured to receive the differential signal transmitted through the isolation device 130, and the decoding circuit 121 is configured to determine that the differential signal is a trigger signal when the differential signal is greater than the second threshold and smaller than the first threshold. The first threshold is for a normally transmitted digital signal, and the second threshold is for a trigger signal, i.e. a threshold for an analog signal.

As shown in fig. 7, the differential signal transmitted from the isolation device 130 enters the receiver 122. The receiver 122 includes a first threshold comparator and a second threshold comparator having a first threshold and a second threshold, respectively. The threshold described herein, which may include a pulse width threshold and a pulse amplitude threshold, may be determined for different isolation devices 130.

If the pulse width is used as a mark, as shown in fig. 8, a shorter pulse can be identified because the second threshold has a smaller threshold. If the width of the fourth pulse signal is shorter than that of the normal digital signal, the fourth pulse signal cannot be identified by the first threshold comparator, so that the fourth pulse signal is processed by the first threshold comparator to output 0; but the threshold of the second threshold comparator is smaller and shorter pulses can be identified and therefore identified as 1. From this difference in output, the subsequent logic circuit can determine that a trigger signal is present.

As shown in fig. 9, if the pulse amplitude is used as a flag, for example, the signal amplitude of the fourth bit is small, the first threshold comparator with a larger threshold value cannot recognize the signal, but the second threshold comparator with a lower threshold value can recognize the signal, and the subsequent logic circuit can also determine that the trigger signal is present according to the difference of the outputs.

It should be noted that, due to the influence of noise, temperature, voltage, and process in the system, in order to ensure reliability, the second threshold may be 50% less than the first threshold, so as to ensure effective identification of the trigger signal.

On this basis, the scheme of clock resetting can also be diversified. As an implementation manner, please refer to fig. 10, the decoding circuit 121 includes a nand gate, a first not gate and a second not gate, a first input end of the nand gate is used for receiving the trigger signal, a second input end of the nand gate is connected to an output end of the second not gate, an output end of the nand gate is connected to an input end of the first not gate, an output end of the first not gate is connected to an input end of the second not gate, so as to form a ring oscillator through the nand gate, the first not gate and the second not gate, and perform clock resetting by using the ring oscillator.

When the decoding circuit 121 receives the enable signal, the first input terminal of the nand gate inputs 1; when the decoding circuit 121 does not receive the enable signal, the first input terminal of the nand gate inputs 0. When the first input end of the NAND gate inputs 1, the NAND gate is equivalent to an inverter, the circuit is a ring oscillator, when the first input end inputs 0, A necessarily outputs 1, B is set to 0 and C is set to 1, regardless of the logic state of C. The entire oscillator stops operating. When EN changes from 0 to 1, C-1 sets a to 0 after a delay, and then the clock resumes oscillation according to the principle of a ring oscillator. The clock signal is recovered from 0 at a certain delay after the trigger signal changes from 0 to 1, i.e. the phase of the clock is reset each time the trigger signal goes from 0 to 1. A timing diagram of this manner of clock resetting is shown in fig. 11.

On the basis of the above implementation, the second voltage domain 120 may also generate an encoded signal according to signals of some or all of the second signal ports, and transmit the encoded signal to the first voltage domain 110; the first voltage domain 110 receives the encoded signal and decodes the encoded signal to output the decoded signal through the first signal port. In other words, not only can signals be transmitted to the second voltage domain 120 via the first voltage domain 110, but signals can also be transmitted to the first voltage domain 110 via the second voltage domain 120. For example, during the last time period, the first voltage domain 110 transmits a signal to the second voltage domain 120, and during the current time period, the second voltage domain 120 transmits a signal to the first voltage domain 110; in the next time period, the signal is again transmitted through the first voltage domain 110 to the second voltage domain 120.

In this embodiment, two implementation manners are provided to realize bidirectional transmission of signals:

first, referring to fig. 12, the first voltage domain 110 includes a first codec circuit 113 and a first transceiver 114, the second voltage domain 120 includes a second codec circuit 123 and a second transceiver 124, the first codec circuit 113 is respectively connected to the first transceiver 114 and some or all of the plurality of first signal ports, the second codec circuit 111 is respectively connected to the second transceiver 124 and some or all of the plurality of second signal ports, and the first transceiver 114 is connected to the second transceiver 124 through an isolation device 130. I.e., between the first voltage domain 110 and the second voltage domain 120, a bi-directional transmission of signals is achieved through the single isolation device 130.

As shown in fig. 13, for example, taking the first transceiver 114 as an example of being in the transmitting state first, when the first transceiver 114 is in the transmitting state, the operation principle is the same as the above implementation manner, and details are not repeated here. When the data transmission of the first voltage domain 110 is completed, the transceiver of the first voltage domain 110 changes from the transmitting state to the receiving state (either immediately or after a specified time, for example, waiting for a cycle to switch again after the last bit is transmitted). The delay from the transmission of the last bit to the transition to the receive state is TD 1. In the figure, TD1 ═ T1. Other times may be selected, for example, TD1 ═ 0.5 × T1, TD1 ═ 2 × T1, and the like, which is not particularly limited.

The second transceiver 124 is in a receive state when the first transceiver 114 is in a transmit state, and transitions from the receive state to the transmit state after receiving a known number of bits. The delay from receiving the last bit to transitioning to the transmit state is TD 2. For example, TD2 is 1.5 × T2. In other words, it is necessary to ensure that when the second transceiver 124 enters the transmitting state, the first transceiver 114 is already in the receiving state, i.e., TD2 is greater than TD 1.

After the second voltage domain 120 enters the transmitting state, a trigger signal is sent to the first voltage domain 110, and the clock signal of the first voltage domain 110 is reset by the trigger signal received by the first voltage domain 110. The subsequent process is the same as the above implementation, except that the direction of the whole process is reversed, and a signal is transmitted from the second voltage domain 120 to the first voltage domain 110. The processing after the data bit transmission is also similar, the second voltage domain 120 enters the receiving state first, the first voltage domain 110 enters the transmitting state later, the direction is switched again, and the first voltage domain 110 transmits a signal to the second voltage domain 120, which is not described again here.

Thus, in this implementation, there are different signal transmission directions at different time periods from the perspective of the isolation device 130. In either the first voltage domain 110 or the second voltage domain 120, the clocks are not continuous but are alternately reset by the opposite clock, and the two clocks mutually eliminate the accumulation of phase errors of the opposite clock, so that the coupler 100 can continuously and stably operate.

Secondly, referring to fig. 14, the first voltage domain 110 includes a first codec circuit 113, a first receiver 116 and a first transmitter 115, the second voltage domain 120 includes a second codec circuit 123, a second receiver 135 and a second transmitter 136, and the isolation device 130 includes a first isolation device 131 and a second isolation device 132; the first codec circuit 113 is connected to the plurality of first signal ports, the first receiver 116, and the first transmitter 115, the second codec circuit 123 is connected to some or all of the plurality of second signal ports, the second receiver 135, and the second transmitter 136, the first transmitter 115 is connected to the second receiver 135 through the first isolation device 131, and the second transmitter 136 is connected to the first receiver 116 through the second isolation device 132.

That is, in the present implementation, the number of the isolation devices 130 is two, and the signal isolation channels also include two, where one signal isolation channel is only responsible for transmitting signals from the first voltage domain 110 to the second voltage domain 120, and the other channel is only responsible for transmitting signals from the second voltage domain 120 to the first voltage domain 110. At this time, the first voltage domain 110 and the second voltage domain 120 have two clocks, and the clocks corresponding to the first transmitter 115 and the second transmitter 136 are not reset, but the opposite clocks can be reset; and the clocks corresponding to the first receiver 116 and the second receiver 135 may be reset by the opposite trigger signal.

On the basis of the foregoing implementation manner, the embodiment of the present application further provides a signal transmission system, where the signal transmission system includes a first power supply, a second power supply, and the coupler 100, the first power supply is connected to the first voltage domain 110 and is configured to supply power to the first voltage domain 110, and the second power supply is connected to the second voltage domain 120 and is configured to supply power to the second voltage domain 120.

In summary, the embodiment of the present application provides a coupler and a signal transmission system, where the coupler includes a first voltage domain, a second voltage domain, and an isolation device, the first voltage domain is connected to the second voltage domain through the isolation device, the first voltage domain includes a plurality of first signal ports, the second voltage domain includes a plurality of second signal ports, and the number of the isolation devices is less than the number of the first signal ports or the number of the second signal ports; the first voltage domain is used for generating an encoding signal according to data of part or all of the first signal ports and transmitting the encoding signal to the second voltage domain; the second voltage domain is used for receiving the coded signal and decoding the coded signal so as to output the decoded signal through the second signal port. In the coupler provided by the application, the number of the isolation devices is smaller than that of the first signal ports or that of the second signal ports, so that the isolation devices can be shared by a plurality of signal ports, the occupied area and the number of the isolation devices are reduced, and the manufacturing cost of the coupler is reduced.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (10)

1. A coupler, characterized in that the coupler comprises a first voltage domain, a second voltage domain and an isolation device, the first voltage domain and the second voltage domain are connected through the isolation device, the first voltage domain comprises a plurality of first signal ports, the second voltage domain comprises a plurality of second signal ports, the number of isolation devices is smaller than the number of the first signal ports or the second signal ports; wherein,

the first voltage domain is used for generating an encoding signal according to data of part or all of the plurality of first signal ports and transmitting the encoding signal to the second voltage domain;

and the second voltage domain is used for receiving the coded signal and decoding the coded signal so as to output the decoded signal through part or all of the second signal ports.

2. The coupler of claim 1, wherein the first voltage domain is further configured to generate a trigger signal prior to sending the encoded signal and to send the trigger signal to the second voltage domain, the second voltage domain configured to reset a clock of the second voltage domain to align the clock of the second voltage domain with a clock of the first voltage domain upon receiving the trigger signal.

3. The coupler of claim 2, wherein the second voltage domain includes a receiver and a decoding circuit, the receiver being coupled to the isolation device and the decoding circuit, respectively, the receiver further including a first threshold comparator and a second threshold comparator, the first threshold comparator and the second threshold comparator each being coupled to the isolation device and the decoding circuit, respectively, wherein a threshold of the first threshold comparator is greater than a threshold of the second threshold comparator;

the first threshold comparator and the second threshold comparator are both used for receiving a differential signal transmitted by the isolation device, and the decoding circuit is used for determining that the differential signal is the trigger signal when the differential signal is greater than the second threshold and smaller than the first threshold.

4. The coupler of claim 2, wherein the second voltage domain includes a decoding circuit, the decoding circuit includes a nand gate, a first not gate and a second not gate, a first input of the nand gate is configured to receive a trigger signal, a second input of the nand gate is connected to an output of the second not gate, an output of the nand gate is connected to an input of the first not gate, and an output of the first not gate is connected to an input of the second not gate, so that a ring oscillator is formed by the nand gate, the first not gate and the second not gate, and the ring oscillator is utilized for clock resetting.

5. The coupler of claim 1, wherein the first voltage domain includes an encoding circuit and a transmitter, the second voltage domain includes a decoding circuit and a receiver, an input of the encoding circuit is connected to some or all of the plurality of first signal ports, and an output of the encoding circuit is connected to the isolation device;

the input end of the receiver is connected with the isolation device, the output end of the receiver is connected with the input end of the decoding circuit, and the output end of the decoding circuit is connected with part or all of the second signal ports.

6. The coupler of claim 5, wherein the encoding circuit is integrated with the transmitter on a same chip, and the decoding circuit is integrated with the receiver on another chip.

7. The coupler of claim 1, wherein the second voltage domain is further configured to generate an encoded signal from data of some or all of the plurality of second signal ports and to transmit the encoded signal to the first voltage domain;

the first voltage domain is used for receiving the coded signal and decoding the coded signal so as to output the decoded signal through part or all of the first signal ports.

8. The coupler of claim 7, wherein the first voltage domain includes a first codec circuit and a first transceiver, wherein the second voltage domain includes a second codec circuit and a second transceiver, wherein the first codec circuit is connected to the first transceiver and some or all of the first signal ports, wherein the second codec circuit is connected to the second transceiver and some or all of the second signal ports, and wherein the first transceiver and the second transceiver are connected via the isolation device.

9. The coupler of claim 7, wherein the first voltage domain includes a first codec circuit, a first receiver, and a first transmitter, the second voltage domain includes a second codec circuit, a second receiver, and a second transmitter, the isolation devices include a first isolation device and a second isolation device;

the first codec circuit is connected to some or all of the plurality of first signal ports, the first receiver, and the first transmitter, the second codec circuit is connected to some or all of the plurality of second signal ports, the second receiver, and the second transmitter, the first transmitter is connected to the second receiver through the first isolation device, and the second transmitter is connected to the first receiver through the second isolation device.

10. A signal transmission system, characterized in that the signal transmission system comprises a first power supply, a second power supply and a coupler according to any of claims 1 to 9, the first power supply being connected to the first voltage domain and being adapted to supply power to the first voltage domain, the second power supply being connected to the second voltage domain and being adapted to supply power to the second voltage domain.

Images