CN213303613U - Display screen compatible with flash storage circuit and intelligent module design - Google Patents
Display screen compatible with flash storage circuit and intelligent module design Download PDFInfo
- Publication number
- CN213303613U CN213303613U CN202022487565.0U CN202022487565U CN213303613U CN 213303613 U CN213303613 U CN 213303613U CN 202022487565 U CN202022487565 U CN 202022487565U CN 213303613 U CN213303613 U CN 213303613U
- Authority
- CN
- China
- Prior art keywords
- reserved
- hole
- resistor
- sticking
- patch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000013461 design Methods 0.000 title claims abstract description 36
- 238000009434 installation Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 17
- 235000015429 Mirabilis expansa Nutrition 0.000 description 11
- 244000294411 Mirabilis expansa Species 0.000 description 11
- 235000013536 miso Nutrition 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 101710118890 Photosystem II reaction center protein Ycf12 Proteins 0.000 description 7
- 238000012356 Product development Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000006386 memory function Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The utility model discloses a display screen of compatible flash memory circuit and intelligent module design, include: the system comprises a receiving card, a HUB card, an intelligent module and a flash memory chip; wherein: the HUB card comprises a first selection module, the input end of the first selection module is connected with the output end of the receiving card, and the output end of the first selection module is connected with the intelligent module; the first selection module receives one path of output signals of the receiving card and selectively outputs the first selection signals to the intelligent module by adopting a preset selection strategy for the output signals. The intelligent module comprises an MCU and a second selection module, wherein the output end of the second selection module is respectively connected with the MCU and the flash memory chip, and the MCU is connected with the flash memory chip; the input end of the second selection module receives the first selection signal output by the first selection module, and the second selection signal is selected and output by adopting a preset selection strategy for the first selection signal. Through the embodiment of the utility model provides a, can realize the compatible design of pure flash memory circuit and intelligent module circuit, avoid appearing the pin conflict, and can reduce product cost.
Description
Technical Field
The utility model relates to a LED shows the field, in particular to display screen of compatible flash memory circuit and intelligent module design.
Background
In the LED (Light Emitting Diode) industry, end customers have intelligent module requirements. The intelligent module mainly detects the module state, such as voltage, temperature, point inspection, winding displacement detection and information such as storage module correction data, lamp plate date of production.
The flash chip circuit can be used as a peripheral extension circuit of the intelligent module or only the flash circuit is used. The Flash chip is mainly used for storing information such as correction data, lamp panel ID, production date and the like.
Due to cost considerations, some customers only need the lamp panel flash function and do not need the smart module function, while some high-end customers need the smart module function.
Because the control system terminal pin definition conflicts, only one of the two circuits of the intelligent module and the pure flash circuit can be selected, so that two modules of PCB boards and HUB card PCB boards are needed.
In the design of the existing intelligent module and the pure flash circuit, pin conflict can occur, and compatibility cannot be achieved.
SUMMERY OF THE UTILITY MODEL
In view of this, the embodiment of the utility model provides a display screen of compatible flash memory circuit and intelligent module design can realize the compatible design of pure flash memory circuit and intelligent module circuit, avoids appearing the pin conflict, and can reduce product cost.
The utility model provides an above-mentioned technical problem adopted technical scheme as follows:
according to the utility model discloses an aspect provides a compatible flash memory circuit and intelligent module design's display screen, the display screen includes: the system comprises a receiving card, a HUB card, an intelligent module and a flash memory chip; wherein:
the HUB card comprises a first selection module, the input end of the first selection module is connected with the output end of the receiving card, and the output end of the first selection module is connected with the intelligent module; the first selection module receives one path of output signals of the receiving card, and selectively outputs first selection signals to the intelligent module by adopting a preset selection strategy for the output signals.
The intelligent module comprises an MCU and a second selection module, wherein the output end of the second selection module is respectively connected with the MCU and the flash memory chip, and the MCU is connected with the flash memory chip; the input end of the second selection module receives the first selection signal output by the first selection module, and the first selection signal is selected by adopting a preset selection strategy which is the same as that of the first selection module to output a second selection signal.
In one possible design, the one output signal of the receiving card includes two output signals; the first selection module comprises a first resistor reserved sticking hole, a second resistor reserved sticking hole, a third resistor reserved sticking hole, a fourth resistor reserved sticking hole, a first chip set reserved sticking hole, a second chip set reserved sticking hole, a third chip set reserved sticking hole and a fourth chip set reserved sticking hole; wherein:
one end of the first resistor reserved sticking hole and one end of the third resistor reserved sticking hole are connected to form a first input end of the first selection module and electrically connected with a first output end of the receiving card, and one end of the second resistor reserved sticking hole and one end of the fourth resistor reserved sticking hole are connected to form a second input end of the first selection module and electrically connected with a second output end of the receiving card;
the other end of the first resistor reserved sticking hole is electrically connected with the first chip set reserved sticking hole to form a first output end of the first selection module;
the other end of the third resistor reserved sticking hole is electrically connected with a third chip set reserved sticking hole to form a first output end of the first selection module;
the other end of the first resistor reserved sticking hole is electrically connected with the first chip set reserved sticking hole to form a second output end of the first selection module;
the other end of the fourth resistor reserved sticking hole is electrically connected with a fourth chip set reserved sticking hole to form a second output end of the first selection module.
In one possible design, the preset selection strategy includes: simultaneously selecting a first resistor reserved sticking hole, a second resistor reserved sticking hole, a first chip set reserved sticking hole and a second chip set reserved sticking hole; or simultaneously selecting a third resistor reserved sticking hole, a fourth resistor reserved sticking hole, a third chip set reserved sticking hole and a fourth chip set reserved sticking hole.
In one possible design, the second selection module includes a fifth resistor reserved patch hole, a sixth resistor reserved patch hole, a seventh resistor reserved patch hole, an eighth resistor reserved patch hole, a fifth chip reserved patch hole, a sixth chip reserved patch hole, a seventh chip reserved patch hole, and an eighth chip reserved patch hole; wherein:
one end of the fifth resistor reserved sticking hole and one end of the sixth resistor reserved sticking hole are connected to form a first input end of the second selection module and electrically connected with a first output end of the first selection module, and one end of the seventh resistor reserved sticking hole and one end of the eighth resistor reserved sticking hole are connected to form a second input end of the first selection module and electrically connected with a second output end of the first selection module;
the other end of the fifth resistor reserved sticking hole is electrically connected with the fifth chip reserved sticking hole to form a first output end of the second selection module;
the other end of the seventh resistor reserved sticking hole is electrically connected with the seventh chip reserved sticking hole to form a first output end of the second selection module;
the other end of the sixth resistor reserved sticking hole is electrically connected with a sixth chip reserved sticking hole to form a second output end of the second selection module;
and the other end of the eighth resistor reserved sticking hole is electrically connected with the eighth chip reserved sticking hole to form a second output end of the second selection module.
In one possible design, the preset selection strategy includes: meanwhile, a fifth resistor reserved sticking hole, a sixth resistor reserved sticking hole, a fifth chip reserved sticking hole and a sixth chip reserved sticking hole are selected; or simultaneously selecting a seventh resistor reserved sticking hole, an eighth resistor reserved sticking hole, a seventh chip reserved sticking hole and an eighth chip reserved sticking hole.
In one possible design, one output signal of the receiving card includes one output signal; the first selection module comprises a ninth resistor reserved patch hole, a tenth resistor reserved patch hole, a ninth chipset reserved patch hole and a tenth chipset reserved patch hole; wherein:
one end of the ninth resistor reserved patch hole and one end of the tenth resistor reserved patch hole are connected to form an input end of the first selection module and electrically connected with an output end of the receiving card, and the other end of the ninth resistor reserved patch hole and the ninth chipset reserved patch hole are electrically connected to form an output end of the first selection module; the other end of the tenth resistor reserved pasting hole is electrically connected with the tenth chipset reserved pasting hole to form an output end of the first selection module.
In one possible design, the preset selection strategy includes: and simultaneously selecting a ninth resistor reserved patch hole and a ninth chipset reserved patch hole, or simultaneously selecting a tenth resistor reserved patch hole and a tenth chipset reserved patch hole.
In one possible design, the second selection module includes an eleventh resistor reserved patch hole, a twelfth resistor reserved patch hole, an eleventh chipset reserved patch hole, and a twelfth chipset reserved patch hole; wherein:
one end of the eleventh resistor reserved sticking hole and one end of the twelfth resistor reserved sticking hole are connected to form an input end of the second selection module and electrically connected with an output end of the first selection module, and the other end of the eleventh resistor reserved sticking hole is electrically connected with the eleventh chipset reserved sticking hole to form an output end of the second selection module; the other end of the twelfth reserved sticking hole of the resistor is electrically connected with the reserved sticking hole of the twelfth chip set to form an output end of the second selection module.
In one possible design, the preset selection strategy includes: and simultaneously selecting an eleventh reserved sticking hole of the resistor and a reserved sticking hole of the eleventh chip set, or simultaneously selecting a twelfth reserved sticking hole of the resistor and a reserved sticking hole of the twelfth chip set.
In one possible design, the resistance values of the first resistor reserved sticking hole, the second resistor reserved sticking hole, the third resistor reserved sticking hole, the fourth resistor reserved sticking hole, the fifth resistor reserved sticking hole, the sixth resistor reserved sticking hole, the seventh resistor reserved sticking hole, the eighth resistor reserved sticking hole, the ninth resistor reserved sticking hole, the tenth resistor reserved sticking hole, the eleventh resistor reserved sticking hole and the twelfth resistor reserved sticking hole corresponding to the installation resistors are 0 ohm.
Compared with the prior art, the embodiment of the utility model provides a pair of compatible flash memory circuit and intelligent module design's display screen, the display screen includes: the system comprises a receiving card, a HUB card, an intelligent module and a flash memory chip; wherein: the HUB card comprises a first selection module, the input end of the first selection module is connected with the output end of the receiving card, and the output end of the first selection module is connected with the intelligent module; the first selection module receives one path of output signals of the receiving card, and selectively outputs first selection signals to the intelligent module by adopting a preset selection strategy for the output signals. The intelligent module comprises an MCU and a second selection module, wherein the output end of the second selection module is respectively connected with the MCU and the flash memory chip, and the MCU is connected with the flash memory chip; the input end of the second selection module receives the first selection signal output by the first selection module, and the first selection signal is selected by adopting a preset selection strategy which is the same as that of the first selection module to output a second selection signal. Through the embodiment of the utility model, the compatible design of the pure flash memory circuit and the intelligent module circuit can be realized by arranging the first selection module in the HUB card and the second selection module in the intelligent module, and the pin conflict is avoided; the pure flash and intelligent module functions are realized by matching different BOMs (product bill of materials) so as to meet different customer groups; display screen lamp plate PCB and HUB card PCB can become one set by original two sets, and greatly reduced product development test cycle reduces manpower, product cost.
Drawings
Fig. 1 is the embodiment of the utility model provides a compatible flash memory circuit and intelligent module design's display screen's that provides structural schematic diagram.
Fig. 2 is the embodiment of the utility model provides a structural schematic diagram of HUB card in compatible flash memory circuit and intelligent module design's the display screen.
Fig. 3 is a schematic circuit diagram of a HUB card in a display screen compatible with a flash memory circuit and an intelligent module design according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of an intelligent module in a display screen compatible with a flash memory circuit and an intelligent module design according to an embodiment of the present invention.
Fig. 5 is a schematic circuit diagram of a compatible design of an intelligent module and a flash memory chip in a display screen compatible with a flash memory circuit and an intelligent module design according to an embodiment of the present invention.
Fig. 6 is a schematic structural diagram of a HUB card in a display screen compatible with a flash memory circuit and an intelligent module design according to an embodiment of the present invention.
Fig. 7 is a schematic structural diagram of an intelligent module in a display screen compatible with a flash memory circuit and an intelligent module design according to an embodiment of the present invention.
Fig. 8 is a schematic diagram of HUB card compatible 16pin HUB75 interface definition in a display screen compatible with a flash memory circuit and an intelligent module design according to an embodiment of the present invention.
The objects, features and advantages of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
In order to make the technical problem, technical solution and advantageous effects to be solved by the present invention clearer and more obvious, the following description of the present invention with reference to the accompanying drawings and embodiments is provided for further details. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the following description, suffixes such as "module", "part", or "unit" used to denote elements are used only for the convenience of description of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
In an embodiment, as shown in fig. 1, the utility model provides a compatible flash memory circuit and intelligent module design's display screen, the display screen includes: the system comprises a receiving card, a HUB card, an intelligent module and a flash memory chip; wherein:
the HUB card comprises a first selection module, the input end of the first selection module is connected with the output end of the receiving card, and the output end of the first selection module is connected with the intelligent module; the first selection module receives one path of output signals of the receiving card, and selectively outputs first selection signals to the intelligent module by adopting a preset selection strategy for the output signals.
The intelligent module comprises an MCU and a second selection module, wherein the output end of the second selection module is respectively connected with the MCU and the flash memory chip, and the MCU is connected with the flash memory chip; the input end of the second selection module receives the first selection signal output by the first selection module, and the first selection signal adopts a preset selection strategy which is the same as that of the first selection module to selectively output a second selection signal to the MCU or the flash memory chip.
In the embodiment, the first selection module is arranged in the HUB card and the second selection module is arranged in the intelligent module, so that the compatible design of the pure flash memory circuit and the intelligent module circuit can be realized, and the pin conflict is avoided; the pure flash and intelligent module functions are realized by matching different BOMs (product bill of materials) so as to meet different customer groups; display screen lamp plate PCB and HUB card PCB can become one set by original two sets, and greatly reduced product development test cycle reduces manpower, product cost.
Preferably, the HUB card includes a 20pin in-line fence JN1 for connecting the output of the HUB card.
Preferably, the preset selection policy includes that, according to the function and the product BOM (product bill of materials) corresponding to the function, for the same function, only the product BOM corresponding to the same function is selected, and at the same time, the product BOM corresponding to another function is not selected.
In one embodiment, as shown in fig. 2, the one output signal of the receiving card includes two output signals. The first selection module comprises a first resistor reserved sticking hole RZ1, a second resistor reserved sticking hole RZ2, a third resistor reserved sticking hole RF3, a fourth resistor reserved sticking hole RF4, a first chip group reserved sticking hole UZ1, a second chip group reserved sticking hole UZ2, a third chip group reserved sticking hole UF3 and a fourth chip group reserved sticking hole UF 4; wherein:
one end of the first resistor reserved patch RZ1 and one end of the third resistor reserved patch RF3 are connected to form a first input end of the first selection module and a first output end of the receiving card, one end of the second resistor reserved patch RZ2 and one end of the fourth resistor reserved patch RF4 are connected to form a second input end of the first selection module and a second output end of the receiving card are electrically connected.
The other end of the first resistor reserved sticking hole RZ1 is electrically connected with a first chip set reserved sticking hole UZ1 to form a first output end of the first selection module.
The other end of the third resistor reserved sticking hole RF3 is electrically connected with a third chip set reserved sticking hole UF3 to form a first output end of the first selection module.
The other end of the first resistor reserved sticking hole RZ2 is electrically connected with the first chip set reserved sticking hole UZ2 to form a second output end of the first selection module.
The other end of the fourth resistor reserved sticking hole RF4 is electrically connected with the fourth chip set reserved sticking hole UF4 to form a second output end of the first selection module.
The first chip set reserved sticking hole UZ1, the second chip set reserved sticking hole UZ2, the third chip set reserved sticking hole UF3 and the fourth chip set reserved sticking hole UF4 respectively at least comprise one chip reserved sticking hole.
At this time, the preset selection policy specifically includes: simultaneously selecting a first resistor reserved sticking hole RZ1, a second resistor reserved sticking hole RZ2, a first chip set reserved sticking hole UZ1 and a second chip set reserved sticking hole UZ 2; or simultaneously selecting a third reserved resistor sticking hole RF3, a fourth reserved resistor sticking hole RF4, a third chip group reserved sticking hole UF3 and a fourth chip group reserved sticking hole UF 4. Thus, the first resistor reserved patch hole RZ1 and the first chip set reserved patch hole UZ1 are connected to serve as one output signal of one path, and the second resistor reserved patch hole RZ2 and the second chip set reserved patch hole UZ2 are connected to serve as the other output signal of one path; or the third reserved resistor patch RF3 and the third reserved chip patch UF3 are connected as one output signal of the other path, and the fourth reserved resistor patch RF4 and the fourth reserved chip patch UF4 are connected as the other output signal of the other path. Therefore, one of the signals is selected from the signals and is output as the first selection signal.
For example, as shown in FIG. 3, a schematic diagram of a HUB card circuit design is shown.
One output signal of the receiving card comprises two output signals HUB _ SPI _ MISO _ RX and HUB _ SPI _ MISO _ TX.
The first selection module of the HUB card comprises a first resistor reserved sticking hole RZ1, a second resistor reserved sticking hole RZ2, a third resistor reserved sticking hole RF3, a fourth resistor reserved sticking hole RF4, a first chip group reserved sticking hole UZ1, a second chip group reserved sticking hole UZ2, a third chip group reserved sticking hole UF3 and a fourth chip group reserved sticking hole UF 4. Wherein: the first chip set reserved pasting hole UZ1 comprises a chip UZ1A and a chip UZ 1B; the second chip set reserved paste hole UZ2 comprises a chip UZ2A and a chip UZ 2B; the third chip group reserved sticking hole UF3 comprises a chip UF3A and a chip UF 3B; the fourth chip set reserved patch holes UF4 includes UF 4A.
When the display screen lamp plate selects the MCU intelligent function, a first resistor reserved sticking hole RZ1, a second resistor reserved sticking hole RZ2, a chip reserved sticking hole UZ1A, a chip reserved sticking hole UZ1B, a chip reserved sticking hole UZ2A and a chip reserved sticking hole UZ2B are simultaneously selected. IN this way, the output signal from HUB _ SPI _ MISO _ RX of the receiving card is connected to one of the output signals SPIMO _ RX _ IN1 as a single path through the first resistor reserved patch RZ1, the chip reserved patch UZ1A, and the chip reserved patch UZ1B, and is connected to pin 20 of the 2X10pin cut-through fence JN 1. The output signal from HUB _ SPI _ MISO _ TX of the receiving card, second resistor reserved patch RZ2, chip reserved patch UZ2A, and chip reserved patch UZ2B are connected to another output signal SPIMO _ TX _ IN1 as a single path, and are connected to pin 19 of 2X10pin add-IN fence JN 1. Therefore, one of the signals is selected from the signals and is output as the first selection signal.
When the display screen lamp panel selects a flash memory function without the MCU, the third resistor reserved sticking hole RF3, the fourth resistor reserved sticking hole RF4, the chip reserved sticking hole UF3A, the chip reserved sticking hole UF3B and the chip reserved sticking hole UF4A are simultaneously selected. IN this way, the output signal from HUB _ SPI _ MISO _ RX of the receiving card is connected to one of the output signals SPIMO _ RX _ IN1 as a single path through the third resistor reserved patch RF3, the chip reserved patch UF3A, and the chip reserved patch UF3B, and is connected to pin 20 of the 2X10pin add-IN fence JN 1. The fourth resistor reserved patch RF4 and chip reserved patch UF4A, which are the output signals from HUB _ SPI _ MISO _ TX of the receiver card, are connected to another output signal SPIMO _ TX _ IN1 as a single path, which is connected to pin 19 of 2X10pin add-IN fence JN 1. Therefore, one of the signals is selected from the signals and is output as the first selection signal.
As shown in fig. 4, the second selection module includes a fifth resistor reserved patch RZ5, a sixth resistor reserved patch RZ6, a seventh resistor reserved patch RF7, an eighth resistor reserved patch RF8, a fifth chip reserved patch UZ5, a sixth chip reserved patch UZ6, a seventh chip reserved patch UF7, and an eighth chip reserved patch UF 8; wherein:
one end of the fifth resistor reserved patch RZ5 and one end of the sixth resistor reserved patch RF6 are connected to form a first input end of the second selection module and electrically connected with a first output end of the first selection module, and one end of the seventh resistor reserved patch RZ7 and one end of the eighth resistor reserved patch RF8 are connected to form a second input end of the first selection module and electrically connected with a second output end of the first selection module.
The other end of the fifth resistor reserved patch RZ5 is electrically connected with a fifth chip reserved patch UZ5 to form a first output end of the second selection module.
The other end of the seventh resistor reserved patch RF7 is electrically connected to the seventh chip reserved patch UF6 to form a first output terminal of the second selection module.
The other end of the sixth resistor reserved patch RZ6 is electrically connected with a sixth chip reserved patch UZ6 to form a second output end of the second selection module.
The other end of the eighth resistor reserved patch RF8 is electrically connected to the eighth chip reserved patch UF8 to form a second output terminal of the second selection module.
The fifth chip set reserved pasting hole UZ5, the sixth chip set reserved pasting hole UZ6, the seventh chip set reserved pasting hole UF7 and the eighth chip set reserved pasting hole UF8 respectively comprise at least one chip reserved pasting hole.
At this time, the preset selection policy specifically includes: meanwhile, a fifth resistor reserved patch RZ5, a sixth resistor reserved patch RZ6, a fifth chip reserved patch UZ5 and a sixth chip reserved patch UZ6 are selected; or, the seventh resistor reserved patch RF7, the eighth resistor reserved patch RF8, the seventh chip reserved patch UF7 and the eighth chip reserved patch UF8 are simultaneously selected. Thus, the fifth resistor reserved patch RZ5 and the fifth chip reserved patch UZ5 are connected as one output signal of one path, and the sixth resistor reserved patch RZ6 and the sixth chip reserved patch UZ6 are connected as the other output signal of one path; or, the seventh resistor reserved patch RF7 and the seventh chip reserved patch UF7 are connected as one output signal of the other path, and the eighth resistor reserved patch RF8 and the eighth chip reserved patch UF8 are connected as the other output signal of the other path. Therefore, one of the signals is selected from the signals to be output as a second selection signal.
For example, as shown in fig. 5, a schematic diagram is designed for the smart module and the flash compatible circuit.
The second selection module comprises a fifth resistor reserved patch hole RZ5, a sixth resistor reserved patch hole RZ6, a seventh resistor reserved patch hole RF7, a fifth chip reserved patch hole UZ5, a seventh chip reserved patch hole UF7 and an eighth chip reserved patch hole UF 8.
When the display screen lamp plate selects the MCU intelligent function, a fifth resistor reserved sticking hole RZ5, a sixth resistor reserved sticking hole RZ6 and a fifth chip reserved sticking hole UZ5 are simultaneously selected. Thus, the output signal from SPIMO _ TX _ IN1(SPIMO/TX) of the HUB card is connected to one of the output signals MCU _ TX as a single path through the fifth resistor reserved patch RZ5 and the fifth chip reserved patch UZ5, and is connected to the pin 30 of the MCU. The sixth resistive reservation patch RZ6 and the fifth chip reservation patch UZ5, which are output signals from HUB _ SPI _ MISO _ RX (SPIMO/RX) of the receiving card, are connected to another output signal MCU _ RX as a single path, which is connected to pin 31 of the MCU. Therefore, one of the signals is selected from the signals and is output as the first selection signal.
When the display screen lamp panel selects a flash memory function without the MCU, the seventh resistor reserved patch hole RF7, the seventh chip reserved patch hole UF7 and the eighth chip reserved patch hole UF8 are simultaneously selected.
Thus, the output signal from HUB _ SPI _ MISO _ RX (SPIMO/RX) of the receiving card is connected through the eighth chip reserved via UF8 as one of the output signals SPIMO _ MISO _ IN1, which is connected to pin 2 of flash. The seventh resistive patch reservation RF7 and seventh chip patch reservation UF7, which are output signals from HUB _ SPI _ MISO _ TX (SPIMO/TX) of the receiver card, are connected as one path to another output signal spiosi, which is connected to pin 5 of the flash. Therefore, one of the signals is selected from the signals and is output as the first selection signal.
In this embodiment, when the HUB card is provided with the first resistor reserved patch RZ1, the second resistor reserved patch RZ2, the chip reserved patch UZ1A, the chip reserved patch UZ1B, the chip reserved patch UZ2A and the chip reserved patch UZ 2B; and a fifth resistor reserved sticking hole RZ5, a sixth resistor reserved sticking hole RZ6 and a fifth chip reserved sticking hole UZ5 are simultaneously selected on the intelligent module, and corresponding resistors and chips are installed in the corresponding reserved sticking holes, so that the intelligent function of the MCU on the display screen can be used.
When the HUB card is simultaneously selected, a third resistor reserved sticking hole RF3, a fourth resistor reserved sticking hole RF4, a chip reserved sticking hole UF3A, a chip reserved sticking hole UF3B and a chip reserved sticking hole UF4A are selected; the seventh resistor reserved sticking hole RF7, the seventh chip reserved sticking hole UF7 and the eighth chip reserved sticking hole UF8 are simultaneously selected on the intelligent module, corresponding resistors and chips are installed in the corresponding reserved sticking holes, and the flash storage function without the MCU on the display screen can be used.
Therefore, the paste resistor and the chip are arranged in the HUB card, so that the compatible design of a pure flash memory circuit and an intelligent module circuit can be realized, and pin conflict is avoided; the pure flash and intelligent module functions are realized by matching different BOMs (product bill of materials) so as to meet different customer groups; display screen lamp plate PCB and HUB card PCB can become one set by original two sets, and greatly reduced product development test cycle reduces manpower, product cost.
In one embodiment, as shown in fig. 6, one output signal of the receiving card includes one output signal. At this time, the first selection module includes a ninth resistor reserved patch RZ9, a tenth resistor reserved patch RF10, a ninth chipset reserved patch UZ9, and a tenth chipset reserved patch UF 10; wherein:
one end of the ninth resistor reserved patch RZ9 and one end of the tenth resistor reserved patch RF10 are connected to form an input end of the first selection module and electrically connected with an output end of the receiving card, and the other end of the ninth resistor reserved patch RZ9 and the ninth chipset reserved patch UZ9 are electrically connected to form an output end of the first selection module; the other end of the tenth resistor reserved patch RF10 is electrically connected to the tenth chipset reserved patch UF10 to form an output end of the first selection module.
Wherein, the ninth chipset preformed hole UZ9 at least includes one chip preformed hole, and the tenth chipset preformed hole UF10 at least includes one chip preformed hole.
At this time, the preset selection policy specifically includes: and simultaneously selecting a ninth resistor reserved patch RZ9 and a ninth chipset reserved patch UZ9, or simultaneously selecting a tenth resistor reserved patch RF10 and a tenth chipset reserved patch UF 10. Thus, the ninth resistor reserved patch RZ9 and the ninth chipset reserved patch UZ9 are connected as one signal, and the tenth resistor reserved patch RF10 and the tenth chipset reserved patch UF10 are connected as the other signal. Therefore, one of the signals is selected from the signals and is output as the first selection signal.
As shown in fig. 7, the second selection module includes an eleventh resistor reservation patch RZ11, a twelfth resistor reservation patch RF12, an eleventh chipset reservation patch UZ11, and a twelfth chipset reservation patch UF 12; wherein:
one end of the eleventh reserved resistor patch RZ11 and one end of the twelfth reserved resistor patch RF12 are connected to form an input end of the second selection module and electrically connected with an output end of the first selection module, and the other end of the eleventh reserved resistor patch RZ11 is electrically connected with the eleventh reserved chip set patch UZ11 to form an output end of the second selection module; the other end of the twelfth reserved resistor patch RF12 is electrically connected to the twelfth reserved chipset patch UF12 to form an output end of the second selection module.
Wherein, the eleventh chipset preformed hole UZ19 includes at least one chip preformed hole, and the twelfth chipset preformed hole UF12 includes at least one chip preformed hole.
At this time, the preset selection policy specifically includes: and simultaneously selecting an eleventh resistor reserved patch hole RZ11 and an eleventh chip set reserved patch hole UZ11, or simultaneously selecting a twelfth resistor reserved patch hole RF12 and a twelfth chip set reserved patch hole UF 12. Thus, the eleventh reserved resistor patch RZ11 and the eleventh reserved chipset patch UZ11 are connected as one signal, and the twelfth reserved resistor patch RF12 and the twelfth reserved chipset patch UF12 are connected as the other signal. Therefore, one of the signals is selected from the signals to be output as a second selection signal.
In this embodiment, when the HUB card simultaneously selects the ninth resistor reserved patch RZ9 and the ninth chipset reserved patch UZ 9; the intelligent module is simultaneously provided with an eleventh resistor reserved sticking hole RZ11 and an eleventh chipset reserved sticking hole UZ11, and corresponding resistors and chips are installed in the corresponding reserved sticking holes, so that the MCU intelligent function on the display screen can be used.
When the HUB card simultaneously selects a tenth resistor reserved patch RF10 and a tenth chipset reserved patch UF 10; the twelfth resistor reserved sticking hole RF12 and the twelfth chipset reserved sticking hole UF12 are simultaneously selected on the intelligent module, corresponding resistors and chips are installed in the corresponding reserved sticking holes, and the flash storage function without the MCU on the display screen can be used.
Preferably, the resistance values of the corresponding mounting resistors of the first resistor reserved patch hole RZ1, the second resistor reserved patch hole RZ2, the third resistor reserved patch hole RF3, the fourth resistor reserved patch hole RF4, the fifth resistor reserved patch hole RZ5, the sixth resistor reserved patch hole RZ6, the seventh resistor reserved patch hole RF7, the eighth resistor reserved patch hole RF8, the ninth resistor reserved patch hole RZ9, the tenth resistor reserved patch hole RF10, the eleventh resistor reserved patch hole RZ11 and the twelfth resistor reserved patch hole RF12 are 0 ohm.
In one embodiment, as shown in FIG. 8, the HUB card is compliant with the 16pin HUB75 interface definition. When using intelligent module, use 20pin wall seat, the TX of intelligent module and RX signal and flash MOSI and MISO signal realize the pin bit sharing, reduce the total pin number of wall seat.
For example, as shown in fig. 8, JP1 is a 20pin fence, J1 is a fence defined by a standard 16pin HUB75 interface, and JP1 can be compatible with the HUB75 interface definition when pasting a 16pin fence, and pin 1 of the 16pin fence is placed corresponding to pin 3 of a 20pin package.
In this embodiment, the module design can compatible HUB75 interface definition to can match the HUB card that has the two unification designs of receiving card and HUB card of price advantage, reduce product cost.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above embodiment numbers of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention essentially or the portions contributing to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk), and includes a plurality of instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many modifications may be made by one skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (11)
1. The utility model provides a compatible flash memory circuit and intelligent module design's display screen which characterized in that, the display screen includes: the system comprises a receiving card, a HUB card, an intelligent module and a flash memory chip; wherein:
the HUB card comprises a first selection module, the input end of the first selection module is connected with the output end of the receiving card, and the output end of the first selection module is connected with the intelligent module; the first selection module receives an output signal of the receiving card, and selectively outputs a first selection signal to the intelligent module by adopting a preset selection strategy on the output signal;
the intelligent module comprises an MCU and a second selection module, wherein the output end of the second selection module is respectively connected with the MCU and the flash memory chip, and the MCU is connected with the flash memory chip; the input end of the second selection module receives the first selection signal output by the first selection module, and the first selection signal is selected by adopting a preset selection strategy which is the same as that of the first selection module to output a second selection signal.
2. The display screen of claim 1, wherein the one output signal of the receiving card comprises two output signals; the first selection module comprises a first resistor reserved sticking hole, a second resistor reserved sticking hole, a third resistor reserved sticking hole, a fourth resistor reserved sticking hole, a first chip set reserved sticking hole, a second chip set reserved sticking hole, a third chip set reserved sticking hole and a fourth chip set reserved sticking hole; wherein:
one end of the first resistor reserved sticking hole and one end of the third resistor reserved sticking hole are connected to form a first input end of the first selection module and electrically connected with a first output end of the receiving card, and one end of the second resistor reserved sticking hole and one end of the fourth resistor reserved sticking hole are connected to form a second input end of the first selection module and electrically connected with a second output end of the receiving card;
the other end of the first resistor reserved sticking hole is electrically connected with the first chip set reserved sticking hole to form a first output end of the first selection module;
the other end of the third resistor reserved sticking hole is electrically connected with a third chip set reserved sticking hole to form a first output end of the first selection module;
the other end of the first resistor reserved sticking hole is electrically connected with the first chip set reserved sticking hole to form a second output end of the first selection module;
the other end of the fourth resistor reserved sticking hole is electrically connected with a fourth chip set reserved sticking hole to form a second output end of the first selection module.
3. The display screen of claim 2, wherein the preset selection policy comprises: simultaneously selecting a first resistor reserved sticking hole, a second resistor reserved sticking hole, a first chip set reserved sticking hole and a second chip set reserved sticking hole; or simultaneously selecting a third resistor reserved sticking hole, a fourth resistor reserved sticking hole, a third chip set reserved sticking hole and a fourth chip set reserved sticking hole.
4. The display screen of claim 2, wherein the second selection module comprises a fifth resistor reserved patch hole, a sixth resistor reserved patch hole, a seventh resistor reserved patch hole, an eighth resistor reserved patch hole, a fifth chip reserved patch hole, a sixth chip reserved patch hole, a seventh chip reserved patch hole, and an eighth chip reserved patch hole; wherein:
one end of the fifth resistor reserved sticking hole and one end of the sixth resistor reserved sticking hole are connected to form a first input end of the second selection module and electrically connected with a first output end of the first selection module, and one end of the seventh resistor reserved sticking hole and one end of the eighth resistor reserved sticking hole are connected to form a second input end of the first selection module and electrically connected with a second output end of the first selection module;
the other end of the fifth resistor reserved sticking hole is electrically connected with the fifth chip reserved sticking hole to form a first output end of the second selection module;
the other end of the seventh resistor reserved sticking hole is electrically connected with the seventh chip reserved sticking hole to form a first output end of the second selection module;
the other end of the sixth resistor reserved sticking hole is electrically connected with a sixth chip reserved sticking hole to form a second output end of the second selection module;
and the other end of the eighth resistor reserved sticking hole is electrically connected with the eighth chip reserved sticking hole to form a second output end of the second selection module.
5. The display screen of claim 4, wherein the preset selection policy comprises: meanwhile, a fifth resistor reserved sticking hole, a sixth resistor reserved sticking hole, a fifth chip reserved sticking hole and a sixth chip reserved sticking hole are selected; or simultaneously selecting a seventh resistor reserved sticking hole, an eighth resistor reserved sticking hole, a seventh chip reserved sticking hole and an eighth chip reserved sticking hole.
6. The display screen of claim 1, wherein one output signal of the receiving card comprises one output signal; the first selection module comprises a ninth resistor reserved patch hole, a tenth resistor reserved patch hole, a ninth chipset reserved patch hole and a tenth chipset reserved patch hole; wherein:
one end of the ninth resistor reserved patch hole and one end of the tenth resistor reserved patch hole are connected to form an input end of the first selection module and electrically connected with an output end of the receiving card, and the other end of the ninth resistor reserved patch hole and the ninth chipset reserved patch hole are electrically connected to form an output end of the first selection module; the other end of the tenth resistor reserved pasting hole is electrically connected with the tenth chipset reserved pasting hole to form an output end of the first selection module.
7. The display screen of claim 6, wherein the preset selection policy comprises: and simultaneously selecting a ninth resistor reserved patch hole and a ninth chipset reserved patch hole, or simultaneously selecting a tenth resistor reserved patch hole and a tenth chipset reserved patch hole.
8. The display screen of claim 6, wherein the second selection module comprises an eleventh resistive reserve patch hole, a twelfth resistive reserve patch hole, an eleventh chipset reserve patch hole, a twelfth chipset reserve patch hole; wherein:
one end of the eleventh resistor reserved sticking hole and one end of the twelfth resistor reserved sticking hole are connected to form an input end of the second selection module and electrically connected with an output end of the first selection module, and the other end of the eleventh resistor reserved sticking hole is electrically connected with the eleventh chipset reserved sticking hole to form an output end of the second selection module; the other end of the twelfth reserved sticking hole of the resistor is electrically connected with the reserved sticking hole of the twelfth chip set to form an output end of the second selection module.
9. The display screen of claim 8, wherein the preset selection policy comprises: and simultaneously selecting an eleventh reserved sticking hole of the resistor and a reserved sticking hole of the eleventh chip set, or simultaneously selecting a twelfth reserved sticking hole of the resistor and a reserved sticking hole of the twelfth chip set.
10. The display screen of any one of claims 2 to 5, wherein the first resistor reserved patch hole, the second resistor reserved patch hole, the third resistor reserved patch hole, the fourth resistor reserved patch hole, the fifth resistor reserved patch hole, the sixth resistor reserved patch hole, the seventh resistor reserved patch hole and the eighth resistor reserved patch hole have a resistance value of 0 ohm corresponding to the installation resistor.
11. The display screen of any one of claims 6 to 9, wherein the ninth resistor preformed hole, the tenth resistor preformed hole, the eleventh resistor preformed hole and the twelfth resistor preformed hole have a resistance value of 0 ohm corresponding to the installation resistor.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022487565.0U CN213303613U (en) | 2020-11-02 | 2020-11-02 | Display screen compatible with flash storage circuit and intelligent module design |
| PCT/CN2021/106284 WO2022088763A1 (en) | 2020-11-02 | 2021-07-14 | Display screen having design compatible with flash memory circuit and smart module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202022487565.0U CN213303613U (en) | 2020-11-02 | 2020-11-02 | Display screen compatible with flash storage circuit and intelligent module design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN213303613U true CN213303613U (en) | 2021-05-28 |
Family
ID=76015758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202022487565.0U Active CN213303613U (en) | 2020-11-02 | 2020-11-02 | Display screen compatible with flash storage circuit and intelligent module design |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN213303613U (en) |
| WO (1) | WO2022088763A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022088763A1 (en) * | 2020-11-02 | 2022-05-05 | 深圳市洲明科技股份有限公司 | Display screen having design compatible with flash memory circuit and smart module |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117174050B (en) * | 2023-09-18 | 2025-10-17 | 湖南旭阳显示科技有限公司 | COB liquid crystal display module with serial-parallel port and Chinese character library |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6820156B1 (en) * | 2001-06-29 | 2004-11-16 | Dell Products L.P. | Computer system with bus socket showing configured mode |
| DE20312372U1 (en) * | 2003-08-11 | 2003-10-02 | Kontron Embedded Modules GmbH, 94469 Deggendorf | display adapter |
| KR100606162B1 (en) * | 2005-01-12 | 2006-08-01 | 삼성전자주식회사 | Device and method for converting Algibi interface to Mddia interface |
| JP2012068996A (en) * | 2010-09-24 | 2012-04-05 | Toshiba Denpa Products Kk | Cpu board |
| CN203573621U (en) * | 2013-11-11 | 2014-04-30 | 西安诺瓦电子科技有限公司 | LED lamp panel and LED display screen |
| CN111063318A (en) * | 2018-10-17 | 2020-04-24 | 西安诺瓦星云科技股份有限公司 | Plug-in component, scanning card, display control card and display control system |
| CN213303613U (en) * | 2020-11-02 | 2021-05-28 | 深圳市洲明科技股份有限公司 | Display screen compatible with flash storage circuit and intelligent module design |
-
2020
- 2020-11-02 CN CN202022487565.0U patent/CN213303613U/en active Active
-
2021
- 2021-07-14 WO PCT/CN2021/106284 patent/WO2022088763A1/en not_active Ceased
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022088763A1 (en) * | 2020-11-02 | 2022-05-05 | 深圳市洲明科技股份有限公司 | Display screen having design compatible with flash memory circuit and smart module |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022088763A1 (en) | 2022-05-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7948120B2 (en) | Modular power distribution backplane, system, and method | |
| CN213303613U (en) | Display screen compatible with flash storage circuit and intelligent module design | |
| US8201135B2 (en) | Printed circuit board layout system and method thereof | |
| CN103996372B (en) | LED display and the control method thereof of storage and read-write data on module can be realized | |
| CN110427775B (en) | Data query authority control method and device | |
| US20130132628A1 (en) | Plug-in module, electronic system, and judging method and querying method thereof | |
| CN104573242A (en) | PCB design layout audit system | |
| CN101533351A (en) | Method and system for identifying information of single plate hardware version | |
| CN109359073A (en) | A kind of communication between devices method and apparatus topological structure based on spi bus | |
| CN103516961A (en) | Image processor, preparing method thereof and mother card | |
| CN106919427A (en) | A kind of method to set up, setting device and electronic equipment | |
| CN104573243A (en) | PCB design layout audit device | |
| CN101499029B (en) | Cabinet recognizing method, computer and main board | |
| CN109726020A (en) | System docking method, system docking equipment, storage medium and device | |
| CN104900187B (en) | LED display boards control method and control device, LED control cards | |
| CN116506378B (en) | Switch equipment, serial communication interface switching method and device thereof | |
| CN109948608A (en) | A kind of license plate number knows method for distinguishing, computer installation and computer readable storage medium | |
| CN110427213A (en) | Method, device, equipment and storage medium for realizing intelligent configuration software | |
| CN113325335A (en) | Circuit failure detection circuit and method and intelligent electronic equipment | |
| CN111583856A (en) | Multi-port repeater and control method | |
| CN109920129B (en) | Driver IC card remote card writing method, monitoring and scheduling host and terminal equipment | |
| CN111361826B (en) | Production line control method and device for name plate of mobile equipment and production line equipment | |
| JP2001195327A (en) | Information processing method and information processing apparatus | |
| CN111611113B (en) | Hardware equipment and hardware version identification device and method thereof | |
| CN106815160A (en) | Notice board implementation method and notice board realize device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |