CN213209277U - Focal plane infrared sensor - Google Patents
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- CN213209277U CN213209277U CN202021698101.8U CN202021698101U CN213209277U CN 213209277 U CN213209277 U CN 213209277U CN 202021698101 U CN202021698101 U CN 202021698101U CN 213209277 U CN213209277 U CN 213209277U
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Abstract
The application provides a focal plane infrared sensor, includes: an operational amplifier; the blind pixel circuit comprises a plurality of blind pixel resistors and is used for generating dark field current according to the bias of the operational amplifier; the sensing element circuit comprises a plurality of sensing element resistors and is used for generating a thermal current according to the bias of the operational amplifier; the blind cell resistor and the sensitive cell resistor have the same circuit structure; a subtraction circuit for subtracting the dark field current and the thermal current to generate a current difference, wherein the subtraction circuit further comprises a selection circuit selectively turned on to enable the blind cell circuit or the sensitive cell circuit to generate the dark field current or the thermal current according to the bias of the operational amplifier; and an integration circuit for integrating the current difference over an integration period.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a focal plane infrared sensor.
Background
The infrared focal plane detector is a core component of a thermal imaging system, is a key for detecting, identifying and analyzing infrared information of an object, and has wide application in various industries such as military, industry, traffic, security monitoring, meteorology, medicine and the like. The infrared focal plane detector can be divided into a refrigeration type infrared focal plane detector and an uncooled infrared focal plane detector. The refrigeration type infrared focal plane detector has the advantages of high sensitivity, capability of distinguishing more subtle temperature difference, longer detection distance and main application to high-end military equipment. The uncooled infrared focal plane array detector can work at normal temperature without refrigeration equipment, has the advantages of light weight, small volume, long service life, low cost, low power consumption, quick start, good stability and the like, and meets the urgent needs of civil infrared systems and partial military infrared systems on long-wave infrared detectors, so that the technology is rapidly developed and widely applied.
The uncooled infrared focal plane detector is mainly based on a thermal sensor prepared by a Micro Electro Mechanical System (MEMS), and can be roughly divided into a thermopile/thermocouple, a pyroelectric, an optical machine, a microbolometer and other types, wherein the microbolometer has the advantages of rapid technical development and the largest market share. The core of the uncooled infrared detector based on the microbolometer is a CMOS (Complementary Metal Oxide Semiconductor) readout circuit and an MEMS (micro electro Mechanical Systems) sensor. The CMOS readout circuit is used for amplifying and reading out signals, and the readout circuit is one of key components of a non-refrigeration infrared focal plane array (IRFPA) so as to perform preprocessing (such as integration, amplification, filtering, sampling/holding and the like) on weak signals sensed by an infrared detector and perform parallel/serial conversion on array signals. The MEMS sensor completes photoelectric conversion operation, the microbolometer Focal Plane Array (FPA) has high sensitivity, and the working principle of the MEMS sensor is that the temperature of a thermosensitive material changes after absorbing incident infrared radiation, so that the resistance value of the thermosensitive material changes, and the size of an infrared radiation signal is detected by measuring the change of the resistance value.
In recent years, the array scale of the uncooled infrared focal plane detector is continuously increased, the size of the sensitive element is continuously reduced, and a plurality of new technical development trends appear in the aspects of the detector unit structure, the optimization design thereof, the reading circuit design, the packaging form and the like.
Disclosure of Invention
The application provides a focal plane infrared sensor, through circuit structure design, makes its output voltage stable, guarantees thermal imaging quality.
The application provides a focal plane infrared sensor, includes:
the operational amplifier comprises a positive input end, a negative input end and an output end, wherein the positive input end of the operational amplifier receives a first reference voltage signal;
the blind pixel circuit comprises a plurality of blind pixel resistors, is connected with the negative input end and the output end of the operational amplifier, and generates dark field current according to the bias of the operational amplifier;
the sensitive element circuit comprises a plurality of sensitive element resistors, is connected with the negative input end and the output end of the operational amplifier, and generates a thermal current according to the bias of the operational amplifier; the blind element resistor and the sensitive element resistor have the same circuit connection structure;
the input end of the subtraction circuit is connected with the output ends of the blind element circuit and the sensitive element circuit and is used for subtracting the dark field current and the thermal current to generate a current difference, and the current difference represents the current change generated on the sensitive element resistor by infrared irradiation; the subtraction circuit further comprises a selection circuit, and the selection circuit is selectively conducted to enable the blind element circuit or the sensitive element circuit to generate the dark field current or the heat current according to the bias of the operational amplifier; and
and the integrating circuit is connected with the output end of the subtracting circuit and is used for integrating the current difference in an integrating period.
According to the focal plane infrared sensor, the blind element circuit is consistent with the sensitive element circuit connecting structure, and voltage feedback is carried out through the operational amplifier, so that the voltage for generating current on the sensitive element resistor can be kept stable, the influence of the temperature change on the bias voltage of the blind element/sensitive element resistor is greatly inhibited by the CMOS process fluctuation, the image signal output consistency is improved, the fixed format noise is reduced, the thermal imaging quality is improved, bias voltage calibration on each sensitive element resistor is avoided in the design principle, and the system application is greatly simplified.
In order to make the aforementioned and other objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a circuit structure of a focal plane infrared sensor according to an embodiment of the prior art;
FIG. 2 is a schematic diagram of a circuit configuration of a focal plane infrared sensor according to an embodiment of the present application;
FIG. 3 is a timing diagram illustrating the operation of signal readout of the focal plane infrared sensor according to an embodiment of the present application; and
fig. 4 is a timing diagram illustrating signal readout of a focal plane infrared sensor according to another embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The term "connected," as used in this application, is defined as follows, and "connected" is used to describe either a direct connection or an indirect connection between two circuit elements. For example, two connection elements may be directly connected by a metal line or indirectly connected by an intermediate circuit element (e.g., a capacitor, a resistor, or a source or a drain of a transistor).
The terms "upper", "lower", "left", "right", "row direction", "column direction", and the like used in the present application indicate orientations or positional relationships based on those shown in the drawings, only for the purpose of clarity and convenience of description of the technical solutions, and thus, should not be construed as limiting the present application.
The embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
Fig. 1 is a schematic circuit diagram of a focal plane infrared sensor according to an embodiment in the prior art. The focal plane infrared sensor comprises a plurality of sensitive element resistors R0-Rn, a blind element resistor Rb, a P-type MOS tube M10, an N-type MOS tube M20, a plurality of row gating switch MOS tubes (N-type MOS tubes) MR0-MRn, an integrating amplifier A0, an integrating capacitor C10 and a reset switch M30. The gate of the P-mos transistor M1 receives a control signal GSK, and the gate of the N-mos transistor M20 receives a control signal GFIDV. The gates of the row gating switch mos tubes MR0-MRn respectively receive row gating control signals rs <0> -rs < n >, wherein n is any integer greater than or equal to 1. The first end of the blind resistor Rb receives a voltage signal VSK, the second end of the blind resistor Rb is connected with the source end of a P-type mos tube, the drain electrode of the P-type mos tube M10 is connected with the drain electrode of an N-type mos tube and the negative input end of an integrating amplifier, and the positive input end of the integrating amplifier A0 receives a reference signal Vref. An integrating capacitor C10 and a reset switch M30 are connected between the negative input and the output of the integrating amplifier a 0. The source electrode of the N-type mos tube M20 is connected with the drain electrodes of a plurality of row gating switch mos tubes MR0-MRn, and the source electrodes of the row gating switch mos tubes MR0-MRn are grounded through the sensitive element resistors R0-Rn respectively. The cell resistors R0-Rn will change with the infrared radiation, so that the current Ia flowing through the cell resistors is changed, Ib is the current flowing through the blind cell resistors Rb, the integrated current Iint-Ib, the integrated voltage Δ Vint-Iint/C10, where Tint is the integration time, and the output voltage Vout-Vref- Δ Vint, so that the output voltage Vout will change with the change of the infrared radiation temperature.
According to the circuit structure of the focal plane infrared sensor, due to the fact that the circuit structures of the blind element resistor Rb and the sensitive element resistors R0-Rn are inconsistent, the voltage on the sensitive element resistors MR0-MRn is unstable, the integrated current Iint is easily interfered, fixed format noise in output signals is obvious, thermal imaging quality is affected, even if point-by-point correction is carried out at the rear end through adjustment of VSK voltage, an ideal state cannot be achieved, and meanwhile the complexity and the cost of the system are greatly increased.
According to the focal plane infrared sensor and the signal reading method thereof, the blind element circuit and the sensitive element circuit are consistent in connection structure, and voltage feedback is carried out through the operational amplifier, so that the voltage for generating current on the sensitive element resistor can be kept stable, the influence of CMOS (complementary metal oxide semiconductor) process fluctuation and temperature change on the bias voltage of the blind element/sensitive element resistor is greatly inhibited, the output consistency of image signals is improved, the fixed format noise is reduced, the thermal imaging quality is improved, bias voltage calibration on each sensitive element resistor is avoided from the design principle, and the system application is greatly simplified.
Fig. 2 is a schematic circuit diagram of a focal plane infrared sensor according to an embodiment of the present application. The focal plane infrared sensor comprises an operational amplifier AMP10, a blind pixel circuit 100, a sensitive pixel circuit 200, a subtraction circuit 300 and an integration circuit 400. The operational amplifier AMP10 includes a positive input terminal, a negative input terminal, and an output terminal, and the positive input terminal of the operational amplifier AMP10 receives a first reference voltage signal Vrep 1.
The blind pixel circuit 100 includes a plurality of blind pixel resistors Rd0-Rdn (n is 1 in this embodiment), the blind pixel circuit 100 is connected to the negative input terminal and the output terminal of the operational amplifier AMP10, and the blind pixel circuit 100 generates a dark field current Id according to the bias of the operational amplifier AMP 10. The dark field current Id comprises currents induced by blind element resistors Rd0-Rdn when no infrared radiation exists, or currents when heat is rapidly dissipated under infrared radiation; the blind element resistors Rd0-Rdn can shield infrared radiation through a light blocking structure, or avoid heat accumulation on the resistors through an accelerated heat dissipation structure.
The sense element circuit 200 comprises a plurality of sense element resistors Ra0-Ran, the sense element circuit 200 is connected with the negative input end and the output end of the operational amplifier AMP10, and the sense element circuit 200 generates a thermal current Ia according to the bias of the operational amplifier AMP 10; the blind cell resistor Rd0-Rdn and the sensitive cell resistor Ra0-Ran have the same circuit connection structure. The subtraction circuit 300 is connected to the output terminals of the blind pixel circuit 100 and the sensor circuit 200, and is configured to subtract the dark field current Id from the thermal current Ia to generate a current difference, where the current difference represents a current change generated by infrared irradiation on the sensor resistor.
The subtraction circuit 300 further includes a selection circuit 310, and the selection circuit 310 is selectively turned on to enable the blind cell circuit 100 or the sense cell circuit 200 to generate the dark field current Id or the thermal current Ia according to the bias of the operational amplifier AMP 10; and an integration circuit 400, connected to the subtraction circuit 300, for integrating the current difference over an integration period.
In one embodiment, the blind pixel circuit 100 further includes a first switch transistor Ms1, a second switch transistor Ms2, and a first transistor M1. The first end of the blind cell resistor Rd0-Rdn is grounded, the second end of the blind cell resistor Rd0-Rdn is connected to the negative input end of the operational amplifier AMP10 through the first switch transistor Ms1 and is connected to the first end of the first transistor M1, the gate of the first transistor M1 is connected to the output end of the operational amplifier AMP10, the second end of the first transistor M1 is connected to the subtraction circuit 300 through the second switch transistor Ms2, and the gates of the first switch transistor Ms1 and the second switch transistor Ms2 are controlled by blind cell row selection signals rsd <0> -rsd < n > to enable or disable the blind cell resistor Rd 0-Rdn. In one embodiment, the first switch transistor Ms1, the second switch transistor Ms2, and the first transistor M1 are NMOS transistors.
In one embodiment, the sense element circuit 200 includes a third switching transistor Ms3, a fourth switching transistor Ms4, and a second transistor M2. The first terminal of the sense element resistor Ra0-Ran is grounded, the second terminal thereof is connected to the negative input terminal of the operational amplifier AMP10 through the third switching transistor Ms3, and is also connected to the first terminal of the second transistor M2, the gate of the second transistor M2 is connected to the output terminal of the operational amplifier AMP10, the second terminal of the second transistor M2 is connected to the subtraction circuit 300 through the fourth switching transistor Ms4, and the gates of the third switching transistor Ms3 and the fourth switching transistor Ms4 are controlled by sense element row selection signals rsa <0> -rsa < n > to make the sense element resistor Ra0-Ran operative or inoperative. In one embodiment, the third switching transistor Ms3, the second switching transistor Ms4, and the second transistor M2 are NMOS transistors.
In one embodiment, the subtraction circuit 300 is a mirror bias circuit, and includes a third transistor M3, a fourth transistor M4, a fifth transistor M5 and a sixth transistor M6, first ends of the third transistor M3 and the fourth transistor M4 are connected to a voltage source VDD, second ends of the third transistor M3 and the fourth transistor M4 are connected to first ends of the fifth transistor M5 and the sixth transistor M6, respectively, gates of the third transistor M3 and the fourth transistor M4 are connected to each other through a first sampling switch S1, a gate of the third transistor M3 is further connected to a second end of the fifth transistor M5, and a gate of the fourth transistor M4 is further connected to ground through a first sampling capacitor C1; the gates of the fifth transistor M5 and the sixth transistor M6 are interconnected through a second sampling switch S2, the second terminal of the fifth transistor M5 and the second terminal of the sixth transistor M6 are connected to the selection circuit 310, and the gate of the sixth transistor M6 is further connected to ground through a second sampling capacitor C2. The first sampling switch S1 and the second sampling switch S2 may be transistor switches, such as NMOS transistor switches, PMOS transistor switches, or CMOS transistor switches.
In one embodiment, the selection circuit 310 includes a fifth switching transistor Ms5 and a sixth switching transistor Ms 6. First terminals of the fifth switch transistor Ms5 and the sixth switch transistor Ms6 are respectively connected to second terminals of the fifth transistor M5 and the sixth transistor M6, second terminals of the fifth switch transistor Ms5 and the sixth switch transistor Ms6 are connected to output terminals of the blind cell circuit 100 and the sensor circuit 200, and gates of the fifth switch transistor Ms5 and the sixth switch transistor Ms6 respectively receive control signals sel _ d and sel _ a to be alternately turned on or off, so that the blind cell circuit 100 generates a dark field current Id according to a bias of the operational amplifier AMP10 or the sensor circuit 200 generates a thermal current Ia according to a bias of the operational amplifier AMP 10.
In one embodiment, the fifth switching transistor Ms5, the sixth switching transistor Ms6, the third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 are PMOS transistors. In one embodiment, the third transistor M3, fourth transistor M4, fifth transistor M5, sixth transistor M6, the fifth switch transistor Ms5 and sixth switch transistor Ms6 respectively comprise a plurality of single transistors connected in parallel, the sizes of the single transistors in the third transistor M3 and the fourth transistor M4 are the same, the sizes of the single transistors in the fifth transistor M5 and the sixth transistor M6 are the same, the individual transistors of the fifth switch transistor Ms5 and the sixth switch transistor Ms6 are of the same size, and the fifth transistor M5 is proportional to the number of individual transistors in the sixth transistor M6, equal in proportional relationship to the number of individual transistors in the third transistor M3 and the fourth transistor M4, and also equal in proportional relationship to the number of individual transistors in the fifth switching transistor Ms5 and the sixth switching transistor Ms 6. This number ratio is equal to the number of blind cell resistors Rd 0-Rdn. In this embodiment, the number of the blind cell resistors Rd0 to Rdn is 2. In other embodiments, the number of the blind cell resistors Rd0-Rdn can be plural.
In one embodiment, the integration circuit 400 is a capacitive feedback transimpedance amplifier (CTIA) structure, and includes a transimpedance amplifier a1, an integration capacitor Cin and an integration reset switch Mr1, a first end of the integration capacitor Cin is connected to the negative input end of the transimpedance amplifier a1, a second end of the integration capacitor Cin is connected to the output end of the transimpedance amplifier a1, a positive input end of the transimpedance amplifier a1 receives a second reference voltage signal Vref2, a first end of the integration reset switch Mr1 is connected to the negative input end of the transimpedance amplifier a1, a second end of the integration reset switch Mr1 is connected to the output end of the transimpedance amplifier a1, and the integration reset switch Mr1 is configured to receive an integration reset signal az during an auto clear period, and the integration reset switch Mr1 is controlled to reset the integration capacitor Cin. In one embodiment, the capacitance of the integrating capacitor Cin is adjustable, and the integration gain can be adjusted by setting different capacitances of the integrating capacitor Cin. In one embodiment, the integration circuit 400 further comprises an integration control switch S3 connected between the subtraction circuit 300 and the negative input of the transimpedance amplifier a1 for controlling the stopping of the integration. The integral control switch S3 may be a transistor switch, such as an NMOS transistor switch, a PMOS transistor switch, or a CMOS transistor switch. In one embodiment, the integration circuit 400 further comprises a third sampling capacitor C3 connected between the negative input of the transimpedance amplifier a1 and ground.
The circuit structure of the focal plane infrared sensor provided in fig. 2 of the present application only illustrates a simplified circuit structure of a column of pixels, in an actual product, the blind pixel circuit 100, the sensitive pixel circuit 200, and the readout circuit formed by the subtraction circuit 300 and the integration circuit 400 all exist in an array form, and each column of sensitive pixel reads out a signal through one readout circuit to obtain a complete thermal imaging image.
Fig. 3 and 4 are timing diagrams of signal readout of the focal plane infrared sensor according to two embodiments provided in the present application. The application provides a signal reading method applied to the focal plane infrared sensor, which comprises the following steps:
the blind pixel row selection signals rsd <0> -rsd < n > of the blind pixel circuit 100 are gated, the integral control switch S3 is turned on, the fifth switch transistor Ms5, the first sampling switch S1 and the second sampling switch S2 in the selection circuit are turned on, the sixth switch transistor Ms6 is turned off, the operational amplifier AMP10 biases the blind pixel circuit 100, the dark field current Id generated by the blind pixel circuit 100 (the current value of the dark field current Id is determined by dividing the first reference voltage signal Vrep1 by the resistances of the blind pixel resistors Rd0-Rdn respectively) flows through the left half side of the subtraction circuit 300, and the bias voltage is generated and mirrored to the right half side of the subtraction circuit 300 through the first sampling switch S1 and the second sampling switch S2;
the fifth switch transistor Ms5, the first sampling switch S1 and the second sampling switch S2 are turned off, the sixth switch transistor Ms6 is turned on, and the bias voltage is sampled into the first sampling capacitor C1 and the second sampling capacitor C2;
the sensing element row selection signals rsa <0> -rsa < n > of the sensing element circuit 200 are sequentially gated, a sixth switching transistor Ms6 in the selection circuit is turned on, the sensing element circuit 200 is biased by the operational amplifier AMP10 to generate a thermal current Ia (the current value of the thermal current Ia is determined by dividing a first reference voltage signal Vrep1 by the resistance values of sensing element resistors Ra0-Ran respectively), the sensing element resistors Ra0-Ran are subjected to heat accumulation under infrared irradiation, the temperature is increased, the resistance is increased, the thermal current Ia is decreased, and the thermal current Ia generated by the sensing element resistors Ra0-Ran flows through the right side of the subtraction circuit 300; and
the dark field current Id and the thermal current Ia are subtracted in the subtraction circuit 300 to generate a current difference, which represents a current change generated by infrared irradiation on the sensitive element resistor, and the current difference is input to the negative input terminal of the transimpedance amplifier a 1.
Specifically, during the auto clear or reset signal quantization period (T1), the integral reset signal az is at a high level, the integral reset switch Mr1 is turned on, the current difference directly flows into the output terminal of the transimpedance amplifier a1, and the voltage signal amp _ out output from the output terminal of the transimpedance amplifier a1 is equal to the second reference voltage signal Vref2 at the positive input terminal, representing the reset signal. In the embodiment provided in fig. 3 of the present application, the reset signal is quantized (referring to the timing of ramp/count _ en) at the first auto-zero period, that is, at the beginning of the auto-zero period, so as to obtain a digitized reset signal. In the embodiment provided in fig. 4 of the present application, the reset signals are quantized (referring to the timing of the ramp/count _ en) at the same time only during the second auto-clear period, so as to obtain the digitized reset signals.
After the quantization period (T1) of the auto clear or reset signal, an integration period (T2) is entered, and during the integration period (T2), the integration reset signal az is at a low level, the integration reset switch Mr1 is turned off, the current difference flowing out from the subtraction circuit 300 is integrated on the integration capacitor Cin, and the voltage signal amp _ out output from the output terminal of the transimpedance amplifier a1 gradually decreases. In the integration process, the relationship between the integration voltage and the integration current, and the relationship between the integration capacitor and the integration time are the same as those of the calculation method in the prior art, that is, the integration voltage is equal to the integration current multiplied by the integration time divided by the integration capacitor, which is not described herein again.
After the integration period (T2), an image signal quantization period (T3) is entered, and during the image signal quantization period (T3), the integration control switch S3 is turned off, the integration circuit 400 stops integrating, the voltage signal amp _ out at the output terminal of the transimpedance amplifier a1 is an image signal, and the image signal is quantized (referring to the timing of the ramp/count _ en) to obtain a digital image signal. And then entering the quantization period of the automatic zero clearing/resetting signal.
In the embodiment provided in fig. 4 of the present application, since there is no integration time with a long interval between the quantization of the image signal and the quantization of the reset signal, the interval between the two sampling times is short, and the low-frequency noise can be better suppressed.
Further, the back-end circuit subtracts the digitized reset signal and the digitized image signal to obtain a final effective output quantized digital signal, where the final effective output quantized digital signal is proportional to the temperature sensed by the sensing element circuit 200.
According to the focal plane infrared sensor and the signal reading method thereof, the blind element circuit and the sensitive element circuit are consistent in connection structure, and voltage feedback is carried out through the operational amplifier, so that the voltage for generating current on the sensitive element resistor can be kept stable, the influence of CMOS (complementary metal oxide semiconductor) process fluctuation and temperature change on the bias voltage of the blind element/sensitive element resistor is greatly inhibited, the output consistency of image signals is improved, the noise of a fixed format is reduced, the thermal imaging quality is improved, bias voltage calibration on each sensitive element resistor is avoided from the design principle, and the system application is greatly simplified. And because the blind element circuit and the sensitive element circuit share one operational amplifier, the occupied area is small, and the chip integration level is higher.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the recitation of an element by the phrase "comprising an … …" does not exclude the presence of additional like elements in the process, method, article, or apparatus that comprises the element, and further, where similarly-named elements, features, or elements in different embodiments of the disclosure may have the same meaning, or may have different meanings, that particular meaning should be determined by their interpretation in the embodiment or further by context with the embodiment.
It should be understood that, although the steps in the flowcharts in the embodiments of the present application are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and may be performed in other orders unless explicitly stated herein. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, in different orders, and may be performed alternately or at least partially with respect to other steps or sub-steps of other steps.
The present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
Claims (10)
1. A focal plane infrared sensor, comprising:
the operational amplifier comprises a positive input end, a negative input end and an output end, wherein the positive input end of the operational amplifier receives a first reference voltage signal;
the blind pixel circuit comprises a plurality of blind pixel resistors, is connected with the negative input end and the output end of the operational amplifier, and generates dark field current according to the bias of the operational amplifier;
the sensitive element circuit comprises a plurality of sensitive element resistors, is connected with the negative input end and the output end of the operational amplifier, and generates a thermal current according to the bias of the operational amplifier; the blind element resistor and the sensitive element resistor have the same circuit connection structure;
the input end of the subtraction circuit is connected with the output ends of the blind element circuit and the sensitive element circuit and is used for subtracting the dark field current and the thermal current to generate a current difference, and the current difference represents the current change generated on the sensitive element resistor by infrared irradiation; the subtraction circuit further comprises a selection circuit, and the selection circuit is selectively conducted to enable the blind element circuit or the sensitive element circuit to generate the dark field current or the heat current according to the bias of the operational amplifier; and
and the integrating circuit is connected with the output end of the subtracting circuit and is used for integrating the current difference in an integrating period.
2. The focal plane infrared sensor according to claim 1, wherein the first terminal of the blind-cell resistor is grounded, the second terminal of the blind-cell resistor is connected to the negative input terminal of the operational amplifier through a first switching transistor and connected to the first terminal of a first transistor, the gate of the first transistor is connected to the output terminal of the operational amplifier, the second terminal of the first transistor is connected to the subtraction circuit through a second switching transistor, and the gates of the first switching transistor and the second switching transistor are controlled by a blind-cell row selection signal to enable or disable the blind-cell resistor.
3. The focal plane infrared sensor of claim 1, wherein the sense element resistor has a first terminal connected to ground and a second terminal connected to the negative input terminal of the operational amplifier through a third switching transistor and further connected to a first terminal of a second transistor having a gate connected to the output terminal of the operational amplifier, the second terminal of the second transistor being connected to the subtraction circuit through a fourth switching transistor, the gates of the third and fourth switching transistors being controlled by a sense element row selection signal to operate or not operate the sense element resistor.
4. The focal plane infrared sensor of claim 1, wherein the subtraction circuit is a mirror bias circuit comprising a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, first ends of the third and fourth transistors are coupled to a voltage source, second ends of the third and fourth transistors are coupled to first ends of the fifth and sixth transistors, respectively, a gate of the third and fourth transistors is interconnected through a first sampling switch, a gate of the third transistor is further coupled to a second end of the fifth transistor, and a gate of the fourth transistor is further coupled to ground through a first sampling capacitor; the grid electrodes of the fifth transistor and the sixth transistor are interconnected through a second sampling switch, the second end of the fifth transistor and the second end of the sixth transistor are connected with the selection circuit, and the grid electrode of the sixth transistor is grounded through a second sampling capacitor.
5. The focal plane infrared sensor of claim 4, wherein the selection circuit comprises a fifth switching transistor and a sixth switching transistor, first terminals of the fifth switching transistor and the sixth switching transistor are respectively connected to second terminals of the fifth transistor and the sixth transistor, second terminals of the fifth switching transistor and the sixth switching transistor are connected to output terminals of the blind element circuit and the sensing element circuit, gates of the fifth switching transistor and the sixth switching transistor respectively receive a control signal to be alternately turned on or off, so that the blind element circuit generates a dark field current according to the bias of the operational amplifier, or the sensing element circuit generates a thermal current according to the bias of the operational amplifier.
6. The focal plane infrared sensor of claim 5, wherein the third transistor, fourth transistor, fifth transistor, sixth transistor, fifth switching transistor, and sixth switching transistor each comprise a number of individual transistors connected in parallel, the size of a single transistor in the third transistor is the same as that of a single transistor in the fourth transistor, the size of a single transistor in the fifth transistor is the same as that of a single transistor in the sixth transistor, the size of each transistor in the fifth switching transistor and the sixth switching transistor is the same, and the number of the fifth transistors is proportional to the number of the transistors in the sixth switching transistor, equal in proportional relation to the number of individual transistors in the third and fourth transistors and also equal in proportional relation to the number of individual transistors in the fifth and sixth switching transistors.
7. The focal plane infrared sensor of claim 6, wherein the number proportional relationship is equal to the number of blind cell resistors.
8. The focal plane infrared sensor of claim 1, wherein the integrating circuit is a capacitive feedback transimpedance amplifier (CTIA) architecture comprising a transimpedance amplifier, an integrating capacitor, and an integrating reset switch, wherein a first terminal of the integrating capacitor is connected to a negative input terminal of the transimpedance amplifier, a second terminal of the integrating capacitor is connected to an output terminal of the transimpedance amplifier, a positive input terminal of the transimpedance amplifier receives a second reference voltage signal, a first terminal of the integrating reset switch is connected to a negative input terminal of the transimpedance amplifier, a second terminal of the integrating reset switch is connected to an output terminal of the transimpedance amplifier, and the integrating reset switch is configured to receive an integrating reset signal during auto-clear to reset the integrating capacitor.
9. The focal plane infrared sensor of claim 8 wherein the integration circuit further comprises an integration control switch connected between the subtraction circuit and the negative input of the transimpedance amplifier for controlling the cutoff of integration.
10. The focal plane infrared sensor of claim 8, wherein the integrating circuit further comprises a third sampling capacitor connected between the negative input of the transimpedance amplifier and ground.
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| CN202021698101.8U CN213209277U (en) | 2020-08-14 | 2020-08-14 | Focal plane infrared sensor |
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| CN114136455A (en) * | 2020-08-14 | 2022-03-04 | 思特威(上海)电子科技股份有限公司 | Focal plane infrared sensor and signal reading method thereof |
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| CN114136455A (en) * | 2020-08-14 | 2022-03-04 | 思特威(上海)电子科技股份有限公司 | Focal plane infrared sensor and signal reading method thereof |
| CN114136455B (en) * | 2020-08-14 | 2024-07-02 | 思特威(上海)电子科技股份有限公司 | Focal plane infrared sensor and signal reading method thereof |
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