CN213025339U - AC common voltage generating circuit and liquid crystal display device - Google Patents

Abstract

The utility model relates to a liquid crystal display's technical field, the embodiment of the utility model discloses a production circuit and liquid crystal display device of alternating current public voltage, this production circuit of alternating current public voltage includes: a frequency divider dividing the frame start signal by four to output an auxiliary signal; the processor is connected with the frequency divider to receive the auxiliary signal and triggers the generation of the starting signal by the auxiliary signal edge in the narrow visual angle display mode; and the signal source is connected with the processor to receive the starting signal and generate the alternating public voltage under the control of the starting signal. The utility model discloses an alternating current public voltage's production circuit and liquid crystal display device can effectively avoid the appearance of picture scintillation phenomenon under the narrow visual angle display mode.

Description

AC common voltage generating circuit and liquid crystal display device

Technical Field

The present invention relates to a liquid crystal display device, and more particularly, to a circuit for generating an ac common voltage and a liquid crystal display device.

Background

With the development of the technology, people have higher and higher peep-proof requirements on the liquid crystal display device, and the liquid crystal display device with switchable wide and narrow viewing angles is produced. At present, there is a Hybrid Viewing Angle (HVA) switching technology, which is a technology for switching Viewing angles by switching ac and dc of a common voltage, where the dc common voltage corresponds to a wide Viewing Angle display mode and the ac common voltage corresponds to a narrow Viewing Angle display mode.

Fig. 1 is a diagram illustrating a view switching signal HVA, a frame start signal STV, a driving SOURCE signal SOURCE, and an ac common voltage ACVCOM in a narrow viewing angle display mode in the prior art, wherein the view switching signal HVA controls switching of the display mode, the frame start signal STV controls turning on of a frame image, and the driving SOURCE signal SOURCE is applied to the SOURCE of the array transistor to control corresponding sub-pixel gray levels. Referring to fig. 1, the liquid crystal display device switches to the narrow viewing angle display mode when the viewing angle switching signal HVA is switched to the high level, the frame start signal STV and the driving SOURCE signal SOURCE perform the first level switching in the narrow viewing angle mode in synchronization with the viewing angle switching signal HVA, and the driving SOURCE signal SOURCE performs the level switching every two frames in the subsequent process to perform the voltage polarity change. In order to avoid the flicker phenomenon in the narrow viewing angle display mode, the ac common voltage ACVCOM needs to maintain a period waveform that decreases and then increases during the display of two frames of the same polarity of the driving SOURCE signal SOURCE, as shown in the ACVCOM case 1 or the ACVCOM case 3 in fig. 1.

However, the ac common voltage generating circuit generates the ac common voltage ACVCOM according to the frame start signal STV, and thus the ac common voltage ACVCOM condition 2 or the ac common voltage ACVCOM condition 4 shown in fig. 1 is generated after the viewing angle switching signal HVA is pulled up, which obviously cannot satisfy the requirement of avoiding the flicker of the picture in the narrow viewing angle display mode.

SUMMERY OF THE UTILITY MODEL

In order to solve the problems existing in the prior art, the utility model provides an exchange public voltage's production circuit and liquid crystal display device can effectively avoid the appearance of picture scintillation phenomenon under the narrow visual angle display mode.

According to the utility model discloses an aspect provides an exchange public voltage's production circuit, include:

a frequency divider dividing the frame start signal by four to output an auxiliary signal;

the processor is connected with the frequency divider to receive the auxiliary signal and trigger the generation of a starting signal by the auxiliary signal edge in a narrow viewing angle display mode;

and the signal source is connected with the processor to receive the starting signal and generate the alternating public voltage under the control of the starting signal.

Optionally, the processor comprises:

the first trigger is connected with the frequency divider to receive the auxiliary signal and generate a first sub-signal triggered by the rising edge of the auxiliary signal in the narrow viewing angle display mode; and/or the presence of a gas in the gas,

the second trigger is connected with the frequency divider to receive the auxiliary signal and is triggered by the falling edge of the auxiliary signal to generate a second sub-signal in the narrow viewing angle display mode;

wherein the first sub-signal and/or the second sub-signal belong to the activation signal.

Optionally, the first flip-flop comprises: a first D flip-flop, wherein,

a data input end of the first D trigger receives a visual angle switching signal;

the clock input end of the first D flip-flop is connected with the output end of the frequency divider to receive the auxiliary signal;

the set input end and the reset input end of the first D trigger are grounded;

and the non-inverting output end of the first D flip-flop outputs the first sub-signal.

Optionally, the second flip-flop comprises: a second D flip-flop, the processor further comprising an inverter, wherein,

a data input end of the second D trigger receives a visual angle switching signal;

the input end of the inverter is connected with the output end of the frequency divider to receive the auxiliary signal, and the clock input end of the second D flip-flop is connected with the output end of the inverter;

the set input end and the reset input end of the second D trigger are grounded;

and the non-inverting output end of the second D flip-flop outputs the second sub-signal.

Optionally, in a case that the processor includes the first flip-flop and the second flip-flop, the processor further includes: or a door, wherein,

the OR gate and the first flip-flop are connected to receive the first sub-signal;

the OR gate and the second flip-flop are connected to receive the second sub-signal;

and the OR gate performs OR operation on the first sub-signal and the second sub-signal, and is also connected with the signal source to input an operation result of the OR operation to the signal source.

Optionally, the processor further comprises:

and the first switch is arranged on the connecting line of the first trigger and the signal source, receives the visual angle switching signal and is switched to a closed state when the visual angle switching signal switches the display mode to the wide visual angle display mode.

Optionally, the processor further comprises:

and the second switch is arranged on the second trigger and the signal source connecting line, receives the visual angle switching signal and is switched to a closed state when the visual angle switching signal switches the display mode to the wide visual angle display mode.

Optionally, the first switch and the second switch are tri-state gates, and the tri-state gates receive the view switching signal through control terminals thereof to control the switches by the view switching signal.

Optionally, the processor further includes a data collector, and the first flip-flop and the second flip-flop are connected through the data collector and the frequency divider, respectively.

Optionally, the frequency divider comprises: a third D flip-flop and a fourth D flip-flop, wherein,

a clock input end of the third D trigger receives the frame starting signal, a data input end is connected with an inverted output end, and a set input end and a reset input end are grounded;

the in-phase output end of the third D trigger is connected with the clock input end of the fourth D trigger;

and the data input end and the reverse phase output end of the fourth D trigger are connected, the set input end and the reset input end are grounded, and the in-phase output end outputs the auxiliary signal.

According to a second aspect of the present invention, there is provided a liquid crystal display device, comprising: the circuit for generating an ac common voltage according to the first aspect.

The utility model has the advantages that:

the generation circuit of the alternating common voltage comprises: the display device comprises a frequency divider, a processor and a signal source, wherein the frequency divider divides a frame starting signal by four to output an auxiliary signal, the processor triggers the generation of a starting signal by an auxiliary signal edge in a narrow viewing angle display mode, and the signal source generates an alternating current public voltage under the control of the starting signal. The auxiliary signal obtained by dividing the frame starting signal by four is a signal synchronous with the driving source signal, so that the starting signal triggered by the auxiliary signal edge ensures that the alternating current common voltage is only triggered at the edge of the driving source signal, and the alternating current common voltage maintains a periodic waveform which is reduced first and then increased during the display period of two frames of pictures with the same polarity of the driving source signal, thereby effectively avoiding the picture flicker phenomenon under the narrow viewing angle display mode.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 is a diagram illustrating a corresponding diagram of signals in a narrow viewing angle display mode in the prior art;

fig. 2 is a schematic diagram showing a structure of a circuit for generating ac common voltage according to the present invention;

fig. 3 shows a corresponding schematic diagram of signals in the present invention;

fig. 4 is a schematic diagram showing another structure of the ac common voltage generating circuit according to the present invention;

fig. 5 is a partial circuit diagram of the ac common voltage generating circuit according to the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described below in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 2 is a schematic diagram of a circuit for generating an ac common voltage. Referring to fig. 2, the ac common voltage generating circuit 100 includes: a frequency divider 110 dividing the frame start signal STV by four to output an auxiliary signal S-Sync; a processor 120 connected to the frequency divider 110 to receive the auxiliary signal S-Sync and to trigger generation of the start signal S0 by an edge of the auxiliary signal S-Sync in the narrow viewing angle display mode; the signal source 130 is connected to the processor 120 to receive the enable signal S0 and generate the ac common voltage ACVCOM under the control of the enable signal S0.

Specifically, the auxiliary signal S-Sync is a signal obtained by dividing the frame start signal STV by four, and thus, in the case where the frame start signal STV is a square wave signal of frequency f1, the auxiliary signal S-Sync is a square wave signal of frequency f2, where f2 is f 1/4. For example, if f1 is 60Hz, f2 is 15 Hz. Correspondingly, if the period of the frame start signal STV is T1 and the period of the auxiliary signal S-Sync is T2, T2 is 4 × T1. Referring to fig. 1, the period of the driving SOURCE signal SOURCE is 4 times the period of the frame start signal STV, and thus, the auxiliary signal S-Sync and the driving SOURCE signal SOURCE are synchronized. The amplitude of the auxiliary signal S-Sync is set, for example, in the range of 0-5V.

Fig. 3 is a schematic diagram of the signal mapping in the present invention. Referring to fig. 2 and 3, the processor 120 may receive the viewing angle switching signal HVA and determine whether the liquid crystal display device is in the narrow viewing angle display mode according to the viewing angle switching signal HVA. Exemplarily, the viewing angle switching signal HVA is in a low level state, and the liquid crystal display device is in a wide viewing angle display mode; when the viewing angle switching signal HVA is in a high level state, the liquid crystal display device is in a narrow viewing angle display mode.

The processor 120 triggers the generation of the start signal S0 by the edge of the auxiliary signal S-Sync in the narrow viewing angle display mode, which may be the generation of the first sub-signal S1 at the rising edge of the auxiliary signal S-Sync when the viewing angle switching signal HVA is at the high level, or the generation of the second sub-signal S2 at the falling edge of the auxiliary signal S-Sync (the first sub-signal S1 and the second sub-signal S2 belong to the start signal S0). Illustratively, the signal source 130 starts to generate the ac common voltage ACVCOM when the first sub-signal S1 and the second sub-signal S2 are pulled high, and terminates the generation of the ac common voltage ACVCOM when the first sub-signal S1 and the second sub-signal S2 are switched to the low level.

It should be noted that the first sub-signal S1 and the second sub-signal S2 are switched to the high level according to the auxiliary signal S-Sync, but the first sub-signal S1 and the second sub-signal S2 are switched to the low level according to the viewing angle switching signal HVA, that is, the first sub-signal S1 and the second sub-signal S2 are switched to the low level when the viewing angle switching signal HVA switches the display mode of the liquid crystal display device to the wide viewing angle display mode.

In the embodiment of the present invention, the auxiliary signal S-Sync generated by the frequency divider 110 is a signal synchronized with the SOURCE signal SOURCE, and therefore the start signal S0 triggered by the edge of the auxiliary signal S-Sync ensures that the ac common voltage ACVCOM can only trigger the edge of the SOURCE signal SOURCE, so that the ac common voltage ACVCOM maintains a periodic waveform that decreases first and increases later during the display of two frames of pictures with the same polarity of the SOURCE signal SOURCE, thereby effectively avoiding the occurrence of the picture flicker phenomenon in the narrow viewing angle display mode.

Fig. 4 is a schematic diagram of another structure of the ac common voltage generating circuit 100. Referring to fig. 4, in an alternative embodiment, processor 120 includes: a data collector 121; the first flip-flop 122, and the frequency divider 110 are connected through the data collector 121 to receive the auxiliary signal S-Sync and generate the first sub-signal S1 triggered by the rising edge of the auxiliary signal S-Sync in the narrow viewing angle display mode; and, the second flip-flop 124, and the frequency divider 110 are connected through the data collector 121 to receive the auxiliary signal S-Sync and generate the above-mentioned second sub-signal S2 triggered by the falling edge of the auxiliary signal S-Sync in the narrow viewing angle display mode.

In other embodiments, the processor 120 may include one of the two flip-flops, the first flip-flop 122 and the second flip-flop 124. If the processor 120 only includes the first flip-flop 122, the signal SOURCE 130 generates the ac common voltage ACVCOM only under the control of the first sub-signal S1, that is, the ac common voltage ACVCOM is triggered at the rising edge of the driving SOURCE signal SOURCE; if the processor 120 only includes the second flip-flop 123, the signal SOURCE 130 generates the ac common voltage ACVCOM only under the control of the second sub-signal S2, that is, the ac common voltage ACVCOM is triggered at the falling edge of the driving SOURCE signal SOURCE. In both cases, the cost of the device is effectively controlled since the processor 120 includes only a single flip-flop.

If the processor 120 includes both the first flip-flop 122 and the second flip-flop 123, the processor 120 may add an or gate 126 to enable the signal source 130 to generate the ac common voltage ACVCOM under the control of the first sub-signal S1 and the second sub-signal S2, as shown in fig. 4. Wherein the or gate 126 and the first flip-flop 122 are connected to receive the first sub-signal S1; the or gate 126 and the second flip-flop 124 are connected to receive the second sub-signal S2; and the or gate 126 performs an or operation on the first sub-signal S1 and the second sub-signal S2, and the or gate 126 is further connected to the signal source 130 to input an operation result S0 of the or operation to the signal source 130. Specifically, referring to fig. 3, the operation result S0 obtained by performing the or operation on the first sub-signal S1 and the second sub-signal S2 is the second sub-signal S2, because the auxiliary signal S-sync has a rising edge after the first falling edge after the view switching signal HVA is switched to the high level; if the auxiliary signal S-sync has a falling edge after a first rising edge after the view switching signal HVA is switched to a high level, the operation result S0 obtained by performing or operation on the first sub-signal S1 and the second sub-signal S2 is the first sub-signal S1. It can be seen from this that: in the case where the processor 120 includes both the first and second flip-flops 122 and 123, it can be ensured that the ac common voltage ACVCOM is triggered at the first edge of the SOURCE signal SOURCE, which has an advantage of generating the ac common voltage ACVCOM in time compared to triggering the ac common voltage ACVCOM only at the first rising edge or only at the first falling edge of the SOURCE signal SOURCE.

Further, referring to fig. 4, the processor 120 further includes: a first switch 123 provided on a connection line between the first flip-flop 122 and the signal source 130; a second switch 125 provided on a connection line between the second flip-flop 124 and the signal source 130 (here, the first switch 123 and the second switch 125 are connected to the signal source 130 via the or gate 126); the first switch 123 and the second switch 125 respectively receive the viewing angle switching signal HVA and switch to an off state when the viewing angle switching signal HVA switches the display mode to the wide viewing angle display mode. That is, if the viewing angle switching signal HVA switches the display mode to the narrow viewing angle display mode, the first switch 123 is turned on to output the first sub-signal S1, and the second switch 125 is turned on to output the second sub-signal S2; if the viewing angle switching signal HVA switches the display mode to the wide viewing angle display mode, the first switch 123 and the second switch 125 are both turned off, the signal source 130 receives the low-level enable signal S0, and the signal source 130 no longer outputs the ac common voltage ACVCOM, so that the ac common voltage ACVCOM is cut off in time when the display mode of the liquid crystal display device is switched from the narrow viewing angle to the wide viewing angle.

Fig. 5 is a partial circuit diagram of the ac common voltage generating circuit 100. Referring to fig. 5, a detailed circuit configuration of the frequency divider 110 and the processor 120 will be described.

Referring to fig. 5, the frequency divider 110 specifically includes: a third D flip-flop U3 and a fourth D flip-flop U4, wherein a clock input terminal CLF of the third D flip-flop U3 receives a frame start signal STV, a data input terminal D is connected with an inverted output terminal Q, and a set input terminal PR and a reset input terminal CLR are grounded; the non-inverting output Q of the third D flip-flop U3 is connected with the clock input CLK of the fourth D flip-flop U4; the data input end D of the fourth D trigger U4 is connected with the inverted output end-Q, the set input end PR and the reset input end CLR are grounded, and the in-phase output end Q outputs an auxiliary signal S-Sync.

Further, referring to fig. 4 and 5, the first flip-flop 122 includes a first D flip-flop U1, wherein a data input D of the first D flip-flop U1 receives the view switching signal HVA; the clock input CLK of the first D flip-flop U1 is connected to the output of the frequency divider 110 to receive the auxiliary signal S-Sync; the set input terminal PR and the reset input terminal CLR of the first D flip-flop U1 are grounded; the non-inverting output Q of the first D flip-flop U1 outputs a first sub-signal S1.

Further, referring to fig. 5, the second flip-flop 124 includes a second D flip-flop U2, and the processor 120 further includes an inverter a1, wherein a data input D of the second D flip-flop U2 receives the view switching signal HVA; the input of the inverter a1 is connected to the output of the frequency divider 110 to receive the auxiliary signal S-Sync, the clock input CLK of the second D flip-flop U2 is connected to the output of the inverter a 1; the set input terminal PR and the reset input terminal CLR of the second D flip-flop U2 are grounded; the non-inverting output Q of the second D flip-flop U2 outputs a second sub-signal S2.

Further, referring to fig. 5, the first switch 123 is a tri-state gate TS1, the second switch 125 is a tri-state gate TS2, and the tri-state gate TS1 and the tri-state gate TS2 receive the viewing angle switching signal HVA through respective control terminals to control the switch by the viewing angle switching signal HVA, wherein the viewing angle switching signal HVA switches the display mode to the narrow viewing angle, then the tri-state gate TS1 and the tri-state gate TS2 are turned on, and the OR gate OR1 receives the first sub-signal S1 and the second sub-signal S2 and outputs a start signal S0 obtained by performing an OR operation on the first sub-signal S1 and the second sub-signal S2; when the viewing angle switching signal HVA switches the display mode to the wide viewing angle, the tri-state gate TS1 and the tri-state gate TS2 are turned off, and the OR gate OR1 outputs the low-level enable signal S0.

The circuit of the processor 120 shown in fig. 5 may be integrated on a chip, the frequency divider 110 as an external auxiliary device of the chip may input the auxiliary signal S-Sync to the chip through a preset I/O interface on the chip, and of course, the chip is further provided with an I/O interface for receiving various signals such as the view switching signal HVA and the power signal, which is not described herein.

Correspondingly, the utility model also provides a liquid crystal display device, this liquid crystal display device include above the production circuit of class common voltage to reach the technological effect of effectively avoiding picture scintillation under the narrow visual angle display mode.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated.

Claims (10)

1. A circuit for generating an ac common voltage, comprising:

a frequency divider dividing the frame start signal by four to output an auxiliary signal;

the processor is connected with the frequency divider to receive the auxiliary signal and trigger the generation of a starting signal by the auxiliary signal edge in a narrow viewing angle display mode;

and the signal source is connected with the processor to receive the starting signal and generate the alternating public voltage under the control of the starting signal.

2. The ac common voltage generating circuit according to claim 1, wherein said processor comprises:

the first trigger is connected with the frequency divider to receive the auxiliary signal and generate a first sub-signal triggered by the rising edge of the auxiliary signal in the narrow viewing angle display mode; and/or the presence of a gas in the gas,

the second trigger is connected with the frequency divider to receive the auxiliary signal and is triggered by the falling edge of the auxiliary signal to generate a second sub-signal in the narrow viewing angle display mode;

wherein the first sub-signal and/or the second sub-signal belong to the activation signal.

3. The ac common voltage generation circuit according to claim 2, wherein said first flip-flop includes: a first D flip-flop, wherein,

a data input end of the first D trigger receives a visual angle switching signal;

the clock input end of the first D flip-flop is connected with the output end of the frequency divider to receive the auxiliary signal;

the set input end and the reset input end of the first D trigger are grounded;

and the non-inverting output end of the first D flip-flop outputs the first sub-signal.

4. The ac common voltage generation circuit according to claim 2, wherein the second flip-flop includes: a second D flip-flop, the processor further comprising an inverter, wherein,

a data input end of the second D trigger receives a visual angle switching signal;

the input end of the inverter is connected with the output end of the frequency divider to receive the auxiliary signal, and the clock input end of the second D flip-flop is connected with the output end of the inverter;

the set input end and the reset input end of the second D trigger are grounded;

and the non-inverting output end of the second D flip-flop outputs the second sub-signal.

5. The ac common voltage generation circuit according to claim 2, wherein in a case where the processor includes the first flip-flop and the second flip-flop, the processor further includes: or a door, wherein,

the OR gate and the first flip-flop are connected to receive the first sub-signal;

the OR gate and the second flip-flop are connected to receive the second sub-signal;

and the OR gate performs OR operation on the first sub-signal and the second sub-signal, and is also connected with the signal source to input an operation result of the OR operation to the signal source.

6. The ac common voltage generating circuit according to claim 2, wherein said processor further comprises:

and the first switch is arranged on a connecting line between the first trigger and the signal source, receives the visual angle switching signal and is switched to a closed state when the visual angle switching signal switches the display mode to the wide visual angle display mode.

7. The ac common voltage generating circuit according to claim 2, wherein said processor further comprises:

and the second switch is arranged on a connecting line between the second trigger and the signal source, receives the visual angle switching signal and is switched to a closed state when the visual angle switching signal switches the display mode to the wide visual angle display mode.

8. The ac common voltage generating circuit according to claim 2, wherein the processor further comprises a data collector, and the first flip-flop and the second flip-flop are connected to the frequency divider through the data collector and the frequency divider, respectively.

9. The ac common voltage generation circuit according to claim 1, wherein said frequency divider comprises: a third D flip-flop and a fourth D flip-flop, wherein,

a clock input end of the third D trigger receives the frame starting signal, a data input end is connected with an inverted output end, and a set input end and a reset input end are grounded;

the in-phase output end of the third D trigger is connected with the clock input end of the fourth D trigger;

and the data input end and the reverse phase output end of the fourth D trigger are connected, the set input end and the reset input end are grounded, and the in-phase output end outputs the auxiliary signal.

10. A liquid crystal display device, comprising: a circuit for generating an alternating common voltage as claimed in any one of claims 1 to 9.

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