CN212872665U - Capacitance change detection circuit - Google Patents
Capacitance change detection circuit Download PDFInfo
- Publication number
- CN212872665U CN212872665U CN202021807753.0U CN202021807753U CN212872665U CN 212872665 U CN212872665 U CN 212872665U CN 202021807753 U CN202021807753 U CN 202021807753U CN 212872665 U CN212872665 U CN 212872665U
- Authority
- CN
- China
- Prior art keywords
- switch
- inverter
- flip
- data comparator
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Measurement Of Resistance Or Impedance (AREA)
Abstract
The utility model relates to a capacitance sensing detection circuit technical field especially relates to a capacitance variation detection circuit, including the electric capacity Csc that awaits measuring, first current source Idcp, second current source Idcn, switch SW0, switch SW1, switch SW10, switch SW11, inverter Inv1, inverter Inv2, inverter Inv3, inverter Inv4, buffer Buf1, buffer Buf2, data comparator and electric capacity group; the utility model discloses circuit structure is simple, need not carry out analog-to-digital conversion through the ADC circuit, and it is simple to judge the comparative process, can save the consumption more than 80%, can make duration increase more than 5 times to the applied scene that uses battery powered.
Description
Technical Field
The utility model relates to a capacitance sensing detection circuitry technical field especially relates to a capacitance variation detection circuitry.
Background
The principle of the existing capacitive sensing detection circuit is generally as follows: the circuit is provided with an emitting electrode TX and a receiving electrode RX, the capacitance sub-capacitance or mutual capacitance is firstly converted into an electric signal, the voltage signal is subjected to digital processing through an ADC circuit to obtain a specific digital quantization value, and then a decision logic judges and gives a conclusion according to the digital quantization value. As shown in fig. 1, the invention patent with chinese patent publication No. CN107247529A discloses a capacitance sensing detection scheme, and it can be seen from this scheme that the circuit system has a complex structure, needs to be subjected to AD conversion, and needs to be processed by an MCU or a filter in the determination process, and the conversion from capacitance to voltage is susceptible to external interference.
SUMMERY OF THE UTILITY MODEL
To the problem among the prior art, the utility model provides a capacitance variation detection circuit.
In order to realize the technical purpose, the technical proposal of the utility model is that:
a capacitance change detection circuit comprises a capacitor Csc to be detected, a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, a switch SW10, a switch SW11, an inverter Inv1, an inverter Inv2, an inverter Inv3, an inverter Inv4, a buffer Buf1, a buffer Buf2, a data comparator and a gating capacitor group;
one end of the capacitor Csc to be tested is grounded, and the other end of the capacitor Csc to be tested is respectively connected with one end of the switch SW0, one end of the switch SW1 and the input end of the inverter Inv 1;
the output end of the inverter Inv1 is connected to the input end of the inverter Inv 2;
the output end of the inverter Inv2 is connected to the input end of the buffer Buf 1;
the output end of the Buf1 buffer is connected with the first input end of the data comparator;
the gating capacitor group comprises M +1 capacitors and M +1 switches, each capacitor is matched with one switch, one end of each of the M +1 capacitors is grounded, and the other end of each capacitor is connected with one end of the switch SW10, one end of the switch SW11 and the input end of the inverter Inv3 after passing through the matched switches;
the output end of the inverter Inv3 is connected to the input end of the inverter Inv 4;
the output end of the inverter Inv4 is connected to the input end of the buffer Buf 2;
the output end of the Buf2 buffer is connected with the second input end of the data comparator;
one end of the current source Idcp serves as a VDD end, and the other end of the current source Idcp is connected with the other end of the switch SW0 and the other end of the switch SW10 respectively;
one end of the current source Idcn is used as the ground, and the other end of the current source Idcn is respectively connected with the other end of the switch SW1 and the other end of the switch SW 11;
and the output end of the data comparator is used as the output end of the detection circuit.
Preferably, the data comparator includes a first D flip-flop group, a second D flip-flop group, and an inverter Inv 5; the first D flip-flop group comprises N D flip-flops connected step by step in a frequency division 2 mode, the CLK input end of the first D flip-flop is used as the first input end of the data comparator, and the Q output end of the Nth flip-flop is connected with the input end of the inverter Inv 5; the second D flip-flop group includes N D flip-flops connected step by step in a frequency division by 2 manner, wherein a CLK input terminal of the first D flip-flop is used as a second input terminal of the data comparator, an output terminal of the nth D flip-flop is used as an output terminal of the data comparator, and reset terminals of the N D flip-flops are all connected to an output terminal of the inverter Inv 5.
As can be seen from the above description, the present invention has the following advantages:
the utility model discloses circuit structure is simple, need not participate in the conversion through the ADC circuit and detect, and it is simple to judge the comparative process, can save the consumption more than 80%, can make duration increase more than 5 times to the applied scene that uses battery powered.
Drawings
FIG. 1 is a schematic circuit diagram of a conventional capacitive sensing circuit;
fig. 2 is a schematic diagram of the circuit structure of the present invention;
fig. 3 is a waveform diagram of the signal Vrf and the signal CLK of the present invention;
fig. 4 is a waveform diagram of the signal Vsc and the signal SC _ Bits according to the present invention;
fig. 5 is a schematic circuit diagram of the data comparator of the present invention.
Detailed Description
With reference to fig. 2 to 5, a specific embodiment of the present invention is described in detail, but the present invention is not limited to the claims.
As shown in fig. 2, a capacitance change detection circuit includes a capacitor Csc to be detected, a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, a switch SW10, a switch SW11, an inverter Inv1, an inverter Inv2, an inverter Inv3, an inverter Inv4, a buffer Buf1, a buffer Buf2, a data comparator, and a gating capacitor group;
one end of the capacitor Csc to be tested is grounded, and the other end of the capacitor Csc to be tested is respectively connected with one end of the switch SW0, one end of the switch SW1 and the input end of the inverter Inv 1;
the output end of the inverter Inv1 is connected to the input end of the inverter Inv 2;
the output end of the inverter Inv2 is connected to the input end of the buffer Buf 1;
the output end of the Buf1 buffer is connected with the first input end of the data comparator;
the gating capacitor group comprises M +1 capacitors and M +1 switches, each capacitor is matched with one switch, one end of each capacitor M +1 is grounded, and the other end of each capacitor M +1 is connected with one end of the switch SW10, one end of the switch SW11 and the input end of the inverter Inv3 after passing through the matched switches;
the output end of the inverter Inv3 is connected to the input end of the inverter Inv 4;
the output end of the inverter Inv4 is connected to the input end of the buffer Buf 2;
the output end of the Buf2 buffer is connected with the second input end of the data comparator;
one end of the current source Idcp serves as a VDD end, and the other end of the current source Idcp is connected with the other end of the switch SW0 and the other end of the switch SW10 respectively;
one end of the current source Idcn is used as the ground, and the other end of the current source Idcn is connected with the other end of the switch SW1 and the other end of the switch SW11 respectively;
the output end of the data comparator is used as the output end of the detection circuit.
The working principle of the utility model is as follows:
in the circuit structure shown in fig. 2, the gate capacitor group includes M +1 capacitors (i.e., capacitors Cr0, Cr1, Cr2, … …, Crm-1, Crm) and M +1 switches (i.e., switches SW4, SW5, SW6, … …, SWm +3, SWm +4), and the M +1 switches control the M +1 capacitors, thereby forming a gate capacitor group to be compared with the capacitor Csc to be measured.
Waveforms of the Vrf signal and the CLK signal of the branch where the gating capacitor bank is located are shown in fig. 3, waveforms of the Vsc signal and the SC _ Bits signal of the branch where the capacitor to be measured Csc is located are shown in fig. 4, and if the following conditions exist:
condition 1: when the capacitance value of the capacitor Csc to be measured is equal to the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the pulse width of the signal CLK is the same as that of the signal SC _ Bits, namely the frequency of the signal CLK is the same as that of the signal SC _ Bits;
condition 2: when the capacitance value of the capacitor Csc to be measured is larger than the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the signal CLK is smaller than the pulse width of the signal SC _ Bits, namely the frequency of the signal CLK is larger than the frequency of the signal SC _ Bits;
condition 3: when the capacitance value of the capacitor Csc to be measured is smaller than the sum of the capacitance values of the gating capacitor groups Cr 0-Crm, the signal CLK is larger than the pulse width of the signal SC _ Bits, namely the frequency of the signal CLK is smaller than the frequency of the signal SC _ Bits.
Therefore, a capacitance sensing detection scheme of the analog system is set based on the above conditions, which specifically includes:
by adopting the condition 3, according to the capacitance increment on the capacitance Csc to be detected during touch, selecting the determined gating capacitance from the gating capacitance groups Cr 0-Crm, and when the capacitance Csc to be detected is not pressed, enabling the sum of the gating capacitances Cr 0-Crm to be larger than the capacitance Csc to be detected by a certain proportion (1%, 2%, 4%, 8%, 16% and the like), wherein the frequency of the signal CLK is lower than the frequency of the signal SC _ Bits at the moment; when the capacitor Csc to be detected is pressed, the capacity sum value of the gating capacitors Cr 0-Crm is smaller than the capacity value of the capacitor Csc to be detected after the pressing induction value is superposed on the capacity value of the capacitor Csc to be detected, and the frequency of the signal CLK is higher than the frequency of the signal SC _ Bits. In the above, when a specific gating capacitor is selected, a part or all of the gating capacitors are selected according to the capacitance value of the capacitor to be measured, and the sum of all capacitance values of the gating capacitors is only required to meet the determination condition.
In the above technical solution, the data comparator may adopt the design scheme shown in fig. 4.
As shown in fig. 5, the data comparator includes a first D flip-flop group, a second D flip-flop group, and an inverter Inv 5;
the first D flip-flop group comprises N D flip-flops (namely D flip-flops 1, 2, 3 and … …, N-1 and N) which are connected in a frequency division manner step by step, the CLK input end of the first D flip-flop (namely D flip-flop 1) is used as the first input end of the data comparator (namely a branch where the SC _ Bits signal is located), and the Q output end of the Nth flip-flop (namely D flip-flop N) is connected with the input end of an inverter Inv 5;
the second D flip-flop group includes N D flip-flops (i.e., D flip-flops N +1, N +2, N +3, … …, 2N-1, and 2N) connected in a frequency-division manner by stages, where a CLK input terminal of the first D flip-flop (i.e., D flip-flop N +1) serves as a second input terminal of the data comparator (i.e., a branch in which the CLK signal is located), an output terminal of the nth D flip-flop (D flip-flop 2N) serves as an output terminal of the data comparator, and reset terminals of the N D flip-flops are all connected to an output terminal of the inverter Inv 5.
The working principle of the data comparator is as follows:
1. the connection modes of N D triggers of the first D trigger group and the second D trigger group are the same, and a halving frequency progressive connection mode is adopted;
the first D trigger group where the SC _ Bits signal is located is in cascade connection, has no reset and always works circularly;
3, the second D flip-flop group where the CLK signal is located is cascaded with a reset function, and the reset signal is a signal obtained by inverting the output signal of the last stage of the first D flip-flop group through the inverter Inv 5;
4. the last stage of the second D flip-flop group outputs as the output of the data comparator: after the signal CLK cascade statistics is full, if the signal SC _ Bits is not full, the INT interruption is changed from 0 to 1, and the output end of the data comparator sends an INT interruption signal; before the CLK cascade statistics is full, if the signal SC _ Bits is full, the output of the last stage of the signal SC _ Bits statistics is changed from 0 to 1, and then the output is changed from 1 to 0 after inversion, so that all the CLK cascade statistics circuits are cleared from 0, and the INT interrupt signal is always 0.
When the technical scheme of the data comparator is applied to the technical scheme shown in fig. 1, when the capacitor Csc to be measured is not pressed, the sum of the gated capacitors Cr 0-Crm is larger than the capacitor Csc to be measured by a certain proportion (the proportion can be designed to be 1%, 2%, 4%, 8%, 16%, etc.), at this time, the frequency of the signal CLK is lower than that of the signal SC _ Bits, the SC _ Bits signal statistics is full first, and the second D flip-flop group where the signal CLK is located is executed to count 0; when the capacitor Csc to be detected is pressed, the sum of the gating capacitors Cr 0-Crm is smaller than the capacitance value of the capacitor Csc to be detected after the capacitance value is superposed with the pressing induction value, the frequency of the signal CLK is higher than that of the signal SC _ Bits, the signal CLK cascade statistics is completed before the signal SC _ Bits statistics, the INT interruption is changed from 0 to 1, an INT interruption signal is sent out, the notification is triggered, and the change of the capacitor Csc to be detected is detected.
To sum up, the utility model has the advantages of it is following:
the utility model discloses circuit structure is simple, does not need the ADC circuit to participate in the conversion and detects, and it is simple to judge the comparative process, can save the consumption more than 80%, can make duration increase more than 5 times to the applied scene that uses battery powered.
It should be understood that the above detailed description of the present invention is only for illustrative purposes and is not limited to the technical solutions described in the embodiments of the present invention. It will be understood by those skilled in the art that the present invention may be modified and equivalents may be substituted to achieve the same technical effects; as long as the use requirement is satisfied, the utility model is within the protection scope.
Claims (2)
1. A capacitance change detection circuit, characterized by: the circuit comprises a capacitor Csc to be tested, a first current source Idcp, a second current source Idcn, a switch SW0, a switch SW1, a switch SW10, a switch SW11, an inverter Inv1, an inverter Inv2, an inverter Inv3, an inverter Inv4, a buffer Buf1, a buffer Buf2, a data comparator and a gating capacitor group;
one end of the capacitor Csc to be tested is grounded, and the other end of the capacitor Csc to be tested is respectively connected with one end of the switch SW0, one end of the switch SW1 and the input end of the inverter Inv 1;
the output end of the inverter Inv1 is connected to the input end of the inverter Inv 2;
the output end of the inverter Inv2 is connected to the input end of the buffer Buf 1;
the output end of the Buf1 buffer is connected with the first input end of the data comparator;
the gating capacitor group comprises M +1 capacitors and M +1 switches, each capacitor is matched with one switch, one end of each of the M +1 capacitors is grounded, and the other end of each capacitor is connected with one end of the switch SW10, one end of the switch SW11 and the input end of the inverter Inv3 after passing through the matched switches;
the output end of the inverter Inv3 is connected to the input end of the inverter Inv 4;
the output end of the inverter Inv4 is connected to the input end of the buffer Buf 2;
the output end of the Buf2 buffer is connected with the second input end of the data comparator;
one end of the current source Idcp serves as a VDD end, and the other end of the current source Idcp is connected with the other end of the switch SW0 and the other end of the switch SW10 respectively;
one end of the current source Idcn is used as the ground, and the other end of the current source Idcn is respectively connected with the other end of the switch SW1 and the other end of the switch SW 11;
and the output end of the data comparator is used as the output end of the detection circuit.
2. The capacitance change detection circuit according to claim 1, wherein: the data comparator includes a first D flip-flop group, a second D flip-flop group, and an inverter Inv 5;
the first D flip-flop group comprises N D flip-flops connected step by step in a frequency division 2 mode, the CLK input end of the first D flip-flop is used as the first input end of the data comparator, and the Q output end of the Nth flip-flop is connected with the input end of the inverter Inv 5;
the second D flip-flop group includes N D flip-flops connected step by step in a frequency division by 2 manner, wherein a CLK input terminal of the first D flip-flop is used as a second input terminal of the data comparator, an output terminal of the nth D flip-flop is used as an output terminal of the data comparator, and reset terminals of the N D flip-flops are all connected to an output terminal of the inverter Inv 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021807753.0U CN212872665U (en) | 2020-08-26 | 2020-08-26 | Capacitance change detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021807753.0U CN212872665U (en) | 2020-08-26 | 2020-08-26 | Capacitance change detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212872665U true CN212872665U (en) | 2021-04-02 |
Family
ID=75190392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021807753.0U Active CN212872665U (en) | 2020-08-26 | 2020-08-26 | Capacitance change detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212872665U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112994682A (en) * | 2021-05-10 | 2021-06-18 | 上海灵动微电子股份有限公司 | Clock frequency divider, microcontroller and phase-locked loop circuit based on switched capacitor |
-
2020
- 2020-08-26 CN CN202021807753.0U patent/CN212872665U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112994682A (en) * | 2021-05-10 | 2021-06-18 | 上海灵动微电子股份有限公司 | Clock frequency divider, microcontroller and phase-locked loop circuit based on switched capacitor |
| CN112994682B (en) * | 2021-05-10 | 2021-08-03 | 上海灵动微电子股份有限公司 | Clock frequency divider, microcontroller and phase-locked loop circuit based on switched capacitor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10408862B2 (en) | Multiple channel capacitive voltage divider scanning method and apparatus | |
| US20110068810A1 (en) | Sensing method and driving circuit of capacitive touch screen | |
| KR102623568B1 (en) | Capacitance detection circuits, sensors, chips and electronics | |
| CN105278776B (en) | Capacitance voltage information sensing circuit and related anti-noise touch control circuit thereof | |
| US20090225044A1 (en) | Determining touch on keys of touch sensitive input device | |
| EP3543668A1 (en) | Capacitance detection circuit, touch detection apparatus and terminal device | |
| CN104794433A (en) | Fingerprint recognition system and fingerprint recognition method | |
| EP3324331B1 (en) | Capacitive sensing circuit | |
| CN101685364B (en) | Sensing device and method for touch panel | |
| CN103699277B (en) | Touch sensing circuit and touch device | |
| CN108777574A (en) | A kind of capacitance touch button circuit | |
| CN212305298U (en) | Environment slowly-varying self-adaptive capacitance induction detection system | |
| CN212872665U (en) | Capacitance change detection circuit | |
| WO2017197574A1 (en) | Capacitance detection device | |
| CN101847070B (en) | Capacitance change detection module taking electric signal change time as detection target | |
| CN205003650U (en) | Capacitive discharge circuit | |
| CN213875939U (en) | Key detection circuit | |
| CN102346607B (en) | Touch sensing circuit and method | |
| CN116185236B (en) | Spaced touch system with high anti-interference capability | |
| CN216819821U (en) | High-speed low-power-consumption capacitive touch detection circuit and chip | |
| CN113054984B (en) | Pressure-sensitive detection circuit, chip, system and pressure-sensitive detection method | |
| Rovere et al. | A 2.1 μW event-driven wake-up circuit based on a level-crossing ADC for pattern recognition in healthcare | |
| CN114124066B (en) | Environment slowly-changing self-adaptive capacitance induction detection system | |
| CN102262487A (en) | Switching type capacitance tracking device of touch panel and operation method thereof | |
| CN213937865U (en) | Fast ping-pong mutual capacitance conversion circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |