CN212750903U - Solar cell - Google Patents
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- CN212750903U CN212750903U CN202022300702.5U CN202022300702U CN212750903U CN 212750903 U CN212750903 U CN 212750903U CN 202022300702 U CN202022300702 U CN 202022300702U CN 212750903 U CN212750903 U CN 212750903U
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Abstract
The application provides a solar cell, which comprises a silicon substrate, a tunneling layer and a polycrystalline silicon layer, wherein the tunneling layer and the polycrystalline silicon layer are sequentially arranged on the back surface of the silicon substrate; the back surface of the silicon substrate is arranged in a pyramid shape, and the height of the suede surface on the back surface of the silicon substrate is set to be 0.5-1.5 mu m. The back of the silicon substrate is provided with the pyramid structure with the set suede height, so that the polycrystalline silicon layer prepared by subsequent deposition is also in a pyramid shape, the contact area of the metal electrode and the polycrystalline silicon layer is increased, the contact performance of the metal electrode and the polycrystalline silicon layer is improved, the contact resistance is reduced, and the conversion efficiency of the solar cell is favorably improved.
Description
Technical Field
The application relates to the technical field of solar cell production, in particular to a solar cell.
Background
In recent years, with the rapid development of photovoltaic technology and markets, the industry also puts higher and higher demands on the conversion efficiency of solar cells. The TOPCon (Tunnel Oxide Passivated Contact) battery has the advantages that the ultrathin Tunnel Oxide layer and the doped polycrystalline silicon layer are prepared on the surface, so that the surface passivation performance is improved, and the open-circuit voltage and the short-circuit current of the battery are effectively improved. The production process of the TOPCon cell generally comprises the steps of cleaning and polishing the surface of a silicon substrate, and then sequentially depositing and preparing the tunneling oxide layer and the doped polysilicon layer, wherein the surface morphology of the silicon substrate has a great influence on the performance of a surface film layer of the silicon substrate. Also disclosed in the art is a POLO-IBC cell that combines the above cell passivation structure with a back cell design to improve cell conversion efficiency. However, the whole production process is complex, the process precision requirement is strict, the battery production cost is high, and the industrial application is difficult.
In view of the above, there is a need for a new solar cell.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a solar cell can improve metal electrode's contact performance, improves battery conversion efficiency.
In order to achieve the above object of the present invention, the present application provides a solar cell, comprising a silicon substrate, a tunneling layer and a polysilicon layer sequentially disposed on the back of the silicon substrate; the back surface of the silicon substrate is arranged in a pyramid shape, and the height of the suede surface on the back surface of the silicon substrate is set to be 0.5-1.5 mu m.
As a further improvement of the application, the front surface of the silicon substrate is also arranged in a pyramid shape, and the height of the textured surface on the front surface of the silicon substrate is set to be 2-4 mu m.
As a further improvement of the present application, the silicon substrate has a first region and a second region; the polysilicon layer comprises a first doped polysilicon layer arranged in the first region and a second doped polysilicon layer arranged in the second region.
As a further improvement of the present application, the first doped polysilicon layer is configured as a boron-doped P-type polysilicon layer; the second doped polysilicon layer is set to be a phosphorus-doped N-type polysilicon layer.
As a further improvement of the application, the first area comprises a plurality of first bar-shaped areas, the second area comprises a plurality of second bar-shaped areas, and the first bar-shaped areas and the second bar-shaped areas are alternately arranged in sequence and are arranged at intervals.
As a further improvement of the application, the width of the first strip-shaped area and the width of the second strip-shaped area are both set to be 40-500 mu m, and the gap width of the first strip-shaped area and the second strip-shaped area is set to be 50-500 mu m.
As a further improvement of the present application, the solar cell further includes a back surface film layer disposed on the back surface of the silicon substrate and a metal electrode, wherein the metal electrode includes a first electrode penetrating the back surface film layer and contacting the first doped polysilicon layer, and a second electrode penetrating the back surface film layer and contacting the second doped polysilicon layer.
As a further improvement of the application, the solar cell further comprises a passivation layer arranged on the front surface of the silicon substrate and an antireflection layer arranged on one side of the silicon substrate, wherein the passivation layer deviates from the antireflection layer.
As a further development of the application, the passivation layer is provided as SiO2And the thickness of the passivation layer is set to be 2-6 nm.
As a further improvement of this application, it includes the neighbouring to subtract the reflection stratum the silicon nitride rete that the passivation layer set up, the refracting index of silicon nitride rete sets up to 2.1 ~ 2.4, and the thickness of this silicon nitride rete sets up to 5 ~ 30 nm.
The beneficial effect of this application is: by adopting the solar cell, the pyramid structure with the established suede height is arranged on the back surface of the silicon substrate, so that the polycrystalline silicon layer prepared by subsequent deposition on the back surface of the silicon substrate is also pyramid-shaped, the contact area between the metal electrode and the polycrystalline silicon layer is increased, the contact performance between the metal electrode and the polycrystalline silicon layer is improved, the contact resistance is reduced, and the conversion efficiency of the cell is favorably improved.
Drawings
FIG. 1 is a schematic structural diagram of a solar cell of the present application;
FIG. 2 is a schematic backside view of a silicon substrate in a solar cell of the present application;
fig. 3 is a schematic main flow chart of a method for manufacturing a solar cell according to the present application.
100-solar cell; 1-a silicon substrate; 11-a first region; 110-a first stripe region; 12-a second region; 120-a second bar; 2-a tunneling layer; 31-a first doped polysilicon layer; 32-a second doped polysilicon layer; 33-an intrinsic polycrystalline silicon layer; 41-a passivation layer; 42-an anti-reflective layer; 5-back surface film layer; 61-a first electrode; 62-second electrode.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. However, the present invention is not limited to the embodiment, and the structural, method, or functional changes made by those skilled in the art according to the embodiment are all included in the scope of the present invention.
Referring to fig. 1, a solar cell 100 provided in the present application includes a silicon substrate 1, a tunneling layer 2 disposed on a back surface of the silicon substrate 1, and a polysilicon layer. Here, the solar cell 100 is a back contact cell, and the silicon substrate 1 is an N-type monocrystalline silicon wafer; the tunneling layer 2 is set to be SiO2Film layer or SiOxNyA film layer; the polysilicon layers include a first doped polysilicon layer 31, a second doped polysilicon layer 32, and an intrinsic polysilicon layer 33, which are alternately arranged in sequence.
The resistivity of the silicon substrate 1 is set to be 0.3-7 omega cm, preferably 0.7-3.5 omega cm; the thickness of the tunneling layer 2 is preferably set to be 0.5-3 nm; the thickness of the polysilicon layer is preferably set to 60nm to 200 nm. Here, the first doped polysilicon layer 31 is a boron-doped P-type polysilicon layer, and the boron doping concentration of the first doped polysilicon layer 31 is 1E 19-5E 20cm-3(ii) a The second doped polysilicon layer 32 is a phosphorus-doped N-type polysilicon layer, and the second doped polysilicon layerThe phosphorus doping concentration of the silicon crystal layer 32 is 1E 20-5E 20cm-3。
The solar cell 100 further comprises a passivation layer 41 and an antireflection layer 42 arranged on the front surface of the silicon substrate 1, wherein the passivation layer 41 is made of SiO2The thickness of the film is set to be 2-6 nm. The antireflection layer 42 may be provided as one of a silicon nitride film, a silicon oxynitride film, a silicon oxide film, or a magnesium fluoride film, or a composite film layer composed of at least two of the foregoing film layers. When antireflection layer 42 sets up to compound rete, the refracting index of different retes reduces from inside to outside gradually, of course, antireflection layer 42 or constitute arbitrary former rete of antireflection layer 42 still can set up to the gradual change membrane. Here, the anti-reflection layer 42 includes a silicon nitride film layer disposed adjacent to the passivation layer 41, the silicon nitride film layer having a refractive index set to 2.1 to 2.4 and a thickness set to 5 to 30nm, and also serving as a hydrogen passivation.
The solar cell further comprises a back surface film layer 5 arranged on one side of the polycrystalline silicon layer, which is far away from the silicon substrate 1, and a metal electrode which penetrates through the back surface film layer 5 and is in contact with the polycrystalline silicon layer. The metal electrodes include a first electrode 61 disposed on the first doped polysilicon layer 31, and a second electrode 62 disposed on the second doped polysilicon layer 32. The first electrode 61 and the second electrode 62 are usually made of silver paste, and are printed and sintered by screen printing, and the silver pastes adopted by the first electrode 61 and the second electrode 62 can be the same or different according to actual product requirements and silver paste performances.
The front surface of the silicon substrate 1 is pyramid-shaped, the height of the suede of the silicon substrate 1 is set to be 2-4 microns, the front surface of the silicon substrate 1 is etched usually by adopting alkaline solution, the arrangement of the height of the suede ensures that the whole suede under the conventional process condition is distributed more uniformly, and the reflectivity of incident light is effectively reduced. The back surface of the silicon substrate 1 is also arranged to be pyramid-shaped, and the height of the texture surface is set to be 0.5-1.5 mu m, so that the polycrystalline silicon layer deposited on the back surface of the silicon substrate 1 is also pyramid-shaped. Here, the textured height of the back surface of the silicon substrate 1 cannot be set too large, which may otherwise affect the deposition preparation of the tunneling layer 2 and the intrinsic amorphous silicon layer. Through the design, under the condition of not changing the metal electrode, the contact areas of the first electrode 61 and the first doped polycrystalline silicon layer 31 and the second electrode 62 and the second doped polycrystalline silicon layer 32 are increased, the contact performance of the metal electrode and the polycrystalline silicon layer is improved, and the contact resistance is reduced.
Referring to fig. 2, the back surface of the silicon substrate 1 has a first region 11 and a second region 12, and the first region 11 is correspondingly provided with a first doped polysilicon layer 31; the second region 12 is correspondingly provided with a second doped polysilicon layer 32. Specifically, the first region 11 includes a plurality of first bar-shaped regions 110, the second region 12 includes a plurality of second bar-shaped regions 120, and the first bar-shaped regions 110 and the second bar-shaped regions 120 are alternately arranged in sequence and are spaced from each other. Here, the widths of the first and second stripe regions 110 and 120 are set to be 40 to 500 μm, and the gap width between adjacent first and second stripe regions 110 and 120 is set to be 50 to 500 μm.
Referring to fig. 3, the method for manufacturing the solar cell 100 includes:
providing a silicon substrate 1, and texturing the silicon substrate 1 for the first time;
preparing a tunneling layer 2 and an intrinsic amorphous silicon layer on the back of a silicon substrate 1;
respectively arranging a first doping source layer and a second doping source layer in a first area 11 and a second area 12 on the back surface of the silicon substrate 1;
annealing to enable the first region 11 and the second region 12 to form a first doped polysilicon layer 31 and a second doped polysilicon layer 32 respectively, wherein the doping types of the first doped polysilicon layer 31 and the second doped polysilicon layer 32 are opposite and are arranged at intervals;
carrying out secondary texturing on the front side of the silicon substrate 1;
and cleaning, coating and metalizing are sequentially carried out to obtain the corresponding solar cell 100.
And etching the silicon substrate by adopting an alkaline solution for the first texturing and the second texturing, wherein the alkaline solution is an aqueous solution of KOH or NaOH or TMAH, and the surface of the silicon substrate 1 can be etched to generate a pyramid-shaped textured structure. The first texturing process controls the height of the textured surface on the back surface of the silicon substrate 1 to be 0.5-1.5 mu m; and the second texturing process controls the height of the textured surface on the front surface of the silicon substrate 1 to be 2-4 mu m. Of course, the first texturing process and the second texturing process can be added with corresponding texturing additives according to actual production requirements.
Before the first texturing is carried out on the silicon substrate 1, firstly, an acid solution or an alkali solution is adopted to carry out rough polishing on the silicon substrate 1, and a mechanical damage layer on the surface of the silicon substrate 1 is removed. The first texturing may be performed only on the back surface of the silicon substrate 1, or may be performed on both sides; the second texturing refers to single-sided texturing of the front side of the silicon substrate 1.
In this embodiment, the tunneling layer 2 is made of SiO2Film layer of said SiO2The film layer is prepared by any one or combination of any two methods of wet chemical oxidation, thermal oxidation and ozone oxidation; the intrinsic amorphous silicon layer is prepared by LPCVD or PECVD.
The phrase "the first doping source layer and the second doping source layer are respectively disposed in the first region 11 and the second region 12 on the back surface of the silicon substrate 1" means that boron slurry is disposed on the intrinsic amorphous silicon layer of the first region 11 on the back surface of the silicon substrate 1, and phosphorus slurry is disposed on the intrinsic amorphous silicon layer of the second region 12 on the back surface of the silicon substrate 1. Specifically, the boron paste and the phosphorus paste may be transferred to the back surface of the silicon substrate 1 by screen printing or spraying, or a patterned first doping source layer and a patterned second doping source layer may be directly formed on the back surface of the silicon substrate 1 by 3D printing.
The temperature of the annealing step is set to 850-1100 ℃, the intrinsic amorphous silicon layer is converted into a polysilicon layer through a high temperature process, and meanwhile, the first region 11 and the second region 12 respectively form a boron-doped P-type first doped polysilicon layer 31 and a phosphorus-doped N-type second doped polysilicon layer 32. And the annealing step further comprises introducing oxygen into the reaction cavity, so that an oxide layer is formed on the front side of the silicon substrate 1, a mask layer is formed on the back side of the silicon substrate 1, and the introduced oxygen is also favorable for removing a small amount of residual organic components. The oxide layer mainly refers to a silicon oxide layer; the mask layer includes a BSG layer formed on the surface of the first doped polysilicon layer 31, a PSG layer formed on the surface of the second doped polysilicon layer 32, and a silicon oxide layer formed in a gap region between the BSG layer and the PSG layer.
Before the silicon substrate 1 is subjected to the second texturing, an oxide layer on the front surface of the silicon substrate 1 needs to be removed, and a chain type cleaning device can be generally adopted to clean the front surface of the silicon substrate 1; meanwhile, a mask layer on the back surface of the silicon substrate 1 is reserved, and the polycrystalline silicon layer structure on the back surface of the silicon substrate 1 is prevented from being damaged in the second texturing process.
Cleaning the silicon substrate 1 after the second texturing to remove the oxide layer and the mask layer on the surface; and then the cleaned and dried silicon substrate 1 is coated with a film. The film coating step comprises the steps of firstly depositing a passivation layer 41 on the front surface of the silicon substrate 1 by adopting a PECVD method; and preparing an antireflection layer 42 on the surface of one side of the passivation layer 41, which is far away from the silicon substrate 1. Of course, the coating step further includes preparing a back surface film layer 5 on the back surface of the silicon substrate 1, and the specific structures and preparation processes of the back surface film layer 5 and the antireflection layer 42 are not described in detail. Here, the passivation layer 41 is provided as SiO2The thickness of the film is set to be 2-6 nm, and the back of the silicon substrate 1 can be simultaneously deposited to obtain corresponding SiO2The film, i.e. the back surface film layer 5, comprises SiO in contact with the polysilicon layer2And (3) a membrane.
The metallization step is mainly that the given slurry is printed on a back surface film layer 5 on the back surface of the silicon substrate 1 through a screen printing plate; and drying and sintering to enable the slurry to burn through the back surface film layer 5 and form ohmic contact with the polycrystalline silicon layer.
To sum up, the solar cell 100 of the present application combines the polysilicon passivation contact structure with the back contact design, thereby improving the cell conversion efficiency. The preparation method has simple process, and avoids the damage of multiple high-temperature processes to the silicon substrate 1 and the corresponding film structure; forming a corresponding suede structure on the back of the silicon substrate 1 after the first texturing, depositing the tunneling layer 2 and the intrinsic amorphous silicon layer, improving the contact performance of a subsequent metal electrode with the first doped polycrystalline silicon layer 31 and the second doped polycrystalline silicon layer 32, and reducing the contact resistance; and then, the antireflection performance of the front surface of the silicon substrate 1 is ensured through secondary texturing, and the conversion efficiency of the battery is improved.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above list of details is only for the practical implementation of the present invention, and they are not intended to limit the scope of the present invention, and all equivalent implementations or modifications that do not depart from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1. The utility model provides a solar cell, includes the silicon substrate, sets gradually the tunneling layer and the polycrystalline silicon layer at the silicon substrate back, its characterized in that: the back surface of the silicon substrate is arranged in a pyramid shape, and the height of the suede surface on the back surface of the silicon substrate is set to be 0.5-1.5 mu m.
2. The solar cell of claim 1, wherein: the front surface of the silicon substrate is also arranged in a pyramid shape, and the height of the textured surface on the front surface of the silicon substrate is 2-4 mu m.
3. The solar cell of claim 1, wherein: the silicon substrate is provided with a first region and a second region; the polysilicon layer comprises a first doped polysilicon layer arranged in the first region and a second doped polysilicon layer arranged in the second region.
4. The solar cell of claim 3, wherein: the first doped polycrystalline silicon layer is a boron-doped P-type polycrystalline silicon layer; the second doped polysilicon layer is set to be a phosphorus-doped N-type polysilicon layer.
5. The solar cell of claim 3, wherein: the first area comprises a plurality of first strip-shaped areas, the second area comprises a plurality of second strip-shaped areas, and the first strip-shaped areas and the second strip-shaped areas are alternately arranged in sequence and are arranged at intervals.
6. The solar cell of claim 5, wherein: the width of the first strip-shaped area and the width of the second strip-shaped area are both set to be 40-500 mu m, and the width of a gap between the adjacent first strip-shaped area and the adjacent second strip-shaped area is set to be 50-500 mu m.
7. The solar cell of claim 3, wherein: the solar cell also comprises a back surface film layer and a metal electrode which are arranged on the back surface of the silicon substrate, wherein the metal electrode comprises a first electrode which penetrates through the back surface film layer and is contacted with the first doped polycrystalline silicon layer, and a second electrode which penetrates through the back surface film layer and is contacted with the second doped polycrystalline silicon layer.
8. The solar cell of claim 1, wherein: the solar cell further comprises a passivation layer arranged on the front surface of the silicon substrate and an antireflection layer arranged on one side, deviating from the silicon substrate, of the passivation layer.
9. The solar cell of claim 8, wherein: the passivation layer is set to be SiO2And the thickness of the passivation layer is set to be 2-6 nm.
10. The solar cell of claim 8, wherein: the antireflection layer comprises a silicon nitride film layer adjacent to the passivation layer, the refractive index of the silicon nitride film layer is set to be 2.1-2.4, and the thickness of the silicon nitride film layer is set to be 5-30 nm.
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| CN113284982A (en) * | 2021-05-28 | 2021-08-20 | 浙江爱旭太阳能科技有限公司 | Processing technology of IBC battery with passivation contact structure |
| CN114823973A (en) * | 2022-04-20 | 2022-07-29 | 通威太阳能(眉山)有限公司 | P-type back contact solar cell and preparation method thereof |
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