CN212696265U - Printed circuit board and chip package structure - Google Patents
Printed circuit board and chip package structure Download PDFInfo
- Publication number
- CN212696265U CN212696265U CN202021770940.6U CN202021770940U CN212696265U CN 212696265 U CN212696265 U CN 212696265U CN 202021770940 U CN202021770940 U CN 202021770940U CN 212696265 U CN212696265 U CN 212696265U
- Authority
- CN
- China
- Prior art keywords
- pad
- circuit board
- printed circuit
- capacitor
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
本实用新型公开了一种印刷电路板和芯片封装结构，其中，印刷电路板包括：基板；电容焊盘，所述电容焊盘设置在所述基板上，所述电容焊盘包括两个相对设置的水平段和两个相对设置的弯折部，所述弯折部包括竖直段以及两个与所述竖直段的两端连接的倾斜段，所述倾斜段与所述水平段连接；管脚焊盘，所述管脚焊盘设置在所述基板背离所述电容焊盘的一侧；过孔，所述过孔为贯穿所述基板且位于所述管脚焊盘的旁侧，所述倾斜段朝向所述过孔设置。相对于传统的矩形电容焊盘，本实用新型的倾斜段至过孔的距离增大，避免了电容焊盘与过孔之间的干涉，且无需使用埋孔或盲孔，减小了制作成本。
The utility model discloses a printed circuit board and a chip packaging structure, wherein the printed circuit board comprises: a substrate; a capacitor pad, the capacitor pad is arranged on the substrate, and the capacitor pad comprises two oppositely arranged a horizontal section and two oppositely arranged bending parts, the bending part includes a vertical section and two inclined sections connected with both ends of the vertical section, and the inclined sections are connected with the horizontal section; a pin pad, which is arranged on the side of the substrate away from the capacitor pad; a via hole, which penetrates through the substrate and is located on the side of the pin pad, The inclined section is disposed toward the via hole. Compared with the traditional rectangular capacitor pad, the distance from the inclined section to the via hole of the present invention is increased, which avoids the interference between the capacitor pad and the via hole, and does not need to use buried holes or blind holes, thus reducing the manufacturing cost. .
Description
Technical Field
The utility model relates to the field of semiconductor technology, concretely relates to printed circuit board and chip package structure.
Background
With the development of large-scale integrated circuit technology, the operating frequency and power consumption of integrated circuit chips are continuously increased, and the operating frequency and wiring density of printed circuit boards must be increased accordingly. Maintaining good power integrity is also increasingly important in high speed, high density printed circuit board applications. Each power supply pin of the chip is generally connected with a filter capacitor so as to ensure the stability of power supply when current is supplied and reduce the power supply impedance so as to meet the requirement of the integrity of a power supply of a chip packaging structure. However, as the integration of chip packaging is higher and higher, the packaging size is smaller and smaller, and as the number of filter capacitors for packaging such chips on the same layer of the chip is limited, most of the filter capacitors are placed on the back of the chip pins, and a plurality of through holes for leading out signals of each pin are formed in the substrate. The traditional capacitor bonding pad is rectangular, and for a chip packaging structure with high integration level, the capacitor bonding pad and the via hole are interfered with each other due to too small distance, so that the via hole can only be designed into a buried hole or a blind hole in order to avoid interference, and the manufacturing cost of the printed circuit board is increased.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a printed circuit board and chip package structure aims at improving and avoids electric capacity pad and via hole interference at present, is buried hole or blind hole with the via hole design, has increased printed circuit board's cost of manufacture's problem.
In order to achieve the above object, the present invention provides a printed circuit board, including:
a substrate;
the capacitor bonding pad is arranged on the substrate and comprises two horizontal sections arranged oppositely and two bent sections arranged oppositely, each bent section comprises a vertical section and two inclined sections connected with two ends of the vertical section, and the inclined sections are connected with the horizontal sections;
the pin bonding pad is arranged on one side of the substrate, which is far away from the capacitor bonding pad;
the via hole, the via hole run through in the base plate just is located the side of pin pad, the slope section orientation the via hole setting.
Preferably, the capacitor bonding pad is arranged corresponding to the pin bonding pad.
Preferably, the inclined section is a straight section.
Preferably, a copper layer is sputtered on the inner wall surface of the via hole, and the capacitor pad and the pin pad are respectively connected with the copper layer through signal lines.
Preferably, the substrate is provided with a copper ring along an edge of the via hole, and the copper ring is connected with the copper layer.
Preferably, the number of the pin pads and the vias is multiple, and the pin pads and the vias are uniformly arranged on the substrate at intervals.
Preferably, the capacitor pads are equidistant from the surrounding vias.
Furthermore, the utility model also provides a chip package structure, include chip, filter capacitor and as above-mentioned printed circuit board, the chip subsides are established on the pin pad, filter capacitor pastes and establishes on the electric capacity pad.
Preferably, the Chip Package structure is BGA (Ball Grid Array), LGA (Land Grid Array), or CSP (Chip Scale Package).
The technical scheme of the utility model, electric capacity pad and pin pad set up respectively at the both sides that the base plate deviates from, can reduce chip package structure's whole size, set up the via hole at the side of pin pad, and this via hole is for the through-hole that runs through the base plate, and the cost of manufacture is low, the utility model discloses an electric capacity pad includes the horizontal segment of two relative settings and the kink of two relative settings, the kink include vertical section and two with the slope section that the both ends of vertical section are connected, the slope section with the horizontal segment is connected, and the slope section is towards the via hole setting, for traditional rectangle electric capacity pad, because the utility model discloses a distance increase of slope section to via hole has avoided the interference between electric capacity pad and the via hole, and need not to use buried hole or blind hole, has reduced the cost of manufacture.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic diagram of a printed circuit board according to an embodiment of the present invention;
fig. 2 is a schematic diagram illustrating a comparison between a capacitor pad according to an embodiment of the present invention and a conventional rectangular pad;
fig. 3 is a schematic diagram illustrating a comparison between a distance between a capacitor pad and a via hole and a distance between a conventional rectangular pad and a via hole according to an embodiment of the present invention.
The reference numbers illustrate:
| 1 | |
2 | |
| 21 | Horizontal segment | 22 | A |
| 221 | Inclined |
222 | |
| 3 | |
4 | Via |
| 41 | |
5 | |
| 6 | Rectangular bonding pad |
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely below, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative efforts belong to the protection scope of the present invention.
In addition, the technical solutions between the embodiments of the present invention can be combined with each other, but it is necessary to be able to be realized by a person having ordinary skill in the art as a basis, and when the technical solutions are contradictory or cannot be realized, the combination of such technical solutions should be considered to be absent, and is not within the protection scope of the present invention.
As shown in fig. 1 and 2, the present invention provides a printed circuit board, including:
a substrate 1;
the capacitor bonding pad 2 is arranged on the substrate 1, the capacitor bonding pad 2 comprises two horizontal sections 21 arranged oppositely and two bent sections 22 arranged oppositely, the bent sections 22 comprise vertical sections 222 and two inclined sections 221 connected with two ends of the vertical sections 222, and the inclined sections 221 are connected with the horizontal sections 21;
the pin bonding pad 3 is arranged on one side of the substrate 1, which is far away from the capacitor bonding pad 2;
and the via hole 4 penetrates through the substrate 1 and is positioned beside the pin pad 3, and the inclined section 221 is arranged towards the via hole 4.
As shown in fig. 2, the conventional capacitor pad 2 is a rectangular pad 6 (indicated by a dotted line), and the present invention forms a bending portion 22 protruding to both sides on the basis of the rectangular pad 6. For traditional rectangle pad 6, the utility model discloses a relative rectangle pad 6's of horizontal segment 21 width reduces, kink 22 highly unchangeable, slope section 221 is from the horizontal part to the direction slope of vertical section 222, a part of slope section 221 is located original rectangle pad 6, another part surpasss rectangle pad 6, vertical section 222 is located outside rectangle pad 6, such design makes the area of the electric capacity pad 2 after the change shape not less than original rectangle pad 6's area, filter capacitance's paster is not influenced, the design of slope section 221 makes electric capacity pad 2 to via hole 4's distance increase, the interference between electric capacity pad 2 and the via hole 4 has been avoided. As shown in fig. 3, the outer diameter of the via 4 is r, the distance between the center of the via 4 and the rectangular pad 6 is d1, and if d1-r < 0.1mm, it means that there is interference between the rectangular pad 6 and the via 4, and only the filter capacitor can be omitted or the via 4 can be designed as a buried via or a blind via.
Vias are one of the important components of multilayer printed circuit boards, and the cost of drilling typically accounts for 30% to 40% of the cost of board fabrication. In effect, vias can be divided into two categories: one is used for electrical connection between layers; secondly, the device is used for fixing or positioning; the utility model provides a via hole 4 just is used for the electric connection between electric capacity pad 2 and pin pad 3. These vias are generally classified into three categories, i.e., blind vias, buried vias and through vias, if the process is considered, the blind vias are located on the top or bottom surface of the printed circuit board and have a certain depth for connecting the surface layer circuit and the underlying inner layer circuit, and the depth of the vias does not usually exceed a certain ratio (aperture). Buried via is a connection hole in an inner layer of a printed circuit board that does not extend to the surface of the circuit board. The third type is called through hole, which can be used to realize internal interconnection or as a mounting positioning hole for components through the whole circuit board.
If the filter capacitor is abandoned, the requirement of the integrity of the power supply of the chip packaging structure cannot be met; if the via hole is designed as a buried hole or a blind hole, the manufacturing cost is increased. Please continue to refer to fig. 3, the distance between the capacitor pad 2 and the via hole 4 of the present invention is d2, d2 is significantly greater than d1, and d2-r is greater than or equal to 0.1mm, so as to avoid the interference between the capacitor pad 2 and the via hole 4. The utility model discloses need not bury hole or blind hole, reduced the cost of manufacture, and guaranteed the integrality of power, in addition, the area of electric capacity pad 2 can not reduce, the paster of being convenient for.
As shown in FIG. 2, the width of the rectangular pad 6 is set to be w, the width of the horizontal segment 21 in the embodiment is set to be w1, the height of the vertical segment 222 is set to be w2, w1 is equal to or more than 2/3w, and w2 is equal to or more than 1/3w, that is, the horizontal segment 21 cannot be too narrow, the pad at the vertical segment 222 cannot be too sharp, otherwise the pad will affect the chip.
Preferably, as shown in fig. 1, the capacitor pad 2 is disposed corresponding to the pin pad 3, and since the pin pad 3 and the capacitor pad 2 are disposed on opposite sides of the substrate, fig. 1 shows the capacitor pad 2 by a dotted line, a projected area of the capacitor pad 2 on the substrate 1 is slightly larger than a projected area of the pin pad 3 on the substrate 1, and the symmetrical disposition further reduces the overall size of the chip package structure.
The inclined section 221 of the present embodiment is a straight line section, and the capacitor bonding pad is easy to manufacture, so that the board manufacturing efficiency is high.
As shown in fig. 1, a copper layer is sputtered on the inner wall surface of the via hole 4, and the capacitor pad 2 and the pin pad 3 are connected to the copper layer via signal lines 5, respectively. A copper layer is uniformly sputtered on the inner wall surface of the through hole 4, and then the pin bonding pad 3 is electrically connected with the capacitor bonding pad 2 through the signal wire 5.
As shown in fig. 3, the substrate 1 is provided with a copper ring 41 along the edge of the via 4, the copper ring 41 being connected to the copper layer. The copper ring 41 is generally disposed around the via 4, and the outer diameter in this embodiment refers to the distance from the center of the via 4 to the outer edge of the copper ring 41, i.e. a safe distance needs to be kept between the capacitor pad 2 and the copper ring 41, so that no interference can occur. The copper ring 41 is a solder area if the via 4 is used for mounting an electronic device, but in the present embodiment, the via 4 is used for electrical connection between the capacitor pad 2 and the pin pad 3, and the copper ring 41 has a function of reinforcing structural stability of the via 4.
As shown in fig. 1, the number of the pin pads 3 and the vias 4 is plural, and the plural pin pads 3 and the plural vias 4 are arranged on the substrate 1 at regular intervals. Due to the problems of multiple functions, multiple pin pads 3 and the space between the pin pads 3, all wires can not be led out on the same layer, only the signal wires 5 corresponding to the peripheral 1-2 rows of pin pads 3 can be led out from the layer where the chip is packaged (for example, the chip is placed on the top layer), and some signal wires 5 need to be led out to the bottom layer through the through holes 4. The pin pads 3 and the via holes 4 of the present embodiment are uniformly spaced, so as to implement chip packaging with high integration level.
The capacitor pads 2 are equidistant from the surrounding vias 4. Some pins connected with the pin bonding pads 3 are power pins, a capacitor bonding pad 2 is correspondingly arranged on the back of each power pin bonding pad 3, and the capacitor bonding pads 2 are used for being attached with filter capacitors so as to realize the integrity of the power supply of the chip packaging structure. The capacitor bonding pad 2 and the peripheral via holes 4 of the embodiment do not interfere with each other, so that each power supply pin can be connected with a filter capacitor, buried holes or blind holes are avoided, and the production cost is reduced.
Furthermore, the utility model also provides a chip package structure, including chip, filter capacitor and above-mentioned printed circuit board, the chip is established on pin pad 3 including pasting, and filter capacitor pastes and establishes on electric capacity pad 2. The specific structure of the printed circuit board refers to the above embodiments, and since the chip package structure adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
Preferably, the Chip Package structure is BGA (Ball Grid Array), LGA (Land Grid Array), or CSP (Chip Scale Package). The requirements of small packaging size, high integration level, low manufacturing cost and power supply integrity are met.
The above is only the preferred embodiment of the present invention, not so limiting the patent scope of the present invention, all of which are under the concept of the present invention, the equivalent transformation made by the specification or direct/indirect application in other related technical fields are included in the patent protection scope of the present invention.
Claims (9)
1. A printed circuit board, comprising:
a substrate;
the capacitor bonding pad is arranged on the substrate and comprises two horizontal sections arranged oppositely and two bent sections arranged oppositely, each bent section comprises a vertical section and two inclined sections connected with two ends of the vertical section, and the inclined sections are connected with the horizontal sections;
the pin bonding pad is arranged on one side of the substrate, which is far away from the capacitor bonding pad;
the via hole, the via hole run through in the base plate just is located the side of pin pad, the slope section orientation the via hole setting.
2. The printed circuit board of claim 1, wherein the capacitor pads are disposed in correspondence with the pin pads.
3. The printed circuit board of claim 1, wherein the angled section is a straight line section.
4. The printed circuit board of claim 1, wherein the inner wall surface of the via hole is sputtered with a copper layer, and the capacitor pad and the pin pad are connected to the copper layer through signal lines, respectively.
5. The printed circuit board of claim 4, wherein the substrate is provided with a copper ring along an edge of the via, the copper ring being connected to the copper layer.
6. The printed circuit board of any one of claims 1 to 5, wherein the number of the pin pads and the vias is plural, and the plural pin pads and the plural vias are uniformly spaced on the substrate.
7. A printed circuit board of any of claims 1-5, wherein the capacitor pads are equidistant from the surrounding vias.
8. A chip packaging structure, characterized by comprising a chip, a filter capacitor and the printed circuit board as claimed in any one of claims 1 to 7, wherein the chip is attached to the pin bonding pad, and the filter capacitor is attached to the capacitor bonding pad.
9. The chip package structure according to claim 8, wherein the chip package structure is a BGA, LGA, or CSP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021770940.6U CN212696265U (en) | 2020-08-20 | 2020-08-20 | Printed circuit board and chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021770940.6U CN212696265U (en) | 2020-08-20 | 2020-08-20 | Printed circuit board and chip package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212696265U true CN212696265U (en) | 2021-03-12 |
Family
ID=74902704
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021770940.6U Active CN212696265U (en) | 2020-08-20 | 2020-08-20 | Printed circuit board and chip package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212696265U (en) |
-
2020
- 2020-08-20 CN CN202021770940.6U patent/CN212696265U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6346743B1 (en) | Embedded capacitor assembly in a package | |
| KR101218011B1 (en) | Flip chip interconnect pad layout semiconductor package and its production method | |
| TW472331B (en) | Semiconductor integrated circuit and printed wiring substrate provided with the same | |
| TWI444120B (en) | Mainboard assembly including a package overlying a die directly attached to the mainboard,a method of fabricating a mainboard assembly,and a computing system | |
| US6418029B1 (en) | Interconnect system having vertically mounted passive components on an underside of a substrate | |
| KR100833589B1 (en) | Stack package | |
| TWI377657B (en) | Semiconductor chip package | |
| US20150022985A1 (en) | Device-embedded package substrate and semiconductor package including the same | |
| JP3368870B2 (en) | Package substrate and semiconductor device having the same | |
| TWI673845B (en) | Chip-on-film package structure | |
| US6831233B2 (en) | Chip package with degassing holes | |
| US7180182B2 (en) | Semiconductor component | |
| TW200416908A (en) | Mounting capacitors under ball grid array | |
| CN112788842A (en) | Chip power supply system, chip, PCB and computer equipment | |
| CN114420661B (en) | Integrated circuit packaging structure, packaging method, integrated circuit system and electronic equipment | |
| US10103115B2 (en) | Circuit substrate and semicondutor package structure | |
| CN212696265U (en) | Printed circuit board and chip package structure | |
| KR20220133992A (en) | Package substrate and package structure | |
| TWI362733B (en) | Optimized power delivery to high speed, high pin-count devices | |
| CN219812292U (en) | 6X 6 arranges single blind hole fan-out structure of 0.4mmBGA partial dish | |
| CN210518987U (en) | PCB structure for optimizing nuclear power distribution network impedance of BGA packaged chip | |
| US20030080418A1 (en) | Semiconductor device having power supply pads arranged between signal pads and substrate edge | |
| CN222126516U (en) | Chip packaging structure, packaging module and electronic equipment | |
| CN112492752A (en) | Chip pin extension device | |
| KR200295665Y1 (en) | Stacked Semiconductor Package |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |