CN212381187U - Power switching output circuit - Google Patents

Abstract

The utility model discloses a power switching output circuit. The power switching output circuit comprises a load signal buffer circuit, a judgment module and a power switching module; the load signal buffer circuit is used for receiving each load request signal output by the control circuit of more than or equal to 2 loads and generating an enable signal of each load according to each load request signal; the judging module is used for receiving the enabling signals of all the loads, performing operation on the enabling signals of all the loads, including AND-OR logic operation or time sequence judging operation, and outputting an effective control signal, wherein the effective control signal corresponds to the load to be switched on by a power supply; the power switching module is used for receiving the effective control signal and switching the connection between the power supply and the load according to the effective control signal. According to the scheme, the effective control signal is determined through the judging module according to the request signal, and then the power switching is realized through the power switching module according to the effective control signal, so that one power supply switching multi-path load output is realized, and the total cost of equipment is reduced.

Description

Power switching output circuit

Technical Field

The utility model belongs to the technical field of power drive circuit, in particular to power switching output circuit.

Background

The power supply output in the current market is only one load, the power supply is fixedly connected with the load, and a plurality of power supplies are required to be configured for the intermittent output of the plurality of loads, so that a power switching output circuit capable of continuous high-frequency switching is urgently required to be designed, and the free switching of one power supply to the plurality of loads is realized.

For example, the left and right horizontal sealing jaw loads of the existing filling machine require two high-frequency power supplies, and one high-frequency power supply outputs and controls power corresponding to one jaw load. And the power supply output port on the market is only one path, and two or more high-frequency power supplies are needed to be configured for intermittent output of two paths or even multiple paths of loads, so that the total cost of the equipment is high.

SUMMERY OF THE UTILITY MODEL

To address the above issues, the present invention discloses a power switching output circuit to overcome the above problems or at least partially solve the above problems.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the embodiment of the utility model discloses a power switching output circuit on the one hand, its characterized in that, power switching output circuit includes load signal buffer circuit, judgement module and power switching module;

the load signal buffer circuit is used for receiving each load request signal output by the control circuit of more than or equal to 2 loads and generating an enable signal of each load according to each load request signal;

the judging module is used for receiving the enabling signal of each load, calculating the enabling signal of each load and outputting an effective control signal, wherein the effective control signal corresponds to the load to be switched on by the power supply;

and the power switching module is used for receiving the effective control signal and switching the connection between a power supply and a load according to the effective control signal.

Optionally, each load request signal includes a switching value signal, or includes a switching value signal and an analog value signal;

the load signal buffer circuit comprises an isolation conversion circuit, which is used for realizing the isolation of the control circuit of each load and the judgment module and converting the switching value signal or the switching value signal and the analog signal into an enable signal of each load, which can be received and processed by the judgment module;

the enabling signal of each load comprises the converted switching value signal or comprises the converted switching value signal and the analog value signal.

Optionally, the judging module includes an automatic judging circuit, or a combination circuit of an active delay circuit and an automatic judging circuit;

the active delay circuit is used for delaying the switching value signals in the enabling signals of all the loads, and the number of the active delay circuits is the same as that of the loads;

and the automatic judgment circuit performs logic operation or time sequence judgment on the switching value signal in the enabling signal of each load to generate the effective control signal.

Optionally, the active delay circuit includes a first CMOS inverter, a second CMOS inverter, a third CMOS inverter, a fourth CMOS inverter, a first CMOS two-input nor gate, a fifth CMOS inverter, a first resistor, and a first capacitor, where the first CMOS inverter, the second CMOS inverter, the third CMOS inverter, the first CMOS two-input nor gate, and the fifth CMOS inverter are sequentially connected in series, the first resistor is connected in series between the second CMOS inverter and the third CMOS inverter, and the first capacitor is connected in parallel with the second CMOS inverter and the first resistor; the output end of the fourth CMOS inverter is connected to one input end of the first CMOS two-input nor gate, and the enable signal of the load is input to the input end of the first CMOS inverter and the other input end of the first CMOS two-input nor gate, respectively.

Optionally, the number of the loads is 2, and the automatic judgment circuit comprises a two-way RS trigger circuit, a two-way steady-state judgment circuit and an enable output judgment circuit;

the two-way RS trigger circuit comprises a second CMOS two-input NOR gate and a third CMOS two-input NOR gate, one input end of the second CMOS two-input NOR gate and one input end of the third CMOS two-input NOR gate respectively receive a switching value signal in an enabling signal from the load or an output signal of the active delay circuit, the other input end of the second CMOS two-input NOR gate is connected with the output end of the third CMOS two-input NOR gate, and the other input end of the third CMOS two-input NOR gate is connected with the output end of the second CMOS two-input NOR gate;

the two-way steady state judgment circuit comprises a CMOS two-input exclusive-OR gate, two input ends of the CMOS two-input exclusive-OR gate respectively receive a switching value signal in the enabling signals of the loads or an output signal of the active delay circuit, and the switching value signal in the enabling signals of the two loads or the output signal of the active delay circuit is subjected to exclusive-OR judgment and then output to the enabling output judgment circuit;

the enable output judging circuit comprises a fourth CMOS two-input NOR gate and a fifth CMOS two-input NOR gate, wherein one input end of the fourth CMOS two-input NOR gate receives an output signal of the second CMOS two-input NOR gate, and the other input end of the fourth CMOS two-input NOR gate receives an output signal of the CMOS two-input XOR gate; one input end of the fifth CMOS two-input NOR gate receives an output signal of the third CMOS two-input NOR gate, and the other input end of the fifth CMOS two-input NOR gate receives an output signal of the CMOS two-input XOR gate; and according to the output signals of the two-way steady state judgment circuit and the two-way RS trigger circuit, the fourth CMOS two-input NOR gate or the fifth CMOS two-input NOR gate outputs the effective control signal.

Optionally, the power switching module includes an IGBT control circuit and a power switching circuit, and the number of the IGBT control circuit and the number of the power switching circuit are the same as the number of the loads;

each IGBT control circuit comprises an IGBT driving module, the IGBT driving module receives the effective control signal and outputs a control signal for controlling the power switching circuit to be switched on/off according to the effective condition of the effective control signal;

each power switching circuit comprises a first IGBT power tube, a second IGBT power tube and a protection and drive circuit symmetrically arranged in front of the first IGBT power tube and the second IGBT power tube, gate poles of the first IGBT power tube and the second IGBT power tube are respectively connected with an output control interface of the IGBT control circuit, a collector electrode of the first IGBT power tube is connected with a power supply input, and a collector electrode of the second IGBT power tube is connected with a load.

Optionally, the power switching output circuit further includes a power setting switching circuit, where the power setting switching circuit is configured to receive the output signal of the active delay circuit and/or the valid control signal, receive an analog quantity signal in an enable signal of the load when the load request signal includes the analog quantity signal, determine a corresponding power setting according to the received signal, and output the corresponding power setting to the power supply.

Optionally, the power setting switching circuit includes a dial switch or a digital control analog switch integrated circuit chip.

Optionally, the power switching output circuit further includes an alarm module, where the alarm module is configured to receive an alarm signal of the power supply and an effective control signal output by the judgment module, and output the alarm signal to a corresponding load after logic operation and conversion processing.

Optionally, the alarm module includes an alarm signal switching and locking circuit and two alarm signal level conversion circuits;

the alarm signal switching and locking circuit comprises a first CMOS two-input AND gate, a second CMOS two-input AND gate, a first CMOS latch and a second CMOS latch, wherein one input end of the first CMOS two-input AND gate and one input end of the second CMOS two-input AND gate receive the effective control signal respectively, and the other input end of the first CMOS two-input AND gate and the other input end of the second CMOS two-input AND gate are connected with the alarm signal of the power supply; the CLK interfaces of the first and second CMOS latches are coupled to the first and second CMOS two-input AND gates, respectivelyThe D interfaces of the first and second CMOS latches are connected to the active control signal, respectively, the first and second CMOS latches are connected via the active control signal, respectively

The interface outputs an alarm pulse signal to the alarm signal level conversion circuit;

each alarm signal level conversion circuit comprises a triode and a relay, wherein the triode controls the on or off of the relay according to the alarm pulse signal output by the first CMOS latch or the second CMOS latch, so that the alarm signal is output to the corresponding load.

The utility model has the advantages and beneficial effects that:

the scheme can determine the effective control signal corresponding to the load communicated with the power supply through the logic or time sequence operation of the judging module according to the request signal sent by the load, and then realize the power switching through the power switching module according to the effective control signal, thereby realizing the multi-path load output of one power switching, and reducing the total cost of equipment.

The above description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented according to the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the present invention is given.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a schematic structural diagram of a power switching output circuit according to an embodiment of the present invention;

fig. 2 is a circuit diagram of a judging module according to an embodiment of the present invention;

fig. 3 is a circuit diagram of a power switching module according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a power supply setting and power supply alarm flow according to an embodiment of the present invention;

fig. 5 is a circuit diagram of an alarm module according to an embodiment of the present invention;

fig. 6 is an overall frame diagram of a power switching output circuit according to an embodiment of the present invention;

fig. 7 is a schematic diagram of the timing sequence of each signal of the active delay circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions of the present invention with reference to the specific embodiments and the accompanying drawings of the present invention. It should be apparent that the described embodiments are only some of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Example 1

Fig. 1 shows a structure of a power switching output circuit in an embodiment of the present invention, and the power switching output circuit includes a load signal buffer circuit 110, a judgment module 120, and a power switching module 130.

The load signal buffer circuit 110 is configured to receive load request signals output by 2 or more loads and generate enable signals of the loads corresponding to the loads according to the load request signals, and the load signal buffer circuit 110 includes a switching value buffer circuit, and optionally may further include an analog buffer circuit that processes a switching value signal or a switching value signal and analog signals such as a voltage value and a current value in the load request signals from the load control circuit.

The determining module 120 is configured to receive the enable signal of each load, perform an operation on the enable signal of each load, and output an effective control signal, where the effective control signal corresponds to a load to which the power supply is switched.

And the power switching module 130 is configured to switch connection between the power supply and the load according to the active control signal.

The technical scheme disclosed in the embodiment is that firstly, load request signals including analog quantity signals such as switching quantity signals, voltage or current and the like of two or more loads are converted into enabling signals of the load which can be received and processed by a power switching output circuit through a load signal buffer circuit 110, then the enabling signals of the load are transmitted to a judging module 120 to be processed, and a path of preferential high-level effective control signal is obtained through logical operation aiming at the AND or of two paths of load enabling signals or time sequence judgment aiming at multiple paths of load enabling signals; then, the power switching module 130, for example, a power switching circuit including an IGBT or an MOS power transistor, switches the power supply input to the power supply output end of the corresponding channel according to the high-level effective control signal, thereby implementing the connection of the power supply and the load corresponding to the effective control signal.

Further, in order to obtain more accurate control, a switching value signal and an analog signal are obtained from a controller of the load, such as a PLC or a single chip microcomputer, the switching value signal is a pulse signal, and the analog signal includes a voltage value, a current value, and the like required by the load.

The load request signal comprises a switching value signal or comprises the switching value signal and an analog value signal; the load signal buffer circuit comprises an isolation conversion circuit, is used for realizing the isolation of a control circuit and a judgment module of a load, and converts the switching value signal and the analog quantity signal into an enabling signal of the load, which can be received by the judgment module, wherein the enabling signal of the load comprises the converted switching value signal or comprises the converted switching value signal and the analog quantity signal.

Preferably, the isolation conversion circuit can be implemented by an isolation converter, including an analog isolation converter and a switching isolation converter, and can be implemented by an existing isolation conversion circuit product.

It should be noted that the judging module 120 is a control core of the power switching output circuit, and includes an automatic judging circuit or a combined circuit including an active delay circuit and an automatic judging circuit, and the number of the active delay circuits is the same as the number of the loads; the automatic judgment circuit performs logic operation or timing judgment on the enable signal of each load to generate the effective control signal.

The active delay circuit can realize the delayed output of the enabling signal of the load, the delay time can be selected according to practical application, and the time is 1-100 mS. The active delay circuit comprises a resistor, a capacitor and a CMOS inverter, and the purpose of adjusting the delay time can be achieved by changing the numerical values of the resistor and the capacitor.

In a preferred embodiment, the left side of fig. 2 shows an active delay circuit for performing delay processing on enable signals of two loads, and referring to an upper part circuit in fig. 2, the active delay circuit specifically includes a first CMOS inverter U1A, a second CMOS inverter U1B, a third CMOS inverter U1C, a fourth CMOS inverter U1D, a first CMOS two-input nor gate U3B and a fifth CMOS inverter U1E which are connected in series with each other, wherein a first resistor R1 is connected in series between the second CMOS inverter U1B and the third CMOS inverter U1C, a first capacitor C2 is connected in parallel with the second CMOS inverter U1B and a first resistor R1, the fourth CMOS inverter U1D is connected with one input terminal of the first CMOS two-input nor gate U3B, and enable signals of the loads are respectively input to an input terminal of the first CMOS inverter U1A and the other input terminal of the first CMOS two-input nor gate U3B.

The right side of fig. 2 shows an automatic judgment circuit of the judgment module, taking a two-way load circuit as an example, the automatic judgment circuit includes a two-way RS trigger circuit, a two-way steady state judgment circuit and an enable output judgment circuit, and can judge two-way signals, output a high level as an effective control signal to one of the two-way loads, and judge as an ineffective control signal when the two-way signals are enabled simultaneously or are low simultaneously.

The two paths of enabling switching value signals simultaneously enter a two-path RS trigger circuit and a two-path steady state judgment circuit, and the two-path RS trigger circuit has the functions of selecting a path of first-coming signals for effective judgment and triggering and outputting high level; the two-way steady state judgment circuit comprises a CMOS two-input exclusive-OR gate U5B and is used for outputting low level when the invalid condition that the two-way signal level is consistent occurs; the enabling output judging circuit consists of two CMOS two-input NOR gates U4A and U4B, and finally judges an effective control signal according to an output value (high level effective) of the two-way RS trigger circuit and an output value (high level effective) of the two-way steady state judging circuit.

With specific reference to the right side of fig. 2, the two-way RS flip-flop circuit includes a second CMOS two-input nor gate U4C and a third CMOS two-input nor gate U4D, one input terminal of the second CMOS two-input nor gate U4C and one input terminal of the third CMOS two-input nor gate U4D respectively receive an output signal from the active delay circuit, the other input terminal of the second CMOS two-input nor gate U4C is connected to the output terminal of the third CMOS two-input nor gate U4D, and the other input terminal of the third CMOS two-input nor gate U4D is connected to the output terminal of the second CMOS two-input nor gate U4C; the two-way steady state judgment circuit comprises a CMOS two-input exclusive-OR gate U5B, two input ends of the CMOS two-input exclusive-OR gate U5B are respectively connected with the output of the active delay circuit, and output signals of the active delay circuit to the enable output judgment circuit after being subjected to exclusive-OR judgment.

The enabling output judging circuit comprises a fourth CMOS two-input NOR gate U4A and a fifth CMOS two-input NOR gate U4B, wherein one input end of the fourth CMOS two-input NOR gate U4A receives an output signal of the second CMOS two-input NOR gate U4C, and the other input end of the fourth CMOS two-input NOR gate U4A receives an output signal of the CMOS two-input XOR gate U5B; one input terminal of the fifth CMOS two-input nor gate U4B receives the output signal of the third CMOS two-input nor gate U4D, and the other input terminal receives the output signal of the CMOS two-input exclusive or gate U5B.

Through the circuit, which path of the two-path signal can output high level is finally determined, and the situation that two paths output low level can be generated.

Referring to fig. 3, the power switching module includes an IGBT control circuit and a power switching circuit, and the number of the IGBT control circuit and the number of the power switching circuit are the same as the number of the loads. The input signal of the IGBT control circuit and the power switching circuit is an effective control signal (high level effective) output by the automatic judging circuit, and the power input is the power output of the high-frequency power supply.

Taking the two-way load as an example, the enabling signal of the two-way load generates an effective control signal (high-level signal) after passing through the automatic judgment circuit in the judgment module, and outputs the effective control signal to the IGBT control circuit to generate a signal for driving the IGBT to turn on/off, and then transmits the on/off signal to the power switching circuit, and finally the power switching circuit realizes the communication between the high-frequency power supply and one of the two ways of load.

The left part in fig. 3 is an IGBT control circuit, and the core component of the IGBT control circuit is an IGBT driver module, which receives an active control signal and outputs a signal capable of controlling the power switching circuit to turn on/off according to the active condition of the active control signal.

The right part in fig. 3 is a power switching circuit, which is composed of an IGBT power tube Q3/Q4, a gate-level driving resistor R5, a gate-level biasing resistor R13, a gate-level protection zener diode D5/D6, and the like. When the IGBT control circuit controls the IGBT power tube in the power switching circuit to be opened, the power input of the power supply is conducted with the corresponding power output end, and therefore the power supply is output to the corresponding load.

Specifically, the power switching circuit comprises a first IGBT power tube Q3, a second IGBT power tube Q4 and protection and drive circuits symmetrically arranged in front of the first IGBT power tube Q3 and the second IGBT power tube Q4, gate electrodes of the first IGBT power tube Q3 and the second IGBT power tube Q4 are respectively connected with an output control interface of the IGBT control circuit, a collector electrode of the first IGBT power tube Q3 is connected with a power supply input, and a collector electrode of the second IGBT power tube Q4 is connected with a load.

With continued reference to the right diagram of fig. 3, the protection and driving circuit includes a gate-level driving resistor R5/R6, oppositely disposed zener diodes D5/D6/D7/D8, and a gate-level biasing resistor R13/R14, wherein the gate-level driving resistor R5 is connected in series between the DriveOutput interface of the IGBT driving board and the gate of the first IGBT power transistor Q3, the two oppositely disposed zener diodes D5/D6 are connected in parallel with the gate-level biasing resistor R13, one end of the gate-level biasing resistor R13 and one end of the two oppositely disposed zener diodes D5/D6 are connected to the dccom interface of the IGBT driving module and the emitter connection of the first IGBT power transistor Q3, and the other end is connected to the connection of the gate-level driving resistor R5 and the gate of the first IGBT power transistor Q3. The gate-level driving resistor R6, the oppositely arranged voltage stabilizing diodes D7/D8 and the gate-level biasing resistor R14 are respectively and symmetrically arranged with the gate-level driving resistor R5, the oppositely arranged voltage stabilizing diodes D5/D6 and the gate-level biasing resistor R13.

Example 2

Referring to fig. 4, the power switching output circuit disclosed in this embodiment includes a power setting switching circuit for setting a parameter of the power supply according to the load request signal. Specifically, the load request signal includes a switching value signal and an analog value signal, the power setting switching circuit is used for receiving an output signal of the active delay circuit, and in a specific case, an effective control signal can also be used as an input of the power setting switching circuit. When the load request signal comprises an analog quantity signal, the power supply setting switching circuit can also receive the analog quantity signal output by the load signal buffer circuit, then determine corresponding power supply setting according to the received signal and output the corresponding power supply setting to the power supply.

The output signal of the active delay circuit, i.e. the delay switching value signal, is a signal that is in phase with the switching value signal, and may be an output signal obtained by delaying through part of the components in the active delay circuit, or may be a final output signal of the active delay circuit.

In specific implementation, the power supply setting switching circuit can be implemented by selecting a dial switch, which is also called a DIP switch, and is an address switch for operation control, and the binary coding principle of 0/1 is adopted. The power supply setting switching circuit can also control the analog quantity switch integrated circuit chip through other switching circuits such as digital control.

Through the power supply setting switching circuit, the dial switch or the switch in the digital control analog switch integrated circuit chip can be controlled to be switched on or switched off according to the pulse signal output by the judging module (preferably from the active time delay circuit in the judging module), and when the switch is switched on, the analog signal is connected and output to the control circuit of the power supply, so that the setting of the power supply is changed.

Example 3

The power switching output circuit of embodiment 3 further includes an alarm module, and the alarm module is configured to receive an alarm signal of the power supply and an effective control signal output by the determination module, and output the alarm signal to a corresponding load after logic operation and conversion processing.

Specifically, the input signal of the alarm module is a judgment valid control signal (valid at a high level) and a power supply alarm signal (alarm at a high level) output by an automatic judgment circuit of the judgment module. The working flow of the alarm module is shown in fig. 4. The effective control signal output by the automatic judgment circuit in the judgment module and the alarm signal output by the power supply are processed by the alarm signal switching and locking circuit and then output to corresponding loads by the alarm signal level conversion circuit.

Taking a two-way load as an example, the effective control signal is logically judged by a CMOS two-input AND gate in the alarm signal switching and locking circuit, a high level is output to a CMOS latch, the CMOS latch outputs and locks an alarm signal (high level), the alarm signal level conversion circuit controls an NPN triode to drive a relay to conduct/close according to the signal output by the CMOS latch, and finally the alarm signal is output to a control circuit of a corresponding load.

In a preferred embodiment, referring to fig. 5, the alarm module specifically includes an alarm signal switching and locking circuit and two alarm signal level converting circuits; the alarm signal switching and locking circuit comprises a first CMOS two-input AND gate U12B, a second CMOS two-input AND gate U12C, a first CMOS latch U13A and a second CMOS latch U13B, wherein one input end of the first CMOS two-input AND gate U12B and one input end of the second CMOS two-input AND gate U12C receive effective control signals respectively, and the other input end of the first CMOS two-input AND gate U12B and the other input end of the second CMOS two-input AND gate U12C are connected with a power supply alarm signal; the CLK interfaces of the first and second CMOS latches are connected to the outputs of the first and second CMOS two-input AND gates U12B and U12C, respectively, the D interfaces of the first and second CMOS latches are connected to the active control signal, respectively, the first and second CMOS latchesCMOS latch circuits are respectively connected via

The interface outputs an alarm pulse signal to the alarm signal level conversion circuit.

The alarm signal level conversion circuit comprises a triode Q1 and a relay RL1, wherein the triode controls the on or off of the relay according to the alarm pulse signal output by the first CMOS latch or the second CMOS latch, so that the alarm signal is output to a corresponding load.

Referring specifically to the right hand side view of fig. 5, the base of transistor Q1 is interfaced with the first CMOS latch output

The transistor is provided with a resistor R37, a collector of the triode Q1 is connected with a signal input end of the low-voltage power supply VCC and the relay respectively, an emitter of the triode Q1 is grounded, a resistor R41 is further arranged between the ground and the base, a diode D10 is further arranged between the low-voltage power supply VCC and the collector, and the low-voltage power supply VCC is connected with the other end of the signal input of the relay.

Fig. 6 is an overall frame diagram of a power switching output circuit of a dual-path load, which covers a plurality of circuits such as a load request signal input circuit, a load signal buffer circuit, an active delay circuit, an automatic judgment circuit, a power switching circuit, a power setting switching circuit, and an alarm module, wherein the arrow direction shows the signal flowing process.

Example 4

The embodiment discloses a power switching output method, referring to the signal processing and circulation process in fig. 6, the power switching output method includes the following steps:

110, receiving load request signals output by a control circuit of more than or equal to 2 loads by using an input end of a load signal buffer circuit, wherein the load request signals comprise switching value signals or switching value signals and analog quantity signals, converting the load request signals into enabling signals of each load capable of being processed by a judgment module, and outputting the enabling signals of each load to the judgment module;

step 120, receiving the switching value signal in the enable signal of each load by using the input end of the judging module, and calculating each switching value signal so as to judge a load which can be switched and connected to the power supply, and outputting an effective control signal to the input end of the power switching module through the output end of the judging module, wherein the effective control signal corresponds to the load to be switched and connected by the power supply;

and step 130, receiving the effective control signal by using the input end of the power switching module, and switching and connecting the power supply to a load corresponding to the effective control signal according to the effective control signal.

In the power switching output method disclosed in embodiment 4, first, load signals such as switching value signals of two or more loads are converted into enabling signals of a load that can be received and processed by a determination module through a load signal buffer circuit, then the enabling signals of the load are transmitted to the determination module to be processed, and a preferential high-level effective control signal is obtained through logical operation of and or negation for two paths of load signals or time sequence determination for multiple paths of load signals; and then, the power supply input is switched to the corresponding output end according to the high-level effective control signal through a power switching module such as a power switching circuit comprising an IGBT (insulated gate bipolar transistor) or MOS (metal oxide semiconductor) power tube, so that the power supply is switched on with the load corresponding to the effective control signal.

Further, the judging module comprises an active delay circuit and an automatic judging circuit, and the power switching output method further comprises:

and the switching value signals are transmitted to an active delay circuit to obtain switching value delay signals for prolonging different time periods, one switching value delay signal is selected and input to an automatic judgment circuit, and the automatic judgment circuit outputs effective control signals after time sequence judgment or AND-OR logic operation.

Preferably, the load request signal further includes an analog signal, the enable signal of the load includes a converted analog signal, and the power switching output method further includes:

the input end of the power supply setting switching circuit receives the analog quantity signal in the switching value delay signal of the active delay circuit and the enabling signal of the load, determines corresponding power supply setting according to the received signal and outputs the corresponding power supply setting to the power supply.

Preferably, the power supply further generates an alarm signal when the power supply fails, and the power switching output method further includes:

the input end of the alarm module receives the alarm signal and the effective control signal, and the alarm module carries out logic operation and conversion processing on the input signal and outputs the alarm signal to a load corresponding to the effective control signal.

Fig. 7 shows a schematic diagram of the timing sequence of each path of signals of the active delay circuit, which records the delay condition of the switching value signals in the power switching output circuit under the condition of two paths of loads.

The following determination results can be obtained by performing logical and nor arithmetic operation by the automatic determination circuit based on the switching value signals output by the respective loads:

the above description is only for the embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, extension, etc. made within the spirit and principle of the present invention are all included in the protection scope of the present invention.

Claims (10)

1. A power switching output circuit is characterized by comprising a load signal buffer circuit, a judgment module and a power switching module;

the load signal buffer circuit is used for receiving each load request signal output by the control circuit of more than or equal to 2 loads and generating an enable signal of each load according to each load request signal;

the judging module is used for receiving the enabling signal of each load, performing operation on the enabling signal of each load, including AND-OR logic operation or time sequence judging operation, and outputting an effective control signal, wherein the effective control signal corresponds to the load to be switched on by a power supply;

and the power switching module is used for receiving the effective control signal and switching the connection between a power supply and a load according to the effective control signal.

2. The power switching output circuit according to claim 1, wherein each of the load request signals comprises a switching value signal, or comprises a switching value signal and an analog value signal;

the load signal buffer circuit comprises an isolation conversion circuit, which is used for realizing the isolation of the control circuit of each load and the judgment module and converting the switching value signal or the switching value signal and the analog signal into an enable signal of each load, which can be received and processed by the judgment module;

the enabling signal of each load comprises the converted switching value signal or comprises the converted switching value signal and the analog value signal.

3. The power switching output circuit according to claim 2, wherein the judging module comprises an automatic judging circuit or a combination circuit of an active delay circuit and an automatic judging circuit;

the active delay circuit is used for delaying the switching value signals in the enabling signals of all the loads, and the number of the active delay circuits is the same as that of the loads;

and the automatic judgment circuit performs logic operation or time sequence judgment on the switching value signal in the enabling signal of each load to generate the effective control signal.

4. The power switching output circuit of claim 3, wherein the active delay circuit comprises a first CMOS inverter, a second CMOS inverter, a third CMOS inverter, a fourth CMOS inverter, a first CMOS two-input NOR gate, and a fifth CMOS inverter connected in series in this order, a first resistor connected in series between the second CMOS inverter and the third CMOS inverter, and a first capacitor connected in parallel with the second CMOS inverter and the first resistor; the output end of the fourth CMOS inverter is connected to one input end of the first CMOS two-input nor gate, and the enable signal of the load is input to the input end of the first CMOS inverter and the other input end of the first CMOS two-input nor gate, respectively.

5. The power switching output circuit according to claim 3 or 4, wherein the number of the loads is 2, and the automatic judgment circuit comprises a two-way RS trigger circuit, a two-way steady-state judgment circuit and an enable output judgment circuit;

the two-way RS trigger circuit comprises a second CMOS two-input NOR gate and a third CMOS two-input NOR gate, one input end of the second CMOS two-input NOR gate and one input end of the third CMOS two-input NOR gate respectively receive a switching value signal in an enabling signal from the load or an output signal of the active delay circuit, the other input end of the second CMOS two-input NOR gate is connected with the output end of the third CMOS two-input NOR gate, and the other input end of the third CMOS two-input NOR gate is connected with the output end of the second CMOS two-input NOR gate;

the two-way steady state judgment circuit comprises a CMOS two-input exclusive-OR gate, two input ends of the CMOS two-input exclusive-OR gate respectively receive a switching value signal in the enabling signals of the loads or an output signal of the active delay circuit, and the switching value signal in the enabling signals of the two loads or the output signal of the active delay circuit is subjected to exclusive-OR judgment and then output to the enabling output judgment circuit;

the enable output judging circuit comprises a fourth CMOS two-input NOR gate and a fifth CMOS two-input NOR gate, wherein one input end of the fourth CMOS two-input NOR gate receives an output signal of the second CMOS two-input NOR gate, and the other input end of the fourth CMOS two-input NOR gate receives an output signal of the CMOS two-input XOR gate; one input end of the fifth CMOS two-input NOR gate receives an output signal of the third CMOS two-input NOR gate, and the other input end of the fifth CMOS two-input NOR gate receives an output signal of the CMOS two-input XOR gate; and according to the output signals of the two-way steady state judgment circuit and the two-way RS trigger circuit, the fourth CMOS two-input NOR gate or the fifth CMOS two-input NOR gate outputs the effective control signal.

6. The power switching output circuit of claim 1, wherein the power switching module comprises an IGBT control circuit and a power switching circuit, and the number of the IGBT control circuit and the power switching circuit is the same as the number of the loads;

each IGBT control circuit comprises an IGBT driving module, the IGBT driving module receives the effective control signal and outputs a control signal for controlling the power switching circuit to be switched on/off according to the effective condition of the effective control signal;

each power switching circuit comprises a first IGBT power tube, a second IGBT power tube and a protection and drive circuit symmetrically arranged in front of the first IGBT power tube and the second IGBT power tube, gate poles of the first IGBT power tube and the second IGBT power tube are respectively connected with an output control interface of the IGBT control circuit, a collector electrode of the first IGBT power tube is connected with a power supply input, and a collector electrode of the second IGBT power tube is connected with a load.

7. The power switching output circuit according to claim 3 or 4, further comprising a power setting switching circuit for receiving the output signal of the active delay circuit and/or the active control signal, receiving an analog signal in the enable signal of the load if the load request signal comprises an analog signal, and determining a corresponding power setting according to the received signal and outputting the corresponding power setting to the power supply.

8. The power-switching output circuit of claim 7, wherein the power setting switching circuit comprises a dial switch or a digitally controlled analog switch integrated circuit chip.

9. The power switching output circuit of claim 1, further comprising an alarm module, wherein the alarm module is configured to receive an alarm signal of the power supply and an effective control signal output by the judgment module, and output the alarm signal to a corresponding load after logic operation and conversion processing.

10. The power-switching output circuit of claim 9, wherein the alarm module comprises an alarm signal switching and locking circuit and two alarm signal level shifting circuits;

the alarm signal switching and locking circuit comprises a first CMOS two-input AND gate, a second CMOS two-input AND gate, a first CMOS latch and a second CMOS latch, wherein one input end of the first CMOS two-input AND gate and one input end of the second CMOS two-input AND gate receive the effective control signal respectively, and the other input end of the first CMOS two-input AND gate and the other input end of the second CMOS two-input AND gate are connected with the alarm signal of the power supply; the CLK interfaces of the first CMOS latch and the second CMOS latch are respectively connected with the outputs of the first CMOS two-input AND gate and the second CMOS two-input AND gate, the D interfaces of the first CMOS latch and the second CMOS latch are respectively connected with the effective control signal, and the first CMOS latch and the second CMOS latch are respectively connected with the effective control signal through

The interface outputs an alarm pulse signal to the alarm signal level conversion circuit;

each alarm signal level conversion circuit comprises a triode and a relay, wherein the triode controls the on or off of the relay according to the alarm pulse signal output by the first CMOS latch or the second CMOS latch, so that the alarm signal is output to the corresponding load.

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