CN212322080U - Logging parameter simulator - Google Patents
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- CN212322080U CN212322080U CN202020301635.6U CN202020301635U CN212322080U CN 212322080 U CN212322080 U CN 212322080U CN 202020301635 U CN202020301635 U CN 202020301635U CN 212322080 U CN212322080 U CN 212322080U
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Abstract
Logging parameter simulator belongs to simulator technical field, especially relates to a logging parameter simulator. The utility model provides a logging parameter simulator. The utility model comprises a controller, and is characterized in that the signal output port of the controller is respectively connected with a 4-20mA output part, a 0-5V output part, a frequency output part and a counting output part.
Description
Technical Field
The utility model belongs to the technical field of the simulator, especially, relate to a logging parameter simulator.
Background
The logging technology is a well drilling field service, the main task of logging is to extract first-hand reliable various data information for oil and gas exploration and development in real time, the logging technology takes three technologies of communication network, sensing instrument and application of computer as a support column, and is a high and new technology geometry integrating multiple sciences and multiple technologies, and the logging technology has obvious information technical characteristics, so that the logging technology can obtain a large amount of parameters and data information of drilling, geology and the like on a construction site, and transmitted information has the characteristics of timeliness, diversity and rapid explanation and evaluation, so the logging technology becomes the most basic and necessary technology in oil and gas exploration and development industries.
The comprehensive logging instrument collects and analyzes logging data and completes the logging data by means of mutual cooperation of sensors, data collecting, transmitting and processing units and computer technologies. At present, the data acquisition, transmission and processing unit is debugged by connecting the entity sensor when acquiring data. The comprehensive logging instrument has large measurement data volume and various signals needing to be collected, the performance of the comprehensive logging instrument is tested by using the method, more than 20 physical sensors are required to be connected for testing, the efficiency is seriously influenced, and the method is not intelligent enough. Therefore, the demand of a parameter simulator which issues various analog quantity, frequency quantity and counting quantity is greatly increased.
Disclosure of Invention
The utility model discloses to above-mentioned problem, provide a logging parameter simulation ware.
In order to achieve the above object, the present invention adopts the following technical solution, and the present invention includes a controller, wherein a signal output port of the controller is respectively connected to the 4-20mA output part, the 0-5V output part, the frequency output part, and the count output part.
As a preferred scheme, the display signal output port of controller links to each other with display circuit, and the alarm signal output port of controller links to each other with alarm circuit, and the signal input port of controller links to each other with key input part.
As another preferred scheme, the power port of controller links to each other with the output port of constant voltage power supply, and the input port of constant voltage power supply links to each other with the output port of charge management part, and charge management part links to each other with lithium cell, USB mouth respectively.
As a preferable scheme, the controller of the present invention adopts an STMCU _ LQFP64 chip U5, wherein a pin 5 of U5 is connected to one end of a crystal oscillator X3, the other end of X3 is connected to a pin 6 of U5, a pin 1 of U5 is connected to a VBAT/VLCD terminal, a VDD terminal, and one end of a capacitor C29, and the other end of C29 is grounded;
the pin 13 of U5 is connected with AVDD terminal, one end of inductance L1, the other end of L1 is connected with VDD terminal, 32 pin of U5, 64 pin of U5, 48 pin of U5 and 19 pin of U5, pin 18 of U5 is grounded, pin 47 of U5 is grounded through capacitor C22, pin 63 of U5 is grounded, pin 31 of U5 is grounded through capacitor C25, pin 12 of U5 is grounded, pin 60 of U5 is grounded through resistor R55, pin 7 of U5 is connected with one end of resistor R54, one end of switch S2 and one end of capacitor C14, the other end of R54 is connected with VDD terminal, and the other ends of S2 and C14 are grounded.
As another preferred scheme, the charging management part of the present invention adopts a bq24195 chip U9, wherein pin 1 of U9 is connected to one end of a capacitor C39, one end of a capacitor C38, a VBUS end, and pin 24 of U9, and the other ends of C39 and C38 are grounded;
the pin 2 of the U9 is connected with the pin 3 of the U9 through a CB 2;
the 4 pins of the U9 are connected with the cathode of the LED1 through a resistor R50, and the anode of the LED1 is connected with the VREG end;
the pin 5 of U9 is connected with the VCC3.3 end through a resistor R48;
the pin 6 of the U9 is connected with the VCC3.3 end through a resistor R49;
the 8 feet of U9 are connected with one end of a resistor R52 and the collector of an NPN triode Q7 respectively, the other end of R52 is connected with the VSYS end, the base of Q7 is connected with one end of a resistor R51 and one end of a resistor R62 respectively, the other end of R51 is connected with the VBUS _ IN end, and the other end of R62 is connected with the collector of Q7 and the ground wire respectively;
the pin 10 of U9 is grounded through a resistor R59;
the pin 11 of the U9 is respectively connected with the pin 12 of the U9, one end of a resistor R53, one end of a resistor R60 and one end of a resistor R61, the other end of the R53 is connected with a VREG end, and the other end of the R60 and the other end of the R61 are grounded;
a pin 13 of the U9 is respectively connected with a pin 14 of the U9, one end of a capacitor C44, one end of a capacitor C43 and a VBAT end, and the other end of the C44 and the other end of the C43 are grounded;
the pin 15 of U9 is respectively connected with the pin 16 of U9, one end of an inductor L6, one end of a capacitor C42, one end of a capacitor C40, one end of a capacitor C41 and a VSYS end, the other end of C42, the other end of C40 and the other end of C41 are grounded, the other end of L6 is respectively connected with one end of the capacitor C37, the pin 19 of U9 and the pin 20 of U9, and the other end of C37 is connected with the pin 21 of U9;
pins 17 and 18 of U9 are grounded;
a pin 22 of the U9 is respectively connected with one end of a capacitor C35 and the VREG end, and the other end of the capacitor C35 is grounded;
the pin 23 of the U9 is connected to one end of a capacitor C36, one end of a capacitor C34, one end of a capacitor C33, the end of VBST5V1 and one end of a resistor R45, the other end of the C36, the other end of the C34 and the other end of the C33 are grounded, the other end of the R45 is connected to one end of a resistor R46 and the end of lowbat, and the other end of the R46 is grounded.
As another preferred scheme, the regulated power supply of the utility model adopts RT9193-33GB chip U2, pin 1 of U2 links to each other with VSYS end, electric capacity C9 one end, resistance R1 one end respectively, the other end of C9 is ground connection, the R1 other end links to each other with pin 3 of U2, switch SW1 respectively, pin 2 of U2 is ground connection, 4 of U2's pin passes through electric capacity C10 and links to each other with ground wire, electric capacity C11 one end respectively, the C11 other end links to each other with VCC3.3 end, 5 of U2, inductance L3 one end respectively, another termination VDD of L3.
As another preferred scheme, the key input portion of the present invention includes SW-PB4 switches S1, S3, S4, S5, wherein pins 1 and 4 of S1 are respectively connected to the BTN1 terminal and one end of resistor R2, the other end of R2 is connected to VCC3.3 terminal, and pins 2 and 3 of S1 are grounded; pins 1 and 4 of the S3 are respectively connected with a BTN2 end and one end of a resistor R3, the other end of the R3 is connected with a VCC3.3 end, and pins 2 and 3 of the S3 are grounded; pins 1 and 4 of the S4 are respectively connected with a BTN3 end and one end of a resistor R4, the other end of the R4 is connected with a VCC3.3 end, and pins 2 and 3 of the S4 are grounded; pins 1 and 4 of the S5 are respectively connected with a BTN4 end and one end of a resistor R5, the other end of the R5 is connected with a VCC3.3 end, and pins 2 and 3 of the S1 are grounded.
As another preferred scheme, the 4-20mA output portion of the present invention adopts DAC7311IDCKR chip U3, the 0-5V output portion adopts LM358 chip U7, pin 2 of U3 is connected to PA5 end and resistor R11 end through resistor R15, pin 3 of U3 is connected to PA7 end through resistor R17, pin 1 of U3 is connected to PA4 end through resistor R19, pin 4 of U3 is connected to REF3 end, capacitor C16 end, resistor R10 end, capacitor C12 end, pin 1 of TL431 chip Q1, resistor R8 end, and resistor R7 end;
the other end of the C16 is grounded, a pin 6 of the U3 is respectively connected with the other end of the R11 and a pin 4 of the BL1551 chip U4, a pin 5 of the U4 is respectively connected with the REF3 end and one end of the capacitor C17, the other end of the C17 is grounded, and the pin 6 of the U4 is connected with the PA6 end through a resistor R18;
the pin 2 of the U4 is grounded, the pin 3 of the U4 is respectively connected with one end of a resistor R12, one end of a resistor R20 and the pin 3 of an OPA365 AIDBRR chip U6 through resistors R13 and R14 in sequence, and the other end of the R12 is connected with the other end of the R10;
the other end of the C12 is respectively connected with a pin 2 of the U6, a ground wire, a pin 3 of the Q1 and one end of a resistor R9, and the other end of the resistor R9 is respectively connected with a pin 2 of the Q1 and the other end of the resistor R8;
the other end of R7 is respectively connected with an NPN triode Q2 collector, one end of an inductor L4 and one end of a capacitor C13, the other end of L4 is respectively connected with a diode D1 cathode and one end of a TVS tube D5, the other end of D5 is connected with one end of the inductor L5, and the other end of L5 is respectively connected with the other end of C13, one end of a resistor R21 and the other end of R20; the other end of R21 is respectively connected with the 4 pin of U6, one end of a capacitor C15 and one end of a resistor R16, and the other end of C15 is respectively connected with the 5 pin of U6 and the REF3 end; the other end of R16 is connected with the emitter of Q2;
As another preferred scheme, the frequency output portion and the count output portion of the present invention adopt a 74LVCH2T45DC chip U8, pin 1 of U8 is connected to VCC3.3 terminal, one end of capacitor C21, one end of resistor R30, the other end of C21 is grounded, the other end of R30 is connected to DO _ EN terminal, and pin 5 of U8, pin 2 of U8 is connected to DO _ a terminal through resistor R31, pin 3 of U8 is connected to DO _ B terminal through resistor R32, pin 8 of U8 is connected to VCC5 terminal, one end of capacitor C26, and the other end of C26 is grounded;
a pin 7 of the U8 is respectively connected with one end of a resistor R29 and the base electrode of an NPN triode Q3 through a resistor R28, the other end of the R29 is respectively connected with the ground wire, the emitter of the Q3 and the anode of a PESD24VS1UB diode D7, the collector of the Q3 is respectively connected with one end of a resistor R27 and the cathode of a diode D7, and the other end of the R27 is respectively connected with a DEXT end and the cathode of a diode D2;
the pin 6 of the U8 is connected with one end of a resistor R35 and the base of an NPN triode Q4 through a resistor R34, the other end of the R35 is connected with the ground wire, the emitter of the Q4 and the anode of a PESD24VS1UB diode D8, the collector of the Q4 is connected with one end of a resistor R33 and the cathode of the D8, and the other end of the R33 is connected with a DEXT end.
As another preferred scheme, the utility model discloses still include SGM41000 chip U10, U10's 1 foot links to each other with resistance R63 one end, electric capacity C46 one end respectively, and R63 another termination VBAT holds, and U10's 2, 3, 7 feet ground, and U10's 4, 5 feet ground, and U10's 6 feet are through electric capacity C45 ground connection, and C46 other end ground connection.
As another preferred scheme, the alarm circuit of the utility model includes buzzer BZ1, BZ2, the positive pole of BZ1 links to each other with VCC3.3 end, the positive pole of BZ2, diode D10 negative pole respectively, the negative pole of BZ1 links to each other with the positive pole of D10, the negative pole of BZ1, the negative pole of BZ2, SS8050 triode Q10 collecting electrode respectively, the base of Q10 links to each other with resistance R74 one end, resistance R75 one end respectively, the other end of R74 connects to the BEEP end, the other end of R75 links to each other with Q10 projecting pole, ground wire respectively.
The utility model has the advantages of.
The utility model has 4-20mA output part and 0-5V output part as analog output, and has frequency output and counting output; convenient to use, it is efficient.
Drawings
The present invention will be further described with reference to the accompanying drawings and the following detailed description. The scope of protection of the present invention is not limited to the following description.
Fig. 1 is a schematic block circuit diagram of the present invention.
Fig. 2 is a circuit schematic diagram of the 4-20mA output part and the 0-5V output part of the present invention.
Fig. 3 is a schematic circuit diagram of the frequency output unit and the count output unit of the present invention.
Fig. 4 is a connection relationship diagram of each part of the present invention.
Fig. 5 is a schematic diagram of the voltage-stabilized power supply circuit of the present invention.
Fig. 6 is a schematic diagram of a controller circuit according to the present invention.
Fig. 7 is a schematic diagram of the display circuit and the key input portion of the present invention.
Fig. 8 and 9 are schematic circuit diagrams of the charging management part of the present invention.
Fig. 10 is a wiring diagram of the LCD of the present invention.
Fig. 11 is a schematic diagram of the alarm circuit of the present invention.
Fig. 12 is a schematic diagram of a memory circuit according to the present invention.
Fig. 13 is a simplified schematic diagram of the voltage/current converter of the present invention.
Detailed Description
As shown in the figure, the utility model comprises a controller, the signal output port of which is respectively connected with a 4-20mA output part, a 0-5V output part, a frequency output part and a counting output part.
The display signal output port of the controller is connected with the display circuit, the alarm signal output port of the controller is connected with the alarm circuit, and the signal input port of the controller is connected with the key input part. The display circuit is connected with the display equipment, and the display equipment can be used for displaying the current analog quantity, the voltage analog quantity, the frequency quantity and the counting quantity.
The power supply port of the controller is connected with the output port of the stabilized voltage power supply, the input port of the stabilized voltage power supply is connected with the output port of the charging management part, and the charging management part is respectively connected with the lithium battery and the USB port.
The controller adopts an STMCU _ LQFP64 chip U5, a pin 5 of U5 is connected with one end of a crystal oscillator X3, the other end of the X3 is connected with a pin 6 of U5, a pin 1 of U5 is respectively connected with a VBAT/VLCD end, a VDD end and one end of a capacitor C29, and the other end of the C29 is grounded;
the pin 13 of U5 is connected with AVDD terminal, one end of inductance L1, the other end of L1 is connected with VDD terminal, 32 pin of U5, 64 pin of U5, 48 pin of U5 and 19 pin of U5, pin 18 of U5 is grounded, pin 47 of U5 is grounded through capacitor C22, pin 63 of U5 is grounded, pin 31 of U5 is grounded through capacitor C25, pin 12 of U5 is grounded, pin 60 of U5 is grounded through resistor R55, pin 7 of U5 is connected with one end of resistor R54, one end of switch S2 and one end of capacitor C14, the other end of R54 is connected with VDD terminal, and the other ends of S2 and C14 are grounded.
And the 8MHz crystal oscillator X3 is used for a system main clock after being processed by a frequency multiplier circuit in the MCU to 72 MHz.
The utility model discloses a RC RESETs, when the system just electrifies, charges to electric capacity C14 through resistance R54, and the RESET pin is the low level, and the STM is in the RESET state. When the charging is completed, the RESET pin is restored to a high level, and the system works normally.
The PWM function frequency quantity and counting quantity output of the STMCU _ LQFP64 chip timer provides original signals, and finally the frequency quantity and counting quantity of the specified voltage value are obtained through level conversion.
The 12-bit DAC function built in the STMCU _ LQFP64 chip provides DAC signals for 4-20mA analog quantity output and 0-5V analog quantity output, and corresponding current values and voltage values are obtained finally through conversion of the transmitter.
The utility model discloses STMCU _ LQFP64 chip uses hardware I2C and charge management chip communication, realizes the state monitoring function of lithium cell charge-discharge in-process.
The utility model discloses STMCU _ LQFP64 chip uses hardware SPI communication, shows signal output information through the OLED screen display.
The utility model discloses STMCU _ LQFP64 chip realizes that mode switches, output parameter set for through ordinary IO mouth button.
The STMCU _ LQFP64 chip is a control chip with timer hardware resources supporting PWM output and a DA converter, and can have the output functions of analog quantity, frequency quantity and counting quantity.
The charging management part adopts a bq24195 chip U9, a pin 1 of U9 is respectively connected with one end of a capacitor C39, one end of a capacitor C38, a VBUS end and a pin 24 of U9, and the other ends of C39 and C38 are grounded;
the pin 2 of the U9 is connected with the pin 3 of the U9 through CB2 (which can be a 0 ohm resistor);
the 4 pins of the U9 are connected with the cathode of the LED1 through a resistor R50, and the anode of the LED1 is connected with the VREG end;
the pin 5 of U9 is connected with the VCC3.3 end through a resistor R48;
the pin 6 of the U9 is connected with the VCC3.3 end through a resistor R49;
the 8 feet of U9 are connected with one end of a resistor R52 and the collector of an NPN triode Q7 respectively, the other end of R52 is connected with the VSYS end, the base of Q7 is connected with one end of a resistor R51 and one end of a resistor R62 respectively, the other end of R51 is connected with the VBUS _ IN end, and the other end of R62 is connected with the collector of Q7 and the ground wire respectively;
the pin 10 of U9 is grounded through a resistor R59;
the pin 11 of the U9 is respectively connected with the pin 12 of the U9, one end of a resistor R53, one end of a resistor R60 and one end of a resistor R61, the other end of the R53 is connected with a VREG end, and the other end of the R60 and the other end of the R61 are grounded;
a pin 13 of the U9 is respectively connected with a pin 14 of the U9, one end of a capacitor C44, one end of a capacitor C43 and a VBAT end, and the other end of the C44 and the other end of the C43 are grounded;
the pin 15 of U9 is respectively connected with the pin 16 of U9, one end of an inductor L6, one end of a capacitor C42, one end of a capacitor C40, one end of a capacitor C41 and a VSYS end, the other end of C42, the other end of C40 and the other end of C41 are grounded, the other end of L6 is respectively connected with one end of the capacitor C37, the pin 19 of U9 and the pin 20 of U9, and the other end of C37 is connected with the pin 21 of U9;
pins 17 and 18 of U9 are grounded;
a pin 22 of the U9 is respectively connected with one end of a capacitor C35 and the VREG end, and the other end of the capacitor C35 is grounded;
the pin 23 of the U9 is connected to one end of a capacitor C36, one end of a capacitor C34, one end of a capacitor C33, the end of VBST5V1 and one end of a resistor R45, the other end of the C36, the other end of the C34 and the other end of the C33 are grounded, the other end of the R45 is connected to one end of a resistor R46 and the end of lowbat, and the other end of the R46 is grounded.
The voltage used in the hardware circuit is 5V and 3.3V, and the system input power supply is a lithium battery with 3.7-4.2V.
The 5V power output circuit is the battery voltage obtained through the charge management chip BQ24195 in boost mode. The power inductor L6, the capacitors C33, C34 and C36 are all used for filtering, and the ripple of the power supply is reduced.
The regulated power supply adopts an RT9193-33GB chip U2, a pin 1 of U2 is respectively connected with a VSYS end, one end of a capacitor C9 and one end of a resistor R1, the other end of C9 is grounded, the other end of R1 is respectively connected with a pin 3 of U2 and a switch SW1, a pin 2 of U2 is grounded, a pin 4 of U2 is respectively connected with a ground wire and one end of a capacitor C11 through the capacitor C10, the other end of C11 is respectively connected with a VCC3.3 end, a pin 5 of U2 and one end of an inductor L3, and the other end of L3 is connected with VDD.
The 3.3V voltage output circuit obtains 3.3V voltage by the battery voltage through a low-voltage difference linear voltage stabilization chip RT9193-33GB, and the maximum output current is 300 mA.
The key input part comprises SW-PB4 switches S1, S3, S4 and S5, wherein pins 1 and 4 of S1 are respectively connected with a BTN1 end and one end of a resistor R2, the other end of R2 is connected with a VCC3.3 end, and pins 2 and 3 of S1 are grounded;
The keys may be used to set analog current mode, analog voltage mode, frequency mode, count mode and output parameters. One end of the key is connected to the normal IO of the controller and the other end is connected to ground. When the key is not pressed down, the high level is pulled through an external pull-up resistor, when the key is pressed down, the controller reads the low level through IO, and the high level is recovered after the low level is released.
JTAG is used to transmit debug information. The upper computer carries out debugging programs, downloading programs, registers in the control chip, memories, related peripherals and the like through the interface.
The SWD can complete debugging by adopting 4 lines, and main signal lines comprise SWDIO and SWCLK. The utility model discloses a4 SWD debugging interfaces. The key and SWD debug interface circuit design is shown in fig. 7.
The 4-20mA output part adopts a DAC7311IDCKR chip U3, the 0-5V output part adopts an LM358 chip U7, a pin 2 of U3 is respectively connected with a PA5 end and one end of a resistor R11 through a resistor R15, a pin 3 of U3 is connected with the PA7 end through a resistor R17, a pin 1 of U3 is connected with the PA4 end through a resistor R19, a pin 4 of U3 is respectively connected with a REF3 end, one end of a capacitor C16, one end of a resistor R10, one end of a capacitor C12, one pin 1 of a TL431 chip Q1, one end of a resistor R8 and one end of a resistor R7;
the other end of the C16 is grounded, a pin 6 of the U3 is respectively connected with the other end of the R11 and a pin 4 of the BL1551 chip U4, a pin 5 of the U4 is respectively connected with the REF3 end and one end of the capacitor C17, the other end of the C17 is grounded, and the pin 6 of the U4 is connected with the PA6 end through a resistor R18;
the pin 2 of the U4 is grounded, the pin 3 of the U4 is respectively connected with one end of a resistor R12, one end of a resistor R20 and the pin 3 of an OPA365 AIDBRR chip U6 through resistors R13 and R14 in sequence, and the other end of the R12 is connected with the other end of the R10;
the other end of the C12 is respectively connected with a pin 2 of the U6, a ground wire, a pin 3 of the Q1 and one end of a resistor R9, and the other end of the resistor R9 is respectively connected with a pin 2 of the Q1 and the other end of the resistor R8;
the other end of R7 is respectively connected with an NPN triode Q2 collector, one end of an inductor L4 and one end of a capacitor C13, the other end of L4 is respectively connected with a diode D1 cathode and one end of a TVS tube D5, the other end of D5 is connected with one end of the inductor L5, and the other end of L5 is respectively connected with the other end of C13, one end of a resistor R21 and the other end of R20; the other end of R21 is respectively connected with the 4 pin of U6, one end of a capacitor C15 and one end of a resistor R16, and the other end of C15 is respectively connected with the 5 pin of U6 and the REF3 end; the other end of R16 is connected with the emitter of Q2;
The voltage range of the DAC analog signal output by the microcontroller is only 0-3.3V limited by the power supply input voltage of the microcontroller, and the DAC signal needs to be subjected to voltage amplification for realizing the output of 0-5V at the interface end. Meanwhile, in order to improve the driving capability of analog output, a voltage follower is added at the rear stage, so that the output interface has enough load carrying capability. The utility model discloses a structure of syntropy proportional amplifier + follower.
The working principle and the design steps are as follows:
the output voltage transfer function is:
selecting a suitable VR1/R22 ratio:
vout is calculated from the DAC zero scale voltage (0V), gain ratio (VR 1/R22).
Vout is calculated from the DAC full scale voltage (here 3V), the gain ratio (VR 1/R22).
The 4-20mA signaling standard, first appeared in the 1950 s, was an analog signaling standard adopted by the International Electrotechnical Commission (IEC) process control system and is commonly used for signaling and electronic control in an industrial environment. China also adopts the international standard signal system, the instrument transmission signal adopts 4-20mA, and the receiving signal adopts 1-5V, namely, a signal system of current transmission and voltage receiving is adopted. Because of adopting current signal transmission, have advantages such as difficult quilt disturbs, safe and reliable, should make it become the signal transmission mode of industry common use.
The 4-20mA interface circuit designed by the utility model is composed of a voltage stabilizing circuit, a voltage/current conversion circuit and an interface protection circuit as shown in figure 2.
A simplified schematic diagram of a voltage/current converter is shown in fig. 13 for a loop powered or 2 wire 4-20mA transmitter. The transmitter has only two external input terminals. The transmitter communicates with the host by precisely controlling the magnitude of its return current, thereby communicating with the host.
The working principle and the design steps are as follows:
the output current transfer function is:
a larger R3/R4 ratio was selected:
r2 is calculated from the zero scale current (4mA), the regulator voltage and the gain ratio (R3/R4).
R1 was calculated from the full-scale DAC voltage and the 16mA current range to set the full-scale current.
The zero scale current is calculated from the selected resistor value.
The full-scale current is calculated from the selected resistor value.
The voltage stabilizing circuit adopts a TL431 programmable parallel voltage stabilizing chip, the precision specification is 0.5 percent, the cost is low, and the performance is good. The regulator output will remain relatively consistent even if the load changes.
Since instrumentation using the 4-20mA signal standard is often used in industrial environments that can be very dangerous for sensitive electronic components, protection circuitry is added at the interface end to prevent electrical overstress or poor performance environmental hazards that may result from miswiring. The utility model discloses utilize diode D1's one way conduction, TVS pipe D5's reverse breakdown characteristic prevents the system trouble because of wiring mistake, outside signal interference lead to.
The frequency quantity output part and the counting quantity output part adopt a 74LVCH2T45DC chip U8, a pin 1 of U8 is respectively connected with a VCC3.3 end, one end of a capacitor C21 and one end of a resistor R30, the other end of C21 is grounded, the other end of R30 is respectively connected with a DO _ EN end and a pin 5 of U8, a pin 2 of U8 is connected with a DO _ A end through a resistor R31, a pin 3 of U8 is connected with a DO _ B end through a resistor R32, a pin 8 of U8 is respectively connected with a VCC5 end and one end of a capacitor C26, and the other end of C26 is grounded;
a pin 7 of the U8 is respectively connected with one end of a resistor R29 and the base electrode of an NPN triode Q3 through a resistor R28, the other end of the R29 is respectively connected with the ground wire, the emitter of the Q3 and the anode of a PESD24VS1UB diode D7, the collector of the Q3 is respectively connected with one end of a resistor R27 and the cathode of a diode D7, and the other end of the R27 is respectively connected with a DEXT end and the cathode of a diode D2;
the pin 6 of the U8 is connected with one end of a resistor R35 and the base of an NPN triode Q4 through a resistor R34, the other end of the R35 is connected with the ground wire, the emitter of the Q4 and the anode of a PESD24VS1UB diode D8, the collector of the Q4 is connected with one end of a resistor R33 and the cathode of the D8, and the other end of the R33 is connected with a DEXT end.
The frequency quantity output (digital quantity output) outputs a PWM signal of a programmable frequency using a timer function of the controller. The conversion of signal voltage from 3.3V to 5V is completed by using a 74LVCH2T45DC chip. The output end of the interface is designed to be an NPN open-drain type output, and the design allows a user to provide an external voltage reference and output the frequency quantity output under the specified voltage through an external load.
The counting output utilizes the IO port function and the timer function of the controller to output a low-speed switching signal. The conversion of signal voltage from 3.3V to 5V is completed by using a 74LVCH2T45DC chip. The output end of the interface is designed to be an NPN open-drain type output, and the design allows a user to provide an external voltage reference and output a counting quantity output under a specified voltage through an external load.
The utility model discloses still include SGM41000 chip U10, U10's 1 foot links to each other with resistance R63 one end, electric capacity C46 one end respectively, and another termination VBAT end of R63, U10's 2, 3, 7 foot ground connection, U10's 4, 5 foot ground connection, and electric capacity C45 ground connection is passed through to U10's 6 feet, and C46 other end ground connection.
The alarm circuit comprises a buzzer BZ1 and a BZ2, wherein the positive electrode of BZ1 is respectively connected with the VCC3.3 end, the positive electrode of BZ2 and the cathode of a diode D10, the negative electrode of BZ1 is respectively connected with the positive electrode of D10, the negative electrode of BZ1, the negative electrode of BZ2 and the collector of an SS8050 triode Q10, the base electrode of Q10 is respectively connected with one end of a resistor R74 and one end of a resistor R75, the other end of R74 is connected with a BEEP end, and the other end of R75 is respectively connected with the emitter of Q10 and the ground wire.
The utility model discloses the signal can divide into: four analog quantities, one frequency quantity and one counting quantity.
Analog quantity (the range can be set to be 5-6 adjustable, such as 4-20mA, 4, 8, 12, 16, 20MA can be output, and the voltage is 0, 1, 2, 3, 4, 5): (1)4-20mA, two-wire system, wherein the power supply is 24V. (2)4-20mA, two-wire system, wherein no power is required and the signal is directly output. (3)0-5V, two-wire system, wherein the power supply is 24V. And (4)0-5V, two-wire system, wherein power supply is not needed and signals are directly output.
Frequency quantity: power supply 24V, two-wire system, output 60HZ, 120HZ, 360HZ, 540HZ, 720HZ, 1200HZ, 1800HZ,24000 HZ.
Counting: the initial count value is 40000, the number of the initial count values is sequentially increased or decreased, 1 pulse can be added each time, the speed can reach 1HZ, and 4 wiring terminals can be led out from the channel and are respectively a power supply positive (8V), a power supply negative, a signal A and a signal B. The direct signal A and the signal B output electric signals of +8,0, 0 and-8 (positive direction increment) and-8, 0,0 and +8 (negative direction decrement).
The utility model can be powered by batteries, and is convenient to hold and carry.
It should be understood that the above detailed description of the present invention is only for illustrating the present invention and is not limited by the technical solutions described in the embodiments of the present invention, and those skilled in the art should understand that the present invention can still be modified or equivalently replaced to achieve the same technical effects; as long as the use requirement is satisfied, the utility model is within the protection scope.
Claims (5)
1. The logging parameter simulator comprises a controller, and is characterized in that a signal output port of the controller is respectively connected with a 4-20mA output part, a 0-5V output part, a frequency quantity output part and a counting quantity output part.
2. The logging parameter simulator of claim 1, wherein the display signal output port of the controller is connected to the display circuit, the alarm signal output port of the controller is connected to the alarm circuit, and the signal input port of the controller is connected to the key input section.
3. The logging parameter simulator of claim 1, wherein the power port of the controller is connected to the output port of the regulated power supply, the input port of the regulated power supply is connected to the output port of the charge management section, and the charge management section is connected to the lithium battery and the USB port, respectively.
4. The logging parameter simulator of claim 1, wherein the controller employs a STMCU _ LQFP64 chip U5, wherein a pin 5 of U5 is connected to one end of a crystal oscillator X3, the other end of X3 is connected to a pin 6 of U5, a pin 1 of U5 is connected to VBAT/VLCD terminal, VDD terminal, one end of a capacitor C29, and the other end of C29 is grounded;
the pin 13 of U5 is connected with AVDD terminal, one end of inductance L1, the other end of L1 is connected with VDD terminal, 32 pin of U5, 64 pin of U5, 48 pin of U5 and 19 pin of U5, pin 18 of U5 is grounded, pin 47 of U5 is grounded through capacitor C22, pin 63 of U5 is grounded, pin 31 of U5 is grounded through capacitor C25, pin 12 of U5 is grounded, pin 60 of U5 is grounded through resistor R55, pin 7 of U5 is connected with one end of resistor R54, one end of switch S2 and one end of capacitor C14, the other end of R54 is connected with VDD terminal, and the other ends of S2 and C14 are grounded.
5. The logging parameter simulator of claim 3, wherein the charging management section employs a bq24195 chip U9, wherein pin 1 of U9 is connected to terminal C39 of capacitor, terminal C38 of capacitor, terminal VBUS of capacitor, and pin 24 of U9, and the other terminal C39 and the other terminal C38 are grounded;
the pin 2 of the U9 is connected with the pin 3 of the U9 through a CB 2;
the 4 pins of the U9 are connected with the cathode of the LED1 through a resistor R50, and the anode of the LED1 is connected with the VREG end;
the pin 5 of U9 is connected with the VCC3.3 end through a resistor R48;
the pin 6 of the U9 is connected with the VCC3.3 end through a resistor R49;
the 8 feet of U9 are connected with one end of a resistor R52 and the collector of an NPN triode Q7 respectively, the other end of R52 is connected with the VSYS end, the base of Q7 is connected with one end of a resistor R51 and one end of a resistor R62 respectively, the other end of R51 is connected with the VBUS _ IN end, and the other end of R62 is connected with the collector of Q7 and the ground wire respectively;
pin 9 of U9 is connected to ground through resistor R58;
the pin 10 of U9 is grounded through a resistor R59;
the pin 11 of the U9 is respectively connected with the pin 12 of the U9, one end of a resistor R53, one end of a resistor R60 and one end of a resistor R61, the other end of the R53 is connected with a VREG end, and the other end of the R60 and the other end of the R61 are grounded;
a pin 13 of the U9 is respectively connected with a pin 14 of the U9, one end of a capacitor C44, one end of a capacitor C43 and a VBAT end, and the other end of the C44 and the other end of the C43 are grounded;
the pin 15 of U9 is respectively connected with the pin 16 of U9, one end of an inductor L6, one end of a capacitor C42, one end of a capacitor C40, one end of a capacitor C41 and a VSYS end, the other end of C42, the other end of C40 and the other end of C41 are grounded, the other end of L6 is respectively connected with one end of the capacitor C37, the pin 19 of U9 and the pin 20 of U9, and the other end of C37 is connected with the pin 21 of U9;
pins 17 and 18 of U9 are grounded;
a pin 22 of the U9 is respectively connected with one end of a capacitor C35 and the VREG end, and the other end of the capacitor C35 is grounded;
the pin 23 of the U9 is connected to one end of a capacitor C36, one end of a capacitor C34, one end of a capacitor C33, the end of VBST5V1 and one end of a resistor R45, the other end of the C36, the other end of the C34 and the other end of the C33 are grounded, the other end of the R45 is connected to one end of a resistor R46 and the end of lowbat, and the other end of the R46 is grounded.
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| CN202020301635.6U CN212322080U (en) | 2020-03-12 | 2020-03-12 | Logging parameter simulator |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111190359A (en) * | 2020-03-12 | 2020-05-22 | 辽宁众联石油天然气有限公司 | Logging parameter simulator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111190359A (en) * | 2020-03-12 | 2020-05-22 | 辽宁众联石油天然气有限公司 | Logging parameter simulator |
| CN111190359B (en) * | 2020-03-12 | 2024-12-17 | 辽宁众联石油天然气有限公司 | Logging parameter simulator |
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