CN211930788U - A master-slave configurable Hart interface circuit - Google Patents

Abstract

The embodiment of the utility model discloses a master-slave configurable Hart interface circuit, which includes: a Hart slave mode circuit, a Hart master mode circuit, a Hart signal filter circuit, a Hart modem, a master controller and a power supply circuit; wherein, the Hart slave mode circuit, one end of which is electrically connected to the terminal of the Hart slave terminal, and the other end is electrically connected to the Hart modem; the Hart master mode circuit, one end of which is electrically connected to the terminal of the Hart master terminal, and the other end is electrically connected to the Hart modem; the The Hart signal filtering circuit is electrically connected to the Hart modem; the Hart modem is electrically connected to the main controller. The utility model can flexibly configure the corresponding interface circuit according to the requirements to realize the digital communication with the industrial field bus; at the same time, the product design of the engineers can be simplified, and the master-slave configurable hart can be provided for users without increasing the cost. Interface Circuit.

Description

A master-slave configurable Hart interface circuit

technical field

The utility model relates to the technical field of communication interfaces, in particular to a master-slave configurable Hart interface circuit.

Background technique

The original old-fashioned analog transmitter has gradually withdrawn from the stage of history, and replaced by an intelligent transmitter with a microcontroller as the core of data processing and control. The smart transmitter expands the functions of the analog transmitter, not only improves the measurement accuracy and reliability, but also easily realizes functions such as linearization, temperature compensation, automatic zero and span adjustment, and digital communication.

Since there are still a large number of transmitters using the 4-20mA standard in the industrial field, considering the compatibility with standard analog signals, the American Rosemount Company proposed the HART communication protocol. At present, the HART protocol has become one of the most widely used field communication protocols in the world.

At present, the existing HART modem-based circuit design is quite complicated, and basically there are many smart transmitters that use slave mode according to application requirements. However, if it is required to control the field actuator through 4-20mA and the control parameters can be configured, it is necessary to additionally use the HART master mode interface circuit.

SUMMARY OF THE INVENTION

Based on this, in order to solve the deficiencies in the prior art, a master-slave configurable hart interface circuit is proposed.

A master-slave configurable Hart interface circuit, comprising: a Hart slave mode circuit, a Hart master mode circuit, a Hart signal filter circuit, a Hart modem, a master controller, and a power supply circuit; wherein the Hart slave mode circuit, One end is electrically connected to the terminal of the Hart slave terminal, and the other end is electrically connected to the Hart modem; one end of the Hart master mode circuit is electrically connected to the terminal of the Hart master terminal, and the other end is electrically connected to the Hart modem; The Hart modem is electrically connected; the Hart modem is electrically connected to the host controller.

Optionally, in one of the embodiments, the Hart modem and the host controller are connected through a UART interface and an SPI interface.

Optionally, in one embodiment, the Hart signal filtering circuit adopts a band-pass filter.

Optionally, in one of the embodiments, the Hart modem adopts an NCN5193 CMOS modem.

Optionally, in one of the embodiments, the Hart main mode circuit includes: a first resistor R16, a second resistor R17, a third resistor R18, a fourth resistor R19, a fifth resistor R20, a sixth resistor R21, a Seven resistors R22, the first PNP transistor Q2, the first analog switch U2, the first capacitor C8, the second capacitor C9, and the first operational amplifier AS2A; wherein, one end of the first resistor R16 is connected to the RTS pin, and the other end is connected to the first The base of a PNP transistor Q2; the emitter of the first PNP transistor Q2 is connected to the power supply, and the collector is connected to the non-inverting input terminal of the first operational amplifier AS2A; one end of the second resistor R17 is connected to the collector of the first PNP transistor Q2 , the other end is grounded; one end of the fifth resistor R20 is connected to the ARTF pin, and the other end is connected to the non-inverting input end of the first operational amplifier AS2A; the inverting input end of the first operational amplifier AS2A is grounded, and its output end is connected to the first operational amplifier AS2A. The moving end of the analog switch U2; one of the fixed ends of the first analog switch U2 is connected to the LOOP+ terminal of the Hart main terminal via the first capacitor C8, and the other fixed end is connected to the collector of the first PNP transistor Q2; the third One end of the resistor R18 is connected to the ADC pin, and the other end is connected to the LOOP+ terminal of the Hart main terminal; one end of the fourth resistor R19 is connected to the third resistor R18, and the other end is connected to the LOOP- terminal of the Hart main terminal; the sixth One end of the resistor R21 is connected to the T×AM pin via the seventh resistor R22; one end of the second capacitor C9 is connected to the output end of the first operational amplifier AS2A, and the other end is connected to the inverting input end of the first operational amplifier AS2A.

Optionally, in one embodiment, the Hart slave mode circuit includes an eighth resistor R9, a ninth resistor R10, a tenth resistor R11, an eleventh resistor R12, a twelfth resistor R13, and a thirteenth resistor R14. , the fourteenth resistor R15, the first NPN transistor Q1, the third capacitor C5, the fourth capacitor C6, the fifth capacitor C7 and the second operational amplifier AS1A; wherein, one end of the eighth resistor R9 passes through the third capacitor C5 Connect the T×AS pin, and the other end is connected to the non-inverting input terminal of the second operational amplifier AS1A; the output terminal of the second operational amplifier AS1A is connected to the base of the first NPN transistor Q1, the non-inverting input terminal is connected to the power supply, and the inverting input terminal is connected The terminal is grounded; the collector of the first NPN transistor Q1 is connected to the LOOP+ terminal of the Hart slave terminal, and its emitter is connected to the LOOP- terminal of the Hart slave terminal via the tenth resistor R11 and the eleventh resistor R12; the tenth One end of the resistor R11 is connected to the emitter of the first NPN transistor Q1, and the other end is connected to the eleventh resistor R12; one end of the eleventh resistor R12 is grounded, and the other end is connected to the LOOP- terminal of the Hart slave terminal; the fourth One end of the capacitor C6 is connected to the inverting input end of the second operational amplifier AS1A, and the other end is connected to the output end of the second operational amplifier AS1A; one end of the ninth resistor R10 is connected to the inverting input end of the second operational amplifier AS1A, and the other end is connected to the inverting input end of the second operational amplifier AS1A. Twelve resistors R13 are connected to the LOOP- terminal of the Hart slave terminal; one end of the thirteenth resistor R14 is connected to the DAC pin, the other end is connected to the fourteenth resistor R15, and the other end of the fourteenth resistor R15 is connected to the twelfth resistor R13; one end of the fifth capacitor C7 is respectively connected to the thirteenth resistor R14 and the fourteenth resistor R15, and the other end is grounded.

Optionally, in one embodiment, the Hart interface circuit further includes a Hart master-slave mode configuration circuit.

Implementing the embodiments of the present utility model will have the following beneficial effects:

The utility model designs a Hart interface circuit with switchable configuration in the master-slave mode, which can transmit the required current loop in the slave mode, accept the current signal sent by the control system and use it for control in the master mode, and can also Modulate and demodulate the Hart carrier signal on the current loop to expand the product application range for users; at the same time, it can also set the clock, analog output, and working mode of the Hart modem chip through the SPI interface of the MCU. The interface can complete Hart communication with field devices. All in all, the utility model can flexibly configure the corresponding interface circuit according to the requirements, and realize the digital communication with the industrial field bus; at the same time, it can also simplify the product design of engineers, and provide users with master-slave configurability without increasing the cost. hart interface circuit.

Description of drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are just some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

in:

1 is a circuit schematic diagram of the Hart interface circuit described in one embodiment;

2 is a circuit diagram of the Hart master mode circuit described in one embodiment;

3 is a circuit diagram of the Hart slave mode circuit described in one embodiment;

4 is a circuit diagram of the Hart signal filtering circuit described in one embodiment;

FIG. 5 is a circuit diagram of the Hart master-slave mode configuration circuit in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present utility model more clearly understood, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not intended to limit the present invention.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. It will be understood that the terms "first", "second", etc. used in the present invention may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. Both the first element and the second element are elements, but they are not the same element.

In order to solve the problems existing in the prior art, in this embodiment, a master-slave configurable Hart interface circuit is specially proposed, which can realize the configuration switching of the master-slave mode, for example, in the slave mode, it can transmit the output 4 The -20mA current loop can accept the 4-20mA current signal sent by the DCS control system and use it for control in the main mode, and can also modulate and demodulate the Hart carrier signal on the current loop. Based on the above design principles, as shown in Figure 1, the Hart interface circuit includes a Hart slave mode circuit, a Hart master mode circuit, a Hart signal filter circuit, a Hart modem, a master controller, and a low-power power supply circuit (not shown in the figure); wherein In the Hart slave mode circuit, one end is electrically connected to the terminal of the Hart slave terminal, and the other end is electrically connected to the Hart modem; the Hart master mode circuit is electrically connected to the terminal of the Hart master terminal at one end, and the other end is electrically connected to the Hart modem; The Hart signal filtering circuit is electrically connected to the Hart modem; the Hart modem is electrically connected to the main controller.

In some specific embodiments, the main controller adopts STM32L152RCT6 low-power embedded microcontroller; STM32L152RCT6 is a low-power embedded microcontroller, which can receive and send communication signals to a modem chip, that is, the Hart modem, and Convert the collected sensor signal into engineering dimension; the Hart modem adopts NCN5193 CMOS modem. The corresponding working process is: the low-power power supply circuit provides power (3.0V) for the master controller and the Hart modem to use, specifically: in the slave mode, the sensor signal is converted into a 4-20mA current and transmitted to the control It can load the Hart signal of the main device (usually the host computer or control system), and convert it into a standard RS232 communication signal through the NCN5193 CMOS modem and complete the communication with the STM32L152RCT6, a low-power embedded microcontroller; in the main mode, the Hart signal is loaded On the 4-20mA current loop output from the control room for control.

In some specific embodiments, the Hart signal filtering circuit adopts a band-pass filter to separate the Hart digital signal from the 4-20 mA signal. As shown in Figure 4, a typical Sallen-Key band-pass filter is used, which is placed in the NCN5193 chip; the filtering range of the filter is 620Hz to 2500Hz, and the Hart signal is 1200Hz and 2400Hz, so it can just cover signal frequency.

In some specific embodiments, the Hart modem and the host controller are connected through a UART interface and an SPI interface.

In some specific embodiments, as shown in FIG. 2 , the main design points of the Hart interface circuit in the main mode: because it needs to work under a small current of 3.5mA, it is necessary to design a low-power circuit; 4-20mA signal, you can use the 125 ohm precision sampling resistor R19 to convert the signal into a 0.5-2.5V voltage signal for the main controller to become a digital quantity for control output; The corresponding information is sent when the corresponding information is sent; here, the RTS request sending signal is used to turn on the sending circuit through the 74LVC1G66 analog switch to achieve the purpose of power saving, etc.; based on the above design purpose, the specific Hart main mode circuit includes: the first resistor R16, the second resistor R17, The third resistor R18, the fourth resistor R19, the fifth resistor R20, the sixth resistor R21, the seventh resistor R22, the first PNP transistor Q2, the first analog switch U2, the first capacitor C8, the second capacitor C9, the first operation Amplifier AS2A; wherein, one end of the first resistor R16 is connected to the RTS pin, and the other end is connected to the base of the first PNP transistor Q2; the emitter of the first PNP transistor Q2 is connected to the power supply, and the collector is connected to the first operational amplifier AS2A One end of the second resistor R17 is connected to the collector of the first PNP transistor Q2, and the other end is grounded; one end of the fifth resistor R20 is connected to the ARTF pin, and the other end is connected to the non-inverting input of the first operational amplifier AS2A The inverting input end of the first operational amplifier AS2A is grounded, and its output end is connected to the moving end of the first analog switch U2; the first analog switch U2 one of the fixed ends is connected to the LOOP+ wiring of the Hart main terminal via the first capacitor C8 The other end is connected to the collector of the first PNP transistor Q2; one end of the third resistor R18 is connected to the ADC pin, and the other end is connected to the LOOP+ terminal of the Hart main terminal; one end of the fourth resistor R19 is connected to the The third resistor R18, the other end is connected to the LOOP- terminal of the Hart main terminal; one end of the sixth resistor R21 is connected to the T×AM pin via the seventh resistor R22; one end of the second capacitor C9 is connected to the first operational amplifier The output end of AS2A is connected to the inverting input end of the first operational amplifier AS2A at the other end.

In some specific embodiments, as shown in FIG. 3 , the Hart slave mode circuit includes an eighth resistor R9, a ninth resistor R10, a tenth resistor R11, an eleventh resistor R12, a twelfth resistor R13, and a thirteenth resistor R14, the fourteenth resistor R15, the first NPN transistor Q1, the third capacitor C5, the fourth capacitor C6, the fifth capacitor C7 and the second operational amplifier AS1A; wherein, one end of the eighth resistor R9 passes through the third capacitor C5 is connected to the T×AS pin, and the other end is connected to the non-inverting input terminal of the second operational amplifier AS1A; the output terminal of the second operational amplifier AS1A is connected to the base of the first NPN transistor Q1, and its non-inverting input terminal is connected to the power supply, and the inverting terminal is connected to the power supply. The input terminal is grounded; the collector of the first NPN transistor Q1 is connected to the LOOP+ terminal of the Hart slave terminal, and its emitter is connected to the LOOP- terminal of the Hart slave terminal via the tenth resistor R11 and the eleventh resistor R12; One end of the ten resistor R11 is connected to the emitter of the first NPN transistor Q1, and the other end is connected to the eleventh resistor R12; one end of the eleventh resistor R12 is grounded, and the other end is connected to the LOOP- terminal of the Hart slave terminal; One end of the four capacitor C6 is connected to the inverting input end of the second operational amplifier AS1A, and the other end is connected to the output end of the second operational amplifier AS1A; one end of the ninth resistor R10 is connected to the inverting input end of the second operational amplifier AS1A, and the other end is The twelfth resistor R13 is connected to the LOOP- terminal of the Hart slave terminal; one end of the thirteenth resistor R14 is connected to the DAC pin, the other end is connected to the fourteenth resistor R15, and the other end of the fourteenth resistor R15 is connected to the twelfth resistor Resistor R13; one end of the fifth capacitor C7 is respectively connected to the thirteenth resistor R14 and the fourteenth resistor R15, and the other end is grounded. The circuit can well complete the superposition of the digital-to-analog conversion and the Hart signal to generate a 4-20mA signal corresponding to the sensing signal.

In some specific embodiments, the Hart interface circuit further includes a Hart master-slave mode configuration circuit, as shown in FIG. 5 , which completes the master-slave mode configuration through two jumper caps. The SPDT analog switch chip 74LVC1G3157 selects the channel through the S terminal; when the Jumper1 is connected, the S terminal is low, and the A terminal is connected with the B1 terminal, that is, the TxAM is connected to the TxA signal as the main mode; on the contrary, when the Jumper2 is connected, the S The terminal is high, and the A terminal is connected to the B2 terminal, that is, the TxAS is connected to the TxA signal in the slave mode.

Therefore, it can be said that the utility model can flexibly configure the corresponding interface circuit according to the requirements to realize digital communication with the industrial field bus; at the same time, it can also simplify the product design of engineers, and provide users with master-slave under the premise of not increasing the cost. Configurable hart interface circuit.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the patent of the present application. It should be noted that, for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (7)

1. a master-slave configurable Hart interface circuit is characterized in that, comprising: Hart slave mode circuit, Hart master mode circuit, Hart signal filter circuit, Hart modem, master controller and power supply circuit; Wherein said Hart slave mode a circuit, one end of which is electrically connected to the terminal of the Hart slave terminal, and the other end is electrically connected to the Hart modem; the Hart master mode circuit, one end of which is electrically connected to the terminal of the Hart master terminal, and the other end is electrically connected to the Hart modem; the Hart signal filtering The circuit is electrically connected to the Hart modem; the Hart modem is electrically connected to the host controller. 2 . The master-slave configurable Hart interface circuit according to claim 1 , wherein the Hart modem and the main controller are connected through a UART interface and an SPI interface. 3 . 3. The master-slave configurable Hart interface circuit according to claim 1, wherein the Hart modem adopts an NCN5193 CMOS modem. 4. The master-slave configurable Hart interface circuit according to claim 3, wherein the Hart master mode circuit comprises: a first resistor R16, a second resistor R17, a third resistor R18, a fourth resistor R19, The fifth resistor R20, the sixth resistor R21, the seventh resistor R22, the first PNP transistor Q2, the first analog switch U2, the first capacitor C8, the second capacitor C9, and the first operational amplifier AS2A; wherein, the first resistor One end of R16 is connected to the RTS pin, and the other end is connected to the base of the first PNP transistor Q2; the emitter of the first PNP transistor Q2 is connected to the power supply, and the collector is connected to the non-inverting input of the first operational amplifier AS2A; the second resistor One end of R17 is connected to the collector of the first PNP transistor Q2, and the other end is grounded; one end of the fifth resistor R20 is connected to the ARTF pin, and the other end is connected to the non-inverting input of the first operational amplifier AS2A; the inverse of the first operational amplifier AS2A The phase input terminal is grounded, and its output terminal is connected to the moving terminal of the first analog switch U2; one of the fixed terminals of the first analog switch U2 is connected to the LOOP+ terminal of the Hart main terminal via the first capacitor C8, and the other fixed terminal is connected to the first analog switch U2. The collector of the PNP transistor Q2; one end of the third resistor R18 is connected to the ADC pin, and the other end is connected to the LOOP+ terminal of the Hart main terminal; one end of the fourth resistor R19 is connected to the third resistor R18, and the other end is connected to the Hart main terminal LOOP-terminal of the terminal; one end of the sixth resistor R21 is connected to the T×AM pin via the seventh resistor R22; one end of the second capacitor C9 is connected to the output end of the first operational amplifier AS2A, and the other end is connected to the The inverting input of the first operational amplifier AS2A. 5. The master-slave configurable Hart interface circuit according to claim 4, wherein the Hart slave mode circuit comprises an eighth resistor R9, a ninth resistor R10, a tenth resistor R11, an eleventh resistor R12, The twelfth resistor R13, the thirteenth resistor R14, the fourteenth resistor R15, the first NPN transistor Q1, the third capacitor C5, the fourth capacitor C6, the fifth capacitor C7 and the second operational amplifier AS1A; One end of the eight resistor R9 is connected to the T×AS pin via the third capacitor C5, and the other end is connected to the non-inverting input end of the second operational amplifier AS1A; the output end of the second operational amplifier AS1A is connected to the base of the first NPN transistor Q1 , its non-inverting input terminal is connected to the power supply, and the inverting input terminal is grounded; the collector of the first NPN transistor Q1 is connected to the LOOP+ terminal of the Hart slave terminal, and its emitter is connected to the Hart slave via the tenth resistor R11 and the eleventh resistor R12. LOOP-terminal of the terminal; one end of the tenth resistor R11 is connected to the emitter of the first NPN transistor Q1, and the other end is connected to the eleventh resistor R12; one end of the eleventh resistor R12 is grounded, and the other end is connected to the Hart LOOP-terminal of the terminal; one end of the fourth capacitor C6 is connected to the inverting input end of the second operational amplifier AS1A, and the other end is connected to the output end of the second operational amplifier AS1A; one end of the ninth resistor R10 is connected to the second operational amplifier The inverting input end of AS1A is connected to the LOOP- terminal of the Hart slave terminal via the twelfth resistor R13; one end of the thirteenth resistor R14 is connected to the DAC pin, and the other end is connected to the fourteenth resistor R15. The other end of the fourteen resistor R15 is connected to the twelfth resistor R13; one end of the fifth capacitor C7 is connected to the thirteenth resistor R14 and the fourteenth resistor R15 respectively, and the other end is grounded. 6 . The master-slave configurable Hart interface circuit according to claim 5 , wherein the Hart interface circuit further comprises a Hart master-slave mode configuration circuit. 7 . 7 . The master-slave configurable Hart interface circuit according to claim 1 , wherein the Hart signal filtering circuit adopts a band-pass filter. 8 .

Images