CN211830573U - Power factor correction device - Google Patents

Abstract

The utility model provides a power factor correction device, which solves the problems of charging power factor correction and the like, the voltage boosting circuit comprises a second capacitor C1, a first capacitor C0 and a switch tube Q which are connected in parallel in the rectification circuit, an inductor L, a detection resistor RS and a fuse FU are connected in series between the second capacitor C1 and the switch tube Q, a diode D is connected in series between the switch tube Q and the first capacitor C0, a resistor R and a third capacitor C2 which are connected in series are connected in parallel on the diode D, the input end of the rectification circuit is communicated with the input end of a multiplier K through a feedforward voltage division network, the output end of the rectification circuit is communicated with the input end of the multiplier K through a voltage compensation network, the multiplier K and the rectification circuit are communicated with a current compensation network, and the current compensation network is connected with and controls the switch tube Q in the voltage boosting circuit after passing through a pulse width modulation circuit. The utility model has the advantages of small steady state error, less harmonic pollution and the like.

Description

Power factor correction device

technical field

The utility model belongs to the technical field of electric vehicle charging, in particular to a power factor correction device.

Background technique

With the massive consumption of energy and the increasingly serious air pollution problem, electric vehicles, as a new type of transportation, have become an inevitable trend in the development of the automobile industry due to their superior performance of energy saving and environmental protection. As an important equipment for electric vehicle energy supplement, the development of its technology is one of the key technologies that must be solved in the commercialization of electric vehicles. The boost-active power factor correction circuit can maintain a high input power factor and a small input current ripple when the input voltage and input frequency vary widely, and can reduce the harmonic pollution of the public grid. However, in actual use, the frequency and phase of the input voltage and input current of each module are often different, and the power factor needs to be corrected. In addition, the fluctuation of power often leads to unstable voltage, and the overall circuit loss is more.

In order to solve the shortcomings of the existing technology, people have carried out long-term exploration and proposed various solutions. For example, a Chinese patent document discloses a partially active power factor correction circuit with input voltage threshold control [201410076664.6], which includes a double-loop controlled boost circuit, a voltage error amplifier, a multiplier K, a current error amplifier, and an input voltage sampling Signal sampling threshold judgment module, PWM waveform generation module, and PWM drive IC.

The above scheme solves the problem of high overall circuit consumption to a certain extent, but there are still many shortcomings in this scheme, such as power factor correction of the input voltage and input current frequency, phase and other problems of each module.

SUMMARY OF THE INVENTION

The purpose of the utility model is to solve the above problems, and provide a power factor correction device with reasonable design and convenient power factor correction.

In order to achieve the above-mentioned purpose, the utility model adopts the following technical scheme: the power factor correction device includes a rectifier circuit connected with the power supply, the rectifier circuit includes a booster circuit connected with the load RL, and the booster circuit includes a parallel connection in the rectifier circuit. The second capacitor C1, the first capacitor C0 and the switch Q, the inductor L, the detection resistor RS and the fuse FU are connected in series between the second capacitor C1 and the switch Q, and the switch Q and the first capacitor C0 are connected in series A diode D is connected, and a series-connected resistor R and a third capacitor C2 are connected to the diode D. The input end of the rectifier circuit is connected to the input end of the multiplier K through a feedforward voltage divider network, and the output end of the rectifier circuit is compensated by voltage. The network is connected to the input end of the multiplier K, the multiplier K and the rectifier circuit are connected to the current compensation network, and the current compensation network is connected to the switch tube Q in the booster circuit after passing through the pulse width modulation circuit. Correct the power factor in time to reduce the steady-state error.

In the above power factor correction device, the feedforward voltage divider network includes a second-order low-pass filter composed of a first resistor RFF1, a second resistor RFF2, a third resistor RFF3, a fourth capacitor CFF1, and a fifth capacitor CFF2. After filtering by the second-order low-pass filter, the obtained DC voltage is flatter and more ideal.

In the above power factor correction device, the fifth capacitor CFF2 and the third resistor RFF3 are connected to the ground, and then the second resistor RFF2 and the first resistor RFF1 are connected in series, and the fourth capacitor CFF1 is passed between the second resistor RFF2 and the first resistor RFF1 It is connected to the ground terminals of the fifth capacitor CFF2 and the third resistor RFF3, and the rectifier circuit is connected to the multiplier K through a voltage dividing resistor RAC.

In the above power factor correction device, the voltage compensation network includes a voltage operational amplifier V1. The voltage compensation network filters out the second and above harmonics to ensure the stability of the output voltage, and the maximum value of the ripple voltage allowed by the output of the voltage operational amplifier V1.

In the above power factor correction device, the inverting input terminals of the voltage operational amplifier V1 are respectively connected to the rectifier circuit through the fourth resistor RV1, and the fifth resistor RVD is connected in series to the ground.

In the above power factor correction device, the inverting input terminal of the voltage operational amplifier V1 is connected in parallel with the sixth capacitor CVF and the sixth resistor RVF and then connected to the output terminal of the voltage operational amplifier V1.

In the above power factor correction device, the current compensation network includes a current operational amplifier V2, and a seventh resistor R1 is connected to the inverting input end of the current operational amplifier V2. The current compensation network is connected with the pulse width modulation circuit, and the output deviation signal is modulated by the sawtooth wave signal to obtain the PWM pulse width modulation signal which drives the switching tube Q to open and close.

In the above power factor correction device, the inverting input terminal of the current operational amplifier V2 is connected to the output terminal of the current operational amplifier V2 through the third capacitor C2, and the third capacitor C2 is connected with the second capacitor C1 and the eighth resistor R2. The circuits are connected in parallel, and a ninth resistor RMO is connected to the positive input end of the current operational amplifier V2. Setting the voltage and current compensation network can realize the input current and the input voltage at the same frequency and phase, correct the power factor in time, and achieve the purpose of low harmonics and low pollution.

In the above-mentioned power factor correction device, the multiplier K, the voltage compensation network, the current compensation network and the pulse width modulation circuit are arranged in the control chip. The control chip is convenient for wiring and is suitable for various automotive circuit systems.

Compared with the prior art, the utility model has the advantages that the power factor is corrected in time to reduce the steady state error; the input current and voltage are in the same frequency and phase, the power factor is improved, and the harmonic pollution to the public power grid is reduced; the overall structure of the circuit is compact, Applicable to various automotive circuit systems.

Description of drawings

Fig. 1 is the structural representation of the present utility model;

Fig. 2 is the structural representation of the second-order low-pass filter of the present utility model;

Fig. 3 is the structural representation of the current compensation network of the present invention;

4 is a schematic structural diagram of a voltage compensation network of the present invention;

In the figure, the first capacitor C0, the second capacitor C1, the third capacitor C2, the fourth capacitor CFF1, the fifth capacitor CFF2, the sixth capacitor CVF, the first resistor RFF1, the second resistor RFF2, the third resistor RFF3, the fourth resistor RV1, fifth resistor RVD, sixth resistor RVF, seventh resistor R1, eighth resistor R2, ninth resistor RMO, switch tube Q, detection resistor RS, inductor L, fuse FU, diode D, multiplier K, divider Piezoresistor RAC, voltage operational amplifier V1, current operational amplifier V2, voltage compensation network 1, current compensation network 2, pulse width modulation circuit 3, control chip 4, second-order low-pass filter 5.

Detailed ways

The present utility model will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Figure 1-4, the power factor correction device includes a rectifier circuit connected to the power supply, the rectifier circuit includes a booster circuit connected to the load RL, and the booster circuit includes a second capacitor C1, An inductor L, a detection resistor RS and a fuse FU are connected in series between the first capacitor C0 and the switch Q, the second capacitor C1 and the switch Q, and a diode D is connected in series between the switch Q and the first capacitor C0. A resistor R and a third capacitor C2 connected in series are connected to D in parallel. The input end of the rectifier circuit is connected to the input end of the multiplier K through the feedforward voltage divider network, and the output end of the rectifier circuit is connected to the multiplier K through the voltage compensation network 1. The input end of the multiplier K and the rectifier circuit are connected to the current compensation network 2, and the current compensation network 2 is connected to the switch tube Q in the control boost circuit after passing through the pulse width modulation circuit 3. The 220V commercial power obtains a half-sine wave signal through the rectifier circuit. This signal is connected to the reverse input end of the voltage operational amplifier V1 through the feedforward voltage divider network, and is compared with the base signal, amplified and sent to the multiplier K. The signal output by the multiplier K is used as the reference signal of the current compensation network 2. The signal is compared with the sampled inductor current to obtain a deviation signal. The deviation signal is modulated by the pulse width modulation circuit to obtain the PMW pulse width modulation signal that drives the switch tube Q. It is ensured that the input side current and voltage are in the same phase, and the power factor correction is realized.

In addition, considering the inductor winding resistance and the equivalent series resistance of the output capacitor, the boost circuit has two operating modes in the current continuous mode. Working mode 1: the switch tube Q is turned on, the power supply supplies power to the inductor L, and the first capacitor C0 provides power for the load RL to maintain the output. Working mode 2: The switch tube Q is turned off, the diode D is turned on, the power supply and the inductor L charge the first capacitor C0 at the same time, and supply energy for the load RL. The input inductance L plays the role of energy transmission, storage and filtering in the circuit. The selection of the magnetic core material and the winding of the wire determine the performance. The input inductance L of the utility model is composed of 8 strands of 0.3mm diameter enameled wires. The iron-silicon-aluminum powder magnetic core is wound with 100 turns. The second capacitor C1 mainly plays the role of filtering and energy storage, and its value is mainly determined by the output voltage holding time. In order to meet the output ripple requirements, seven 470μF high-voltage large capacitors are selected in parallel to reduce the equivalent series resistance. In order to meet the stress requirements of current and voltage, the power switch tube Q and diode D are selected from IXFX32N80P and MUR3060PT respectively.

Specifically, the feedforward voltage divider network includes a second-order low-pass filter 5 composed of a first resistor RFF1, a second resistor RFF2, a third resistor RFF3, a fourth capacitor CFF1, and a fifth capacitor CFF2. The fifth capacitor CFF2 and the third The three resistors RFF3 are connected to the ground, and then the second resistor RFF2 and the first resistor RFF1 are connected in series. The second resistor RFF2 and the first resistor RFF1 are connected to the ground terminals of the fifth capacitor CFF2 and the third resistor RFF3 through the fourth capacitor CFF1. The rectifier circuit is connected to the multiplier K through a voltage dividing resistor RAC.

In depth, the voltage compensation network 1 includes a voltage operational amplifier V1, the inverting input terminals of the voltage operational amplifier V1 are respectively connected to the rectifier circuit through the fourth resistor RV1, and the fifth resistor RVD is connected in series to the ground, and the inverting input of the voltage operational amplifier V1 The terminal is connected in parallel with the sixth capacitor CVF and the sixth resistor RVF and then connected to the output terminal of the voltage operational amplifier V1. The non-inverting input of the voltage operational amplifier V1 is the voltage reference. The reverse input is the output voltage sampling signal. The voltage compensation network filters out the second and above harmonics to ensure the stability of the output voltage.

It can be seen that the current compensation network 2 includes a current operational amplifier V2, the inverting input terminal of the current operational amplifier V2 is connected with a seventh resistor R1, and the inverting input terminal of the current operational amplifier V2 is connected to the output of the current operational amplifier V2 through the third capacitor C2 The third capacitor C2 is connected in parallel with the series circuit formed by the second capacitor C1 and the eighth resistor R2, and the positive input terminal of the current operational amplifier V2 is connected with the ninth resistor RMO. The inverting input of current op amp V2 is set to the inductor current.

Further, the multiplier K, the voltage compensation network 1 , the current compensation network 2 and the pulse width modulation circuit 3 are arranged in the control chip 4 . When set in the car charging system, the control chip 4 adjusts the installation position according to the actual situation.

To sum up, the principle of this embodiment is: by building a circuit, establishing a power circuit of an on-board charger, and setting a compensation network for voltage and current, the input current and the input voltage can be at the same frequency and phase, improve the power factor, and achieve low harmonics, low pollution purpose.

The specific embodiments described herein are merely illustrative of the spirit of the present invention. Those skilled in the art of the present invention can make various modifications or supplements to the described specific embodiments or replace them in similar ways, but will not deviate from the spirit of the present invention or go beyond the appended claims the defined range.

Although the first capacitor C0, the second capacitor C1, the third capacitor C2, the fourth capacitor CFF1, the fifth capacitor CFF2, the sixth capacitor CVF, the first resistor RFF1, the second resistor RFF2, the third resistor RFF3 are used more in this paper , the fourth resistor RV1, the fifth resistor RVD, the sixth resistor RVF, the seventh resistor R1, the eighth resistor R2, the ninth resistor RMO, the switch Q, the detection resistor RS, the inductor L, the fuse FU, the diode D, the multiplication K, voltage dividing resistor RAC, voltage operational amplifier V1, current operational amplifier V2, voltage compensation network 1, current compensation network 2, pulse width modulation circuit 3, control chip 4, second-order low-pass filter 5 and other terms, but not The possibility of using other terms is not excluded. These terms are used only to more conveniently describe and explain the essence of the present invention; it is contrary to the spirit of the present invention to interpret them as any kind of additional limitations.

Claims (10)

1. a power factor correction device, comprising a rectifier circuit connected with a power supply, wherein the rectifier circuit comprises a booster circuit connected with the load RL, and the booster circuit comprises a rectifier circuit connected in parallel in the rectifier circuit. The second capacitor C1, the first capacitor C0 and the switch Q, the inductance L, the detection resistor RS and the fuse FU are connected in series between the second capacitor C1 and the switch Q, the switch Q and the first A diode D is connected in series between the capacitors C0, and a resistor R and a third capacitor C2 are connected in parallel on the diode D. The input end of the rectifier circuit is connected to the input of the multiplier K through a feedforward voltage divider network. The output end of the rectifier circuit is connected to the input end of the multiplier K through the voltage compensation network (1), the multiplier K and the rectifier circuit are connected to the current compensation network (2), and the current compensation The network (2) is connected to the switch tube Q in the control booster circuit after passing through the pulse width modulation circuit (3). 2 . The power factor correction device according to claim 1 , wherein the feedforward voltage divider network comprises a first resistor RFF1 , a second resistor RFF2 , a third resistor RFF3 , a fourth capacitor CFF1 , a fifth A second-order low-pass filter (5) composed of capacitor CFF2. 3. The power factor correction device according to claim 2, wherein the second resistor RFF2 and the first resistor RFF1 are connected in series after the fifth capacitor CFF2 and the third resistor RFF3 are connected to the ground. The second resistor RFF2 and the first resistor RFF1 are connected to the ground terminals of the fifth capacitor CFF2 and the third resistor RFF3 through the fourth capacitor CFF1, and the rectifier circuit is connected to the multiplier K through the voltage dividing resistor RAC. 4. The power factor correction device according to claim 1, wherein the voltage compensation network (1) comprises a voltage operational amplifier V1. 5 . The power factor correction device according to claim 4 , wherein the inverting input terminals of the voltage operational amplifier V1 are respectively connected to the rectifier circuit through a fourth resistor RV1 , and the fifth resistor RVD is connected in series to ground. 6 . 6. The power factor correction device according to claim 4 or 5, wherein the reverse input end of the voltage operational amplifier V1 is connected in parallel with the sixth capacitor CVF and the sixth resistor RVF and the voltage operational amplifier V1. output connection. 7. The power factor correction device according to claim 1, wherein the current compensation network (2) comprises a current operational amplifier V2. 8. The power factor correction device according to claim 7, wherein the inverting input terminal of the current operational amplifier V2 is connected with a seventh resistor R1, and the inverting input terminal of the current operational amplifier V2 passes through The third capacitor C2 is connected to the output end of the current operational amplifier V2, and the third capacitor C2 is connected in parallel with the series circuit formed by the second capacitor C1 and the eighth resistor R2. 9 . The power factor correction device according to claim 7 , wherein the forward input end of the current operational amplifier V2 is connected with a ninth resistor RMO. 10 . 10. The power factor correction device according to claim 1, wherein the multiplier K, the voltage compensation network (1), the current compensation network (2) and the pulse width modulation circuit (3) are arranged on the control chip (4).

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