CN211791465U

CN211791465U - RC oscillator circuit of RFID label chip

Info

Publication number: CN211791465U
Application number: CN202020316052.0U
Authority: CN
Inventors: 张建伟
Original assignee: Shanghai Mingsi Microelectronics Co ltd
Current assignee: Shanghai Mingsi Microelectronics Co ltd
Priority date: 2020-03-16
Filing date: 2020-03-16
Publication date: 2020-10-27
Anticipated expiration: 2030-03-16

Abstract

The utility model provides a RC oscillator circuit of RFID label chip, its characterized in that contains: the circuit comprises a reference source circuit, a charging and discharging circuit, an SR latch and a switch control circuit. The main function of the reference source circuit is to generate the bias current Ib and its mirror currents I1 and I2. The charge and discharge circuit has the main function of finishing the charge and discharge process under the control of the switch control circuit to generate physical time delay. The main role of the SR latch is to generate the input signal of the switch control circuit and the output signal of the entire RC oscillator from the voltage flips of n1 and n 2. The switch control circuit mainly has the function of changing the phase of switch control according to the output signal of the SR latch, so that the charge and discharge circuit generates physical time delay. The beneficial effects of the utility model are that, need not to use operational amplifier and comparator among the traditional RC oscillator circuit, have the low power dissipation, the area is little, advantage that implementation is simple.

Description

RC oscillator circuit of RFID label chip

Technical Field

The utility model belongs to the technical field of integrated circuit design. And more particularly, to an RC oscillator of an RFID tag chip.

Background

RFID (radio frequency identification) is a system in which a reader and a tag perform contactless communication. The tag stores information, establishes communication with the reader by receiving the instruction sent by the reader and returning corresponding data, and transmits the information to the reader. The tags are classified into active tags, semi-active tags and passive tags. Different power supply modes determine the selection and design indexes of a circuit architecture in the label.

The oscillator is a basic circuit and is widely applied to various analog and digital-analog mixed products. Commonly used oscillators are classified into ring oscillators, RC oscillators, LC oscillators, and the like. The characteristics and the working principle of the oscillators are different, and a proper framework and a proper implementation mode are selected according to different application conditions and product requirements.

The oscillator circuit used in the RFID tag should meet the requirements of power consumption, area and accuracy. The traditional RC oscillator circuit structure is also provided with an operational amplifier and a comparator, so that the power consumption is high, the occupied area is large, and the RC oscillator circuit structure is not suitable for RFID labels.

Disclosure of Invention

In order to overcome traditional RC oscillator's shortcoming, the utility model provides a RC type oscillator suitable for RFID work requirement need not to use operational amplifier and comparator among the traditional RC oscillator circuit, has the low power dissipation, and the area is little, advantage that implementation is simple.

An RC oscillator circuit for an RFID tag chip, comprising: the circuit comprises a reference source circuit, a charging and discharging circuit, an SR latch and a switch control circuit.

The output end of the reference source circuit is divided into three paths, and the three paths are connected with the charging and discharging circuit. The main function of the reference source circuit is to generate the bias current Ib and its mirror currents I1 and I2.

The input end of the charge and discharge circuit is divided into 4 paths, namely bias current Ib, mirror current I1, mirror current I2 and a switch control signal phase, wherein the three input ends of Ib, I1 and I2 are all connected to a reference source circuit, and the phase is connected to the switch control circuit; the output terminal of which is connected to the SR latch. The charge and discharge circuit has the main function of finishing the charge and discharge process under the control of the switch control circuit to generate physical time delay.

The charging and discharging circuit can be divided into a charging part and a comparison part, the input Ib, I1 and I2 of the charging and discharging circuit are connected with the reference source circuit, and the input phase comes from the switch control circuit. Where Ib is used for charging, I1 and I2 provide a weak pull-up for the compare circuit. The output of the charge and discharge circuit is connected with the SR latch. The charge and discharge circuit comprises 4 switches, S1, S2, S3 and S4, capacitors C1 and C2 and two NMOSs M3 and M4, wherein the 4 switches are controlled by a phase signal which is connected with the switch control circuit. The upper pole plate of a capacitor C2 is connected with the gate end and S3 of the M3, the lower pole plate is grounded, the drain end of the M3 is connected with the I1, the source end is grounded, n1 is led out from the drain end of the M3, the upper pole plate of the capacitor C1 is connected with the gate end and S1 of the M4, the lower pole plate is grounded, the drain end and the source end of the M4 are connected with the I2, the source end is grounded, the n2 is led out from the drain end of the M4, Ib is respectively connected with the S1 and the S3, the S1 and the S2 are connected in series, the S2 is grounded, the S3 and the S4 are connected in series, and the S4 is grounded. S1 and S4 are turned on simultaneously, defined as phase-1 state, and S2 and S3 are turned on simultaneously, defined as phase-2 state.

When the circuit works in phase-1, Ib is used as a charging current to charge C1, when the voltage of the upper plate of C1 reaches the threshold voltage of NMOSM4, the pull-down circuit is conducted, and due to the strong design of the capacity of the pull-down circuit, after the grid electrode of the pull-down circuit reaches the threshold voltage to form a conductive channel, the voltage of a node n1 is pulled down, and a logic circuit at the later stage recognizes '0'; similarly, when the circuit operating state is switched to phase-2, S1 and S4 are opened, S2 and S3 are closed, Ib starts charging C2, and at the same time, the charge of C1 is rapidly discharged through S2 (the discharge time is much less than the charge time). When the upper plate voltage of C2 is charged to the threshold voltage of NMOS M3, the conducting channel of M3 is formed, the same pull-down capability is stronger than the pull-up of I2, the drain terminal voltage of M3 is pulled down, and node n2 is recognized as '0' by the subsequent logic circuit.

The input of the SR latch is divided into two paths which are connected to a charging and discharging circuit, namely n1 and n 2; the output of the RC oscillator is divided into two paths, is connected to a switch control circuit and is used as an output signal of the whole RC oscillator. The main function of the SR latch is to generate the input signal of the switch control circuit and the output signals osc _ out and osc _ out _ bar of the entire RC oscillator according to the voltage flip of n1 and n2, and osc _ out _ bar is the inverted signal of osc _ out.

The input of the switch control circuit is divided into two paths which are connected to the SR latch; the output is 1-way phase signal, which is connected to the charge and discharge circuit. The switch control circuit mainly has the function of changing the phase of switch control according to the output signal of the SR latch, so that the charge and discharge circuit generates physical time delay. The Phase signal may indicate two states: phase-1 and phase-2.

The utility model has the advantages that the static power consumption only has the dynamic power consumption of the bias current Ib and the logic part, so that the power consumption of the oscillator is lower; because the threshold voltage of the NMOS is used as the comparison voltage, the charging time is not influenced by the height of the power supply, and the NMOS can share the power supply with the reference generation module, so that two paths of charging currents can be combined into one path, a part for current mirror image copying is saved, the comparison part is in competition of weak pull-up and strong pull-down, the RC oscillator is simple and efficient, an operational amplifier and a comparator in the traditional RC oscillator circuit are avoided, and the area and the power consumption of the oscillator are smaller.

Drawings

Fig. 1 is a circuit block diagram of an RC oscillator of an RFID tag chip according to the present invention;

fig. 2 is a schematic diagram of a circuit structure of an RC oscillator of an RFID tag chip according to an embodiment of the present invention.

Detailed Description

Preferred embodiments of the present apparatus will be described in detail below with reference to the accompanying drawings.

As shown in fig. 1, the output of the reference source circuit is connected to the charging and discharging circuit, and the reference source circuit outputs three signals, which are the bias current Ib and the two mirror currents I1 and I2 thereof, respectively. Ib, I1 and I2 are input into the charge-discharge circuit.

As shown in fig. 1, the charge/discharge circuit has inputs Ib, I1, and I2 connected to the reference source circuit, and an input phase from the switch control circuit. The output of the charge and discharge circuit is connected with the SR latch. As shown in fig. 2, there are 4 switches in the charge and discharge circuit: the S1, S2, S3 and S4, 4 switches are controlled by the phase signal. S1 and S4 are turned on simultaneously, defined as phase-1 state, and S2 and S3 are turned on simultaneously, defined as phase-2 state. When the circuit works in phase-1, Ib is used as a charging current to charge C1, when the voltage of the upper plate of C1 reaches the threshold voltage of NMOS M4, the pull-down circuit is conducted, and due to the strong design of the capacity of the pull-down circuit, after the grid electrode of the pull-down circuit reaches the threshold voltage to form a conductive channel, the voltage of a node n1 is pulled down, and a logic circuit at the later stage recognizes '0'; similarly, when the circuit operating state is switched to phase-2, S1 and S4 are opened, S2 and S3 are closed, Ib starts charging C2, and at the same time, the charge of C1 is rapidly discharged through S2 (the discharge time is much less than the charge time). When the upper plate voltage of C2 is charged to the threshold voltage of NMOS M3, the conducting channel of M3 is formed, the same pull-down capability is stronger than the pull-up of I2, the drain terminal voltage of M3 is pulled down, and node n2 is recognized as '0' by the subsequent logic circuit.

As shown in fig. 1, the switch control circuit has an input of the SR latch and an output of the SR latch as a phase signal, and is connected to the charge/discharge circuit. When the output signal of the SR latch changes, the switch control circuit changes the phase signal output by the SR latch according to the output signal of the SR latch, so that the working state in the charging and discharging circuit is adjusted.

As shown in fig. 1, the input of the SR latch is divided into two paths n1 and n2, which are both connected to the charging and discharging circuit, and the output of the charging and discharging circuit is the output osc _ out of the RC oscillator and the inverted signal osc _ out _ bar thereof, which are connected to the switch control circuit and the output port of the RC oscillator. When the voltage at point n1 is pulled low, which is considered to be a logic '0', the S-R latch is set, and its output osc _ out changes from '0' to '1'; when the voltage at point n2 pulls low, which is considered a logic '0', the S-R latch is set, and its output osc _ out changes from '1' to '0'.

The above embodiments illustrate the working process of the RC oscillator of the RFID tag chip according to the present invention.

Although the present invention has been described in detail with respect to the preferred embodiments, various modifications and alterations will become apparent to those skilled in the art upon reading the foregoing description. The above description and drawings are only examples of the practice of the invention, and it should be understood that the above description should not be taken as limiting the invention.

Claims

1. An RC oscillator circuit for an RFID tag chip, comprising: the circuit comprises a reference source circuit, a charging and discharging circuit, an SR latch and a switch control circuit; the reference source circuit is connected with the charging and discharging circuit and provides currents Ib, I1 and I2 for the charging and discharging circuit, wherein Ib is bias current, and I1 and I2 are mirror currents of Ib; the input end of the charge and discharge circuit is divided into 4 paths, namely bias current Ib, mirror current I1, mirror current I2 and switch control signal phase, wherein three input ends of Ib, I1 and I2 are all connected to a reference source circuit, phase is connected to a switch control circuit, the output ends n1 and n2 of the charge and discharge circuit are connected to an SR latch, the charge and discharge circuit mainly has the function of completing charge and discharge processes under the control of the switch control circuit to generate physical delay, the charge and discharge circuit comprises 4 switches, S1, S2, S3 and S4, capacitors C1 and C2 and two NMOS M3 and M4, the 4 switches are controlled by phase signals, the phase signal is connected to the switch control circuit, the upper electrode plate of the capacitor C2 is connected with the gate end of M3 and S3, the lower electrode plate is grounded, the drain end of M3 is connected with I1, the source end is grounded, the n1 is grounded from the drain end of M3, and the upper electrode plate of the capacitor C1 is led out to the lower electrode plate of the M4 and the gate end of the capacitor C1 9 and the gate, the drain end of M4 is I2, the source end is grounded, n2 is led out from the drain end of M4, Ib is respectively connected with S1 and S3, S1 is connected with S2 in series, S2 is grounded, S3 is connected with S4 in series, and S4 is grounded; the SR latch is connected with the charge-discharge circuit and the switch control circuit; and the switch control circuit is connected with the SR latch and the charging and discharging circuit.