CN211743144U - Semiconductor device with TSV structure - Google Patents

Abstract

A semiconductor component with a through silicon via structure and a manufacturing method thereof are provided, the semiconductor component with the through silicon via structure comprises: a substrate provided with a plurality of holes penetrating through a first surface on the front side and a second surface on the back side; a through electrode disposed in the hole; a lining layer arranged on the inner wall of the hole; a plurality of pads disposed on the first end surface of the through electrode; a first insulating layer disposed on the front side so that a part of the surface of each pad is exposed; the first conductive component covers the exposed welding pad and part of the first insulating layer; a second insulating layer provided on the back surface side, covering the liner layer on the back surface side, and exposing the whole or part of the second end face of each through electrode; and a second conductive member disposed on the second end surface of the through electrode and extending to cover a portion of the second insulating layer.

Description

Semiconductor device with TSV structure

technical field

The utility model relates to a semiconductor packaging technology, in particular to a semiconductor element with a silicon through hole structure.

Background technique

With the rapid and diversified development of the current wafer market demand, the evolution of the integrated circuit (IC) size scaling technology has entered an extremely small scale of tens of nanometers. Therefore, the wafer module must have the requirements of light, thin and short, low cost, low power consumption, high transmission efficiency, high multi-functional hetero-integration (Hetero-integration), and real-time market. Not only the manufacturing technology at the wafer level must be accelerated, but also the packaging technology at the wafer module packaging level will face severe challenges. Since the integration of wafers has become quite complex, packaging technology has also changed with product requirements. Flip chip, which is currently common in high-end products, can solve the problem of wafer packaging with short connections, but it can only perform single-layer wafer packaging, and with the number of transistors and the number of signal pins (I/ O) has increased rapidly, and flip chip bonding packages have gradually been unable to cope with the packaging requirements of bump gaps smaller than 150μm.

Another example is the so-called Multi-chip package (MCP), POP (Package on package), PIP (Package in package) and other types of system-in-package technology (System in package, SIP) for example, the package layout must be Extending from two-dimensional to three-dimensional, greatly increases the difficulty of packaging technology. Therefore, the so-called 3D Integrated Circuits Through Silicon Via (3D IC TSV) technology is the key technology to solve the above problems, which can make the wafer evolve from a two-dimensional planar layout to a three-dimensional vertical stack layout. . It is a three-dimensional interconnection technology using three-dimensional through-silicon vias, which has the advantages of shorter wire interconnection paths, lower resistance and inductance, and more efficient transmission of signals, power and heat.

The main steps of the 3D TSV process are: (1) TSV etching, (2) TSV filling, (3) carrier bonding, (4) wafer thinning, and (5) carrier detachment. Relying on technologies include: TSV forming technology, wafer handling technology, wafer thinning technology, bonding assembly technology, and wafer testing technology. These techniques involve complicated process steps, such as dry etching (dry etching) requiring an etching mask, chemical vapor deposition (CVD) and chemical-mechanical planarization (CMP) requiring expensive raw materials or equipment. ), making it difficult to reduce manufacturing costs. In the steps of TSV etching, carrier bonding, wafer thinning, etc., there is often a risk of processing. If the supporting strength of the wafer is not enough, it is difficult to prevent the cracking of the wafer, resulting in poor yield, and all the The cost of raw materials will remain high.

Utility model content

To solve the above-mentioned problems, the main purpose of the present invention is to provide a semiconductor device with a TSV structure, using the three-dimensional TSV three-dimensional interconnection technology to have shorter wire interconnection paths, lower resistance and inductance, and better performance. Efficiently transmits signals, electricity and heat.

According to an embodiment of the present invention, a semiconductor device having a TSV structure includes: a substrate having a first surface and a second surface opposite to the first surface, and a plurality of holes are disposed through the first surface of the substrate and the second surface; the through electrode is arranged in each hole of the substrate, the through electrode has a first end face and a second end face opposite to the first end face, the first end face is located on one side of the first surface of the substrate, and the first end face is located on one side of the first surface of the substrate. The two end faces are located on one side of the second surface of the substrate; the lining layer is arranged on the inner wall of each hole and extends from one side of the first surface of the substrate to one side of the second surface; a plurality of bonding pads, each The pad corresponds to and covers the first end face of the through electrode and the lining layer located on one side of the first surface of the substrate; the first insulating layer is arranged on the first surface of the substrate, and makes part of each pad The surface is exposed; a plurality of first conductive components cover each exposed pad and part of the first insulating layer; the second insulating layer covers the second surface of the substrate, and a part located on the second surface of the substrate; a side liner; and a plurality of second conductive components covering the second end face of each through electrode and extending over a portion of the second insulating layer.

Another object of the present invention is to provide a method for fabricating a semiconductor device with a TSV structure, so that the area of electrical contact between the conductive device and the through electrode is constructed to be large, and the electrical connection is enhanced.

According to an embodiment of the present invention, a method for fabricating a semiconductor component with a TSV structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to the first surface; forming a plurality of through-holes in the substrate Holes on the first surface and the second surface of the substrate; a lining layer is formed on the inner wall of each hole in the substrate; metal is formed in each hole to form a through electrode, wherein the through electrode has a first end surface and is connected with the first end surface. a second end face opposite to one end face, the first end face is located on one side of the first surface of the substrate, and the second end face is located on one side of the second surface of the substrate; a plurality of bonding pads are formed to cover the first end face of the through electrode; forming a first insulating layer on the first surface of the substrate and exposing part of the surface of each pad; forming a first conductive component on each pad, and each pad is electrically connected to the first conductive component; to the substrate Perform a thinning process relative to one side of the first surface to expose the liner to the second surface of the substrate; form a second insulating layer on the second surface of the substrate; remove part of the second insulating layer and the liner layer to expose the second end surface of the through electrode; and forming a plurality of second conductive components, and each second conductive component covers the second end surface of the through electrode and extends to part of the second insulating layer.

Another object of the present invention is to provide a method for fabricating a semiconductor component with a TSV structure, which is designed to increase the contact area between the conductive component and the TSV structure, so as to enhance the bonding degree and improve product reliability.

According to an embodiment of the present invention, a method for fabricating a semiconductor component with a TSV structure includes: providing a substrate, the substrate having a first surface and a second surface opposite to the first surface; forming a plurality of through-holes in the substrate Holes on the first surface and the second surface of the substrate; a lining layer is formed on the inner wall of each hole in the substrate; metal is formed in each hole to form a through electrode, wherein the through electrode has a first end surface and is connected with the first end surface. a second end face opposite to one end face, the first end face is located on one side of the first surface of the substrate, and the second end face is located on one side of the second surface of the substrate; a plurality of bonding pads are formed to cover the first end face of the through electrode; forming a first insulating layer on the first surface of the substrate and exposing part of the surface of each pad; forming a first conductive component on each pad, and each pad is electrically connected to the first conductive component; to the substrate A thinning process is performed relative to one side of the first surface to make the through electrodes protrude from the second surface of the substrate; a second insulating layer is formed to cover the second surface of the substrate and the protruding through electrodes; two insulating layers and a lining layer to expose the second end surface of the part of the through electrode; and forming a plurality of second conductive elements, and each second conductive element covers the second end surface of the part of the through electrode and extends to the first end surface of the part of the through electrode on the second insulating layer.

The semiconductor device with the TSV structure disclosed in the present invention has good electrical connectivity and electrical insulation; in another embodiment, since the contact area between the second conductive element and the TSV structure is increased, the bonding degree is enhanced And strengthen the support strength of semiconductor components to improve product reliability and avoid high cost of raw materials. In the manufacturing method, the partial removal of the lining layer and the second insulating layer can be completed in the same etching step, which can save time and labor in the manufacturing process.

Description of drawings

FIG. 1 is a side view of a semiconductor device having a TSV structure according to a first embodiment of the present invention.

2A to 2H are side views illustrating a method for fabricating a semiconductor device with a TSV structure according to a first embodiment of the present invention.

3 is a side view of a semiconductor device having a TSV structure according to a second embodiment of the present invention.

4A to 4H are side views illustrating a method for fabricating a semiconductor device with a TSV structure according to a second embodiment of the present invention.

Detailed ways

The structure and fabrication method of the semiconductor device according to the first embodiment and the second embodiment of the present invention are discussed in detail below. It should be appreciated, however, that the illustrated aspects of implementation provide applicable inventive concepts that can be implemented in a wide variety of scenarios. The specific embodiments discussed are merely specific ways to make and use the invention, and do not limit the scope of the invention.

The invention will be described with reference to the illustrated embodiments in a specific context, namely the use of TSV technology to bond one semiconductor element to another semiconductor element, or to bond a semiconductor element to glass. However, the present invention can also be applied to other bonding packaging processes.

First, a semiconductor device with a TSV structure according to a first embodiment of the present invention will be described with reference to FIG. 1 . As shown in FIG. The electrode 101 , the front bump 320 and the back bump 420 electrically connected to the through electrode 101 . The first surface 11 of the substrate 10 is on the front side, and the second surface 12 of the substrate 10 is on the back side corresponding to the front side. The substrate 10 may include a silicon wafer and have front and back sides opposite to each other. The substrate 10 may be a substrate used in the manufacture of semiconductor memory components, semiconductor logic components, optoelectronic components, display units, and the like. The front side may correspond to the side adjacent to the active region in which active components such as field effect transistors, simulated integrated circuits, or passive components such as resistors, capacitors, connectors, etc. are formed, and the back side may correspond to the front side. the opposite side of the side. The front bumps 320 are disposed on the first surface 11 of the substrate 10 , and the back bumps 420 are disposed on the second surface 12 of the substrate 10 opposite to the front bumps 320 .

The hole 100 penetrates through the substrate 10 from the first surface 11 to the second surface 12 . The hole 100 is filled with metal to form the through electrode 101 . The metal of the through electrode 101 may include copper, silver or tin. The TSV structure (not shown) includes a through electrode 101 and a liner 110 surrounding the inner wall of the through electrode 101 . Therefore, the lining layer 110 is disposed between the through electrode 101 and the substrate 10, the material of the lining layer 110 is oxide, preferably silicon dioxide, and the lining layer 110 extends from the front side to the back side of the substrate 10, basically it can be Metal atoms or metal ions in the through electrodes 101 are prevented from diffusing into the substrate 10 .

The through-electrode 101 has a first end face 1011 and a second end face 1012 opposite to the first end face 1011 . back side. The first end surface 1011 of the through electrode 101 can be in contact with the circuit pattern, so that the through electrode 101 is electrically connected to the circuit pattern. In addition, solder pads 200 are disposed on the first end face 1011 of the through electrode 101 , and the plurality of solder pads 200 also cover the liner 110 located on the front side of the substrate 10 , since the first insulating layer 210 covering the circuit pattern is located on the substrate 10 The first surface 11 of the substrate 10 and the pads 200 also located on the first surface 11 of the substrate 10 need to be exposed to be electrically connected to the circuit patterns to be electrically connected to external circuits of the substrate (not shown).

A first insulating layer 210 for covering the circuit pattern is formed on the first surface 11 of the substrate 10 , and the first insulating layer 210 is patterned to expose a part of the surface of each pad 200 . The material of the first insulating layer 210 is preferably a patternable polymer or a photocurable resin, among which polyimide is the most excellent in heat resistance.

For electrical connection with the through electrodes 101 , the front bumps 320 are attached to the exposed part of the surface of the bonding pads 200 . The front bumps 320 include a metal layer 300 (Under Bump Metallurgy, UBM) disposed on the pads 200 , and solder balls 310 disposed on a surface of the metal layer 300 opposite to the pads 200 . The preferred shape of the metal layer 300 is a cylindrical shape, and the metal layer 300 can be formed of at least three layers of conductive materials, such as: a layer of nickel, a layer of tin-silver alloy, and a layer of copper, and an alloy layer can be selected above the copper layer. The top layer is nickel; the solder balls 310 may be formed of at least two layers of conductive material, such as a layer of tin-silver alloy, and a layer of copper, optionally with an alloy layer over the top layer of the copper layer. In one embodiment, once the tin layer has been formed on the metal layer 300, a reflow is preferably performed to form the tin layer into the desired ball-dot shape. In addition, there are other conductive materials well known in the art, such as a titanium/titanium tungsten/copper arrangement, a copper/nickel/gold arrangement, or a copper/chromium copper arrangement, so it is not limited thereto.

Furthermore, on the back side of the substrate 10, a second insulating layer 220 is disposed on the second surface 12 of the substrate 10. The material of the second insulating layer 220 is preferably a polymer with good insulating properties, solvent resistance and heat resistance. Imide, the second insulating layer 220 can be patterned to cover only the lining layer 110 on the backside of the substrate 10 and on the inner wall, so that the second end face 1012 of the through electrode 101 is exposed. And the backside bump 420 covers the entire second end surface 1012 exposed by the through electrode 101, and extends laterally to a part of the second insulating layer 220. The backside bumps 420 can be formed of at least three layers of conductive materials, such as a layer of gold, a layer of nickel, and a layer of copper, optionally with a nickel layer above the copper layer and gold on the top layer; it can also be composed of one or two layers. A layer of conductive material is formed, and the preferred conductive material is copper, nickel, tin, silver, gold or their alloys. The area of the backside bumps 420 in electrical contact with the through electrodes 101 is larger, and the electrical connectivity is stronger. In addition, the backside bumps 420 and the second surface 12 of the substrate 10 are separated by the second insulating layer 220 , and the backside bumps 420 are separated from the inner wall of the TSV structure by the lining layer 110 , which can exert the effect of electrical insulation.

Next, the flow of the manufacturing method of the first embodiment of the present invention will be described with reference to FIGS. 2A to 2H . First, as shown in FIG. 2A, a substrate 10 is provided, and trenching is performed on the substrate 10, preferably by etching or laser drilling to form a plurality of holes 100 through the substrate 10 in the substrate 10. The holes 100 It has a predetermined depth extending from the front side toward the back side. Then, a lining layer 110 is formed on the inner wall of each hole 100 in the substrate 10 by, for example, physical vapor deposition (PVD); and each hole 100 is filled with metal to form through electrodes 101 separated from each other by a predetermined distance, The through electrode 101 has a first end surface 1011 on the front side of the substrate 10 and a second end surface 1012 on the back side of the substrate 10 . Then, a plurality of bonding pads 200 are formed on each through electrode 101 by sputtering or electroplating to cover the first end surface 1011 of the through electrode 101 , and the bonding pads 200 do not cover the entire first surface 11 of the substrate 10 . The material of the pad 200 is preferably aluminum.

Next, as shown in FIG. 2B , polyimide is coated on the first surface 11 of the substrate 10 , and the polyimide is cured by light or heating to form a first insulating layer 210 on the first surface 11 of the substrate 10 . . Next, etching is performed on the first insulating layer 210 to form a patterned first insulating layer 210 to expose a part of the surface of each pad 200 .

Next, as shown in FIG. 2C , forming front bumps 320 on each pad 200 includes firstly forming a metal layer 300 on each pad 200 by, for example, plasma enhanced chemical vapor deposition (PECVD), and then using sputtering Solder balls 310 are formed on the cylindrical metal layer 300 by means of plating, electroplating, printing, solder migration, or ball mounting, and a reflow method is used to form the solder balls 310 into a desired ball shape. The metal layer 300 is stacked on each pad 200 and covers part of the first insulating layer 210 , so that the front bumps 320 are electrically connected to the through electrodes 101 through the pads 200 .

Next, as shown in FIG. 2D , the substrate 10 is turned over with the back side up to perform thinning on the back side of the substrate 10 , preferably by grinding the back side of the substrate 10 with a grinding roller 400 until the liner 110 is Grinding is stopped when the second surface 12 of the substrate 10 is exposed.

Next, as shown in FIG. 2E , polyimide is coated on the second surface 12 of the substrate 10 , and the polyimide is cured by light or heating, so as to form a second insulation on the second surface 12 of the substrate 10 Layer 220.

Next, as shown in FIGS. 2F and 2G , the second insulating layer 220 is etched by using a dry etching method such as plasma bombardment and the etching mask 500 , corresponding to the second insulating layer 220 above the second end surface 1012 of the through electrode 101 . The lining layer 110 is removed because it is not covered by the etching mask 500 to form a patterned second insulating layer 220 , so that the second end surface 1012 of the through electrode 101 is exposed.

Next, as shown in FIG. 2H , backside bumps 420 are formed on the backside of the substrate 10 corresponding to the second end faces 1012 of the through electrodes 101 by means of sputtering, electroplating, printing, solder migration, or ball mounting. The backside bumps 420 are stacked on the second end surface 1012 of each through-electrode 101 and extend to cover part of the second insulating layer 220 , so that the backside bumps 420 are electrically connected to the through-electrodes 101 .

Next, a semiconductor device with a TSV structure according to a second embodiment of the present invention will be described with reference to FIG. 3. As shown in FIG. 3 and in conjunction with FIG. The first embodiment is the same and will not be repeated here. The difference is that on the backside of the substrate 10 , the second end face 1012 of the through electrode 101 , and a portion of the liner 110 surrounding the second end face 1012 of the through electrode 101 protrude from the second surface 12 of the substrate 10 . That is, if the second end surface 1012 of the through electrode 101 is higher than the second surface 12 of the substrate 10, the TSV structure protrudes above the second surface 12 of the substrate 10.

The second insulating layer 220 is disposed on the second surface 12 of the substrate 10 and covers one end of the protruding TSV structure. The second insulating layer 220 can be patterned to cover the lining layer 110 on the inner wall and part of the lining layer 110 on the second end surface 1012 of the through electrode 101 , so that part of the second end surface 1012 of the through electrode 101 is exposed. In detail, the second insulating layer 220 covers one end of the protruding TSV structure, including the liner 110 protruding from the second surface 12 of the substrate 10 and the liner disposed on the second end surface 1012 of the through electrode 101 part layer 110 , but does not extend beyond the liner layer 110 to cover the entire second end face 1012 of the through-electrode 101 .

The backside bumps 420 cover the exposed part of the second end surface 1012 of the through electrode 101 , are in contact with part of the liner 110 on the second end surface 1012 of the through electrode 101 , and extend laterally to part of the second insulating layer 220 . In detail, the backside bumps 420 are sequentially stacked on a part of the second end surface 1012 of the through electrode 101 and a part of the second insulating layer 220 surrounding the liner 110 , and are located on the second end surface 1012 of the through electrode 101 . part of the liner 110 and the sidewall of the second insulating layer 220 are in contact. In the second embodiment, the backside bump 420 covers one end of the protruding TSV structure, and the backside bump 420 extends laterally from the inner wall of the protruding TSV structure and covers part of the second insulating layer 220 . Compared with the backside bumps 420 that only contact the second end face 1012 of the through electrode 101 (ie, the first embodiment), the second embodiment has better electrical connectivity and electrical insulation. The increased contact area of the TSV structure enhances the bonding and improves product reliability.

Next, the flow of the manufacturing method of the second embodiment of the present invention will be described with reference to FIGS. 4A to 4H . First, as shown in FIG. 4A, a substrate 10 is provided, and trenching is performed on the substrate 10, preferably by etching or laser drilling to form a plurality of holes 100 through the substrate 10 in the substrate 10. The holes 100 It has a predetermined depth extending from the front side toward the back side. Then, a lining layer 110 is formed on the inner wall of each hole 100 in the substrate 10 by, for example, physical vapor deposition; 101 has a first end surface 1011 on the front side of the substrate 10 and a second end surface 1012 on the back side of the substrate 10 . Then, a plurality of bonding pads 200 are formed on each through electrode 101 by sputtering or electroplating to cover the first end surface 1011 of the through electrode 101 , but the bonding pads 200 do not cover the entire first surface 11 of the substrate 10 . The material of the pad 200 is preferably aluminum.

Next, as shown in FIG. 4B , polyimide is coated on the first surface 11 of the substrate 10 , and the polyimide is cured by irradiation or heating to form a first insulating layer 210 on the first surface 11 of the substrate 10 . . Etching is then performed on the first insulating layer 210 to form a patterned first insulating layer 210 exposing a portion of the surface of each pad 200 .

Next, as shown in FIG. 4C , forming front bumps 320 on each pad 200 includes firstly forming a metal layer 300 on each pad 200 by, for example, plasma enhanced chemical vapor deposition, and then using sputtering, electroplating Solder balls 310 are formed on the cylindrical metal layer 300 by methods such as , printing, solder migration, or ball mounting, and a reflow method is used to make the solder balls 310 form a desired ball point shape. The metal layer 300 is stacked on each pad 200 and covers part of the first insulating layer 210 , so that the front bumps 320 are electrically connected to the through electrodes 101 through the pads 200 .

Next, as shown in FIG. 4D , the substrate 10 is turned over with the back side facing upward to perform thinning on the back side of the substrate 10 , preferably the back side of the substrate 10 is ground with a grinding roller 400 so that the back side of the substrate 10 is ground. The second surface 12 is recessed inward, and grinding is stopped until the TSV structure (including the liner 110 and the through electrode 101 ) protrudes from the second surface 12 of the substrate 10 by a predetermined height.

Next, as shown in FIG. 4E , polyimide is coated on the back side of the substrate 10 , and the polyimide is hardened by light or heating to form a second insulating layer 220 on the second surface 12 of the substrate 10 . The second insulating layer 220 covers one end of the protruding TSV structure and the recessed second surface 12 of the substrate 10.

Next, as shown in FIGS. 4F and 4G , the second insulating layer 220 is etched using a dry etching method such as plasma bombardment and the etching mask 500 , corresponding to the second insulating layer 220 above the second end surface 1012 of the through electrode 101 . The lining layer 110 is removed because it is not covered by the etching mask 500 to form a patterned second insulating layer 220, so that part of the second end surface 1012 of the through electrode 101 is exposed, and the second end surface 1012 of the through electrode 101 is exposed. The other part is still covered with the second insulating layer 220 and the lining layer 110 . In detail, the patterned second insulating layer 220 covers one end of the protruding TSV structure, including the lining layer 110 protruding from the second surface 12 of the substrate 10 and the second end surface 1012 disposed on the through electrode 101 part The lining layer 110 on top, but not extending beyond the lining layer 110 to cover the entire second end face 1012 of the through electrode 101 .

Next, as shown in FIG. 4G , backside bumps 420 are formed on the backside of the substrate 10 corresponding to the second end faces 1012 of the through electrodes 101 by means of sputtering, electroplating, printing, solder migration, or ball mounting. The backside bumps 420 are stacked on the second end surface 1012 of each through-electrode 101 and extend to cover part of the second insulating layer 220 , so that the backside bumps 420 are electrically connected to the through-electrodes 101 .

The above descriptions are only the preferred embodiments of the present invention, and are not intended to limit the scope of the rights of the present invention; meanwhile, the above descriptions should be understood by those with ordinary knowledge in the relevant technical field and implemented accordingly, so others do not depart from Equivalent changes or modifications accomplished under the concepts disclosed in the present invention should all be included in the scope of the patent application.

Claims (10)

1. A semiconductor device having a through-silicon-via structure, comprising:

the device comprises a substrate, a first electrode and a second electrode, wherein the substrate is provided with a first surface and a second surface opposite to the first surface, and a plurality of holes penetrate through the first surface and the second surface of the substrate;

a through electrode disposed in each of the holes of the substrate, the through electrode having a first end surface and a second end surface opposite to the first end surface, the first end surface being located at one side of the first surface of the substrate, the second end surface being located at one side of the second surface of the substrate;

a lining layer disposed on an inner wall of each of the holes, extending from the side of the first surface to the side of the second surface of the substrate;

a plurality of pads, each pad corresponding to and covering the first end surface of the through electrode and the lining layer on the side of the first surface of the substrate;

the first insulating layer is arranged on the first surface of the substrate and exposes part of the surface of each welding pad;

a plurality of first conductive elements covering each of the exposed pads and a portion of the first insulating layer;

a second insulating layer covering the second surface of the substrate and the liner layer on the side of the second surface of the substrate; and

a plurality of second conductive elements covering the second end surface of each of the through electrodes and extending onto a portion of the second insulating layer.

2. The semiconductor component with a through-silicon-via structure of claim 1, wherein the liner layer covers the second end face of the portion of the through-electrode.

3. The semiconductor component with a through-silicon-via structure of claim 1, wherein the second end face of the through-electrode is higher than the second surface of the substrate.

4. The semiconductor device of claim 1, wherein the liner is an oxide.

5. The semiconductor device of claim 1, wherein the through-silicon-via is copper.

6. The semiconductor device according to claim 1, wherein the first insulating layer and the second insulating layer are polyimide.

7. The semiconductor device of claim 1, wherein the first conductive element comprises a metal layer and a solder ball, the metal layer is correspondingly disposed on the pad, and the solder ball is disposed on a surface of the metal layer opposite to the pad.

8. The semiconductor assembly with the through silicon via structure of claim 7, wherein the solder ball, the metal layer are copper, nickel, tin, silver, titanium, tungsten, chromium or alloys thereof.

9. The semiconductor assembly with a through silicon via structure of claim 7, wherein the metal layer is cylindrical in shape.

10. The semiconductor device of claim 1, wherein the second conductive element is copper, nickel, tin, silver, gold, or alloys thereof.

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