CN211719590U - Communication interface and packaging structure - Google Patents
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- CN211719590U CN211719590U CN202020141076.7U CN202020141076U CN211719590U CN 211719590 U CN211719590 U CN 211719590U CN 202020141076 U CN202020141076 U CN 202020141076U CN 211719590 U CN211719590 U CN 211719590U
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Abstract
An embodiment of the utility model provides a communication interface and packaging structure, include: the first interface is connected with the first semiconductor unit, the second interface is connected with the second semiconductor unit, the first interface is matched and connected with the second interface, and a plurality of transmission channels are formed between the first semiconductor unit and the second semiconductor unit; in one clock cycle of the communication interface, M transmission channels in the plurality of transmission channels are multiplexed to transmit interconnection signals of multiple types between the first semiconductor unit and the second semiconductor unit, wherein M is an integer greater than 8. By adopting the scheme, the multiplexing rate of the transmission channel is balanced while the transmission channel is multiplexed, so that the requirement of a communication interface on the working frequency is reduced, and the power consumption is further reduced.
Description
Technical Field
The utility model relates to the field of semiconductor technology, in particular to communication interface and packaging structure.
Background
At present, when two chips need to be interconnected and communicated, chip pin processing modules (IO PADs) on the two chips are connected through metal wires in a routing manner, so that the interconnection and communication between the two chips are realized. For chip interconnection of multiple IO PADs, corresponding IO PADs can be set for various signals to realize interconnection communication between two chips.
SUMMERY OF THE UTILITY MODEL
An object of the embodiment of the utility model is to provide a communication interface and packaging structure to in multiplexing transmission channel, transmission channel's reuse rate has been balanced, thereby has reduced communication interface to operating frequency's requirement, and then has reduced the consumption.
An embodiment of the utility model provides a communication interface, include: the first interface is connected with the first semiconductor unit, the second interface is connected with the second semiconductor unit, the first interface is matched and connected with the second interface, and a plurality of transmission channels are formed between the first semiconductor unit and the second semiconductor unit; in one clock cycle of the communication interface, M transmission channels in the plurality of transmission channels are multiplexed to transmit multiple types of interconnection signals between the first semiconductor unit and the second semiconductor unit, wherein M is an integer greater than 8.
An embodiment of the utility model provides a packaging structure, include: the communication interface, the first semiconductor unit and the second semiconductor unit are provided.
The embodiment of the utility model provides a now to prior art, a communication interface is provided, this communication interface is including connecting in the first interface of first semiconductor unit, and connect in the second interface of second semiconductor unit, first interface and second interface phase-match and be connected, and form many transmission channel between first semiconductor unit and second semiconductor unit, in a clock cycle of communication interface, M transmission channel among many transmission channel is multiplexed and transmits polytype interconnection signal between first semiconductor unit and second semiconductor unit, the quantity M that sets up the transmission channel that is multiplexed is greater than 8, in order to multiplex transmission channel, transmission channel's reuse rate has been balanced, thereby communication interface to operating frequency's requirement has been reduced, and then the consumption has been reduced.
For example, the first interface and the second interface have the same structure; each interface comprises a logic control unit, a register unit and a driving unit which are connected with each other; the driving unit of the first interface is connected with the driving unit of the second interface to form a plurality of transmission channels; the logic control unit is used for acquiring the interconnection signal to be transmitted from the register unit and outputting the interconnection signal to be transmitted through the driving unit; the logic control unit is also used for storing the interconnection signals received by the driving unit into the register unit. The embodiment provides a specific structure of the first interface and the second interface.
For example, the register unit includes: an input state register, an input address register, an input data register and an output data register; the logic control unit is used for judging whether the interface is in an output state or not according to the flag bit in the input state register; the logic control unit is used for acquiring the interconnection signal to be transmitted from the output data register when the interface to which the logic control unit belongs is judged to be in the output state, and outputting the interconnection signal to be transmitted through the driving unit; the logic control unit is used for controlling the driving unit to be in a receiving state when the interface to which the logic control unit belongs is judged to be in an input state, and receiving the interconnection signal through the driving unit; the logic control unit is used for storing the received interconnection signals into the input data register according to the address information in the input address register. The present embodiment provides a specific structure of the register unit.
For example, each drive unit forms a plurality of pins on the associated interface; a plurality of pins of the first interface and a plurality of pins of the second interface are in one-to-one correspondence and are connected to form a plurality of transmission channels; the plurality of pins comprise M data pins; the multiplexed transmission channel is a transmission channel formed between a data pin of the first interface and a data pin of the second interface. The present embodiment provides a specific implementation of the multiplexed transmission channels.
For example, the first interface and the second interface use the same operating frequency, and the operating frequency is the internal clock frequency of the first semiconductor unit or the internal clock frequency of the second semiconductor unit. In the embodiment, both transmission speed and power consumption are considered, and low power consumption is realized while higher transmission speed is realized.
For example, M is greater than or equal to the bit width of any of the plurality of types of interconnect signals.
For example, M is equal to the largest of the bit widths of the various types of interconnect signals.
For example, the plurality of transmission channels includes a transmission channel for transmitting a power supply signal, and the transmission channel for transmitting the power supply signal does not overlap with the M transmission channels.
For example, various types of interconnect signals include: operation instructions, address signals, and data signals.
For example, various types of interconnect signals also include: communicating the handshake signals.
For example, the first semiconductor unit includes a first chip, and the second semiconductor unit includes a second chip.
For example, the first chip and the second chip are a main control chip and a memory chip, respectively.
For example, the parasitic capacitance between any two transmission channels is smaller than a preset capacitance threshold. In this embodiment, power consumption is effectively reduced, a signal transmission speed is increased, and high-speed transmission with low power consumption between the first semiconductor unit and the second semiconductor unit is realized.
For example, the first interface and the second interface have the same structure; each interface comprises a logic control unit, a register unit and a driving unit which are connected with each other, and each driving unit forms a plurality of pins on the corresponding interface; a plurality of pins of the first interface and a plurality of pins of the second interface are in one-to-one correspondence and are connected to form a plurality of transmission channels; and connecting the plurality of pins of the first interface and the plurality of pins of the second interface in a flip-chip packaging mode to form a plurality of transmission channels. The embodiment provides a specific packaging manner for making the parasitic capacitance between any two transmission channels smaller than a preset capacitance threshold value.
For example, the first semiconductor unit and the second semiconductor unit are both located on the third semiconductor unit, and the communication interface is located on the third semiconductor unit; and the first interface and the second interface in the communication interfaces are connected through the wiring on the third semiconductor unit. In this embodiment, the first interface and the second interface are connected with each other through a plurality of wires on the third semiconductor unit, so that the first semiconductor unit and the second semiconductor unit realize interconnection communication through a plurality of transmission channels formed by the plurality of wires, the area of the wires inside the third semiconductor unit is reduced, and then the interference between the wires is also reduced.
For example, the third semiconductor unit is a chip, and the first semiconductor unit and the second semiconductor unit are two different modules on the third semiconductor unit.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic diagram of a communication interface according to a first embodiment of the present invention;
fig. 2 is a schematic diagram of communication interfaces in a second embodiment according to the present invention, wherein each interface comprises a logic control unit, a register unit, and a driving unit connected to each other;
fig. 3 is a schematic diagram of a communication interface according to a second embodiment of the present invention, in which the register unit includes an input status register, an input address register, an input data register, and an output data register;
fig. 4 is a schematic diagram of a communication interface according to a second embodiment of the present invention, wherein the plurality of pins includes: a VDD pin, a VCC pin, a VSS pin, M data pins, a CLK pin, a TX pin and an RX pin;
fig. 5 is a schematic diagram of a communication interface according to a second embodiment of the present invention, wherein a plurality of pins includes: a VDD pin, a VCC pin, a VSS pin, M data pins and a CLK pin;
fig. 6 is a timing diagram of reading and writing data between a first semiconductor cell and a second semiconductor cell in a second embodiment according to the present invention;
fig. 7 is a schematic diagram of a package structure according to a fourth embodiment of the present invention.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
In order to make the objects, technical solutions and advantages of the present invention more clearly understood, some embodiments of the present invention will be described in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The inventor finds that the prior art has at least the following problems: for chip interconnection of multiple IO PADs, the parasitic capacitance generated between the IO PAD to ground and the IO PAD is high, which results in too high power consumption.
The first embodiment of the present invention relates to a communication interface for connecting a first semiconductor unit and a second semiconductor unit. In this embodiment, referring to fig. 1, the communication interface includes: the first interface 11 is connected to the first semiconductor unit 2, and the second interface 12 is connected to the second semiconductor unit 3, the first interface 11 is matched and connected with the second interface 12, and a plurality of transmission channels 4 are formed between the first semiconductor unit 2 and the second semiconductor unit 3, that is, a plurality of connection lines between the first interface 11 and the second interface 12 form a plurality of transmission channels 4.
In this embodiment, M transmission channels 4 of the plurality of transmission channels 4 are multiplexed between the first semiconductor unit and the second semiconductor unit to transmit a plurality of types of interconnection signals in one clock cycle of the communication interface, where M is an integer greater than 8; wherein the types of the multiplexed transmission channels are the same.
In one example, the first interface 11 and the second interface 12 use the same operating frequency, which is the internal clock frequency of the first semiconductor unit 2 or the internal clock frequency of the second semiconductor unit 3, that is, when the first semiconductor unit 2 is the master device, the operating frequency is the internal clock frequency of the first semiconductor unit 2; when the second semiconductor unit 3 is the master device, the operating frequency is the internal clock frequency of the second semiconductor unit 3, and at this time, both the transmission speed and the power consumption of the communication interface can be considered, so that a higher transmission speed is realized, and at the same time, low power consumption is realized.
Compared with the prior art, the embodiment provides a communication interface, which includes a first interface connected to a first semiconductor unit and a second interface connected to a second semiconductor unit, where the first interface is matched and connected with the second interface, and multiple transmission channels are formed between the first semiconductor unit and the second semiconductor unit, M transmission channels of the multiple transmission channels are multiplexed between the first semiconductor unit and the second semiconductor unit to transmit multiple types of interconnection signals in one clock cycle of the communication interface, and the number M of the multiplexed transmission channels is set to be greater than 8, so that while the transmission channels are multiplexed, the multiplexing rate of the transmission channels is balanced, thereby reducing the requirement of the communication interface on the operating frequency, and further reducing the power consumption.
The second embodiment of the present invention relates to a communication interface, and the present embodiment is mainly different from the first embodiment in that: a specific structure of the first interface 11 and the second interface 12 is provided.
In this embodiment, referring to fig. 2, the first interface 11 and the second interface 12 have the same structure; each interface includes a logic control unit 111, a register unit 112 and a driving unit 113 connected to each other, and the driving unit 113 of the first interface 11 is connected to the driving unit 113 of the second interface 12 to form a plurality of transmission channels 4. The first interface 11 is an interface formed inside the first semiconductor unit 2, and the second interface 12 is an interface formed inside the second semiconductor unit 3.
The logic control unit 111 is configured to obtain the interconnection signal to be transmitted from the register unit 112, and output the interconnection signal to be transmitted through the driving unit 113.
The logic control unit 111 is also used to store the interconnect signals received through the driving unit 113 into the register unit 112.
In one example, referring to fig. 3, the register unit 112 includes: input status register 1121, input address register 1122, input data register 1123, output data register 1124. The input status register 1121, the input address register 1122, the input data register 1123, and the output data register 1124 may be at least partially multiplexed to reduce the area occupied by the register unit 112.
The logic control unit 111 is configured to determine whether the interface is in an output state according to the flag bit in the input status register 1121.
The logic control unit 111 is configured to obtain the interconnect signal to be transmitted from the output data register 1124 when determining that the interface to which the logic control unit belongs is in the output state, and output the interconnect signal to be transmitted through the driving unit 113.
The logic control unit 111 is configured to control the driving unit 113 to be in a receiving state when determining that the interface is in the input state, and receive the interconnection signal through the driving unit.
The logic control unit 11 is configured to store the received interconnect signal in the input data register 1123 according to the address information in the input address register 1122.
In this embodiment, each driving unit 113 forms a plurality of pins on the corresponding interface, that is, each driving unit 113 forms a plurality of pins on the corresponding interface; the plurality of pins of the first interface 11 and the plurality of pins of the second interface 12 are in one-to-one correspondence and connected to form a plurality of transmission channels 4. The driving unit 113 may include a plurality of buffer buffers, each buffer corresponds to one transmission channel 4, each buffer is configured to complete driving of the corresponding transmission channel 4, and the working state of each buffer includes an output high level, an output low level, and a high impedance.
In this embodiment, the types of the pins are defined in the first interface 11 and the second interface 12, and the types of the two connected pins determine the type of the transmission channel formed.
In one example, referring to fig. 4, the plurality of pins of each interface includes a VDD pin, a VCC pin, a VSS pin, M data pins, a CLK pin, a TX pin, and an RX pin. A transmission channel 4 formed by connecting a VDD pin of the first interface 11 and a VDD pin of the second interface is a VDD channel and is used for transmitting a VDD signal; a transmission channel 4 formed by connecting the VCC pin of the first interface 11 and the VCC pin of the second interface is a VCC channel and is used for transmitting a VCC signal; a transmission channel 4 formed by connecting a VSS pin of the first interface 11 with a VSS pin of the second interface is a VSS channel so as to realize grounding; a transmission channel 4 formed by connecting a data pin of the first interface 11 with a data pin of the second interface is a data channel and is used for transmitting various types of interconnection signals; the transmission channel 4 formed by connecting the CLK pin of the first interface 11 and the CLK pin of the second interface is a CLK channel and is used for transmitting clock signals; a transmission channel 4 formed by connecting a TX pin of the first interface 11 and a TX pin of the second interface is a TX channel and is used for transmitting an output control signal (TX signal); the transmission channel 4 formed by connecting the RX pin of the first interface 11 and the RX pin of the second interface is an RX channel for transmitting an input control signal (RX signal).
VCC is a power supply voltage, VDD is a working voltage (generally VCC > VDD), VSS is a ground, a VDD signal, a VCC signal, and a VSS signal may be collectively referred to as a power supply signal, and thus a VDD channel, a VCC channel, and a VSS channel may be collectively referred to as a transmission channel for transmitting a power supply signal. VCC supplies power to the logic control unit 101 and the register unit in the first interface 11, and simultaneously supplies power to the logic control unit 101 and the register unit in the second interface 12 through the VCC interface, VDD supplies power to the driving unit 113 in the first interface 11, and simultaneously supplies power to the driving unit 113 in the second module 12 through the VDD pin.
In fig. 4, M data pins in two interfaces (a first interface 11 and a second interface 12) are respectively connected to form M data channels (a data channel 1 to a data channel M), the M data channels are multiplexed between the first semiconductor unit 2 and the second semiconductor unit 3 to transmit a plurality of types of interconnection signals in a time-sharing manner, and the plurality of types of interconnection signals include an operation instruction, an address signal and a data signal.
In one example, referring to fig. 5, the plurality of pins of each interface includes a VDD pin, a VCC pin, a VSS pin, M data pins, and a CLK pin. The connection mode of the pins and the signal types transmitted by the channels in fig. 3 are the same as those in fig. 2, and are not described herein again, but the main differences are as follows: in this embodiment, an RX pin dedicated to transmit an input control signal (RX signal) and a TX pin used to transmit an output control signal (TX signal) in two interfaces (the first interface 11 and the second interface 12) are eliminated, and at this time, when M data channels formed by connecting M data pins in the two interfaces (the first interface 11 and the second interface 12) are used to transmit multiple types of interconnection signals in a time-sharing manner, a communication handshake signal including the TX signal and the RX signal may be added to the multiple types of interconnection signals, so that the total number of pins in the communication interface is further reduced, and power consumption may be further reduced.
In this embodiment, in one clock cycle, the first semiconductor unit 2 and the second semiconductor unit 3 can complete at least one read/write operation, and the communication interface shown in fig. 4 is taken as an example to explain that the first semiconductor unit 2 reads data from the second semiconductor unit 3, and fig. 6 is a timing chart of data reading and data writing of the first semiconductor unit 2 and the second semiconductor unit 3.
In the first stage, the TX signal is at a high level, the RX signal is at a low level, the first interface 11 of the first semiconductor unit 2 is in a sending state, the first semiconductor unit 2 sends a read command and a read address to the second semiconductor unit 3 through M data channels, that is, the logic control unit 111 controls the buffer of each data pin to output a high level or a low level signal through the corresponding data channel according to the binary coding of the read command and the read address; at this time, the second interface 12 of the second semiconductor unit 3 is in a receiving state, and the buffer of each data pin is in a high impedance state, so that the read command and the read address can be received.
In the second stage, the TX signal is at a low level, the RX signal is at a high level, the first semiconductor unit 2 needs to be switched to the receiving state after sending the read command and reading the address through the M data channels, and the logic control unit 111 in the first interface 11 switches the buffers of the data pins to the high impedance state to receive the data signals sent by the second semiconductor unit 3 through the M data channels. At this time, the second interface 12 of the first semiconductor unit 2 is in a transmitting state, and the logic control unit 111 of the second interface 12 controls the buffer of each data pin to output a high level or low level signal through the corresponding data channel according to the binary coding of the data signal, so as to transmit the data signal to the first semiconductor unit 2 through the M data channels.
In this embodiment, M is greater than or equal to the bit width of any type of interconnect signal, and in one example, M may be set to be equal to the largest bit width among the bit widths of multiple types of interconnect signals; specifically, for example, taking various types of interconnect signals including an operation instruction, an address signal, and a data signal, among the three types of signals, if the bit width of the data signal is the largest, the number of data channels may be set to be equal to the bit width of the data signal, for example, for a 32-bit data signal, each interface includes 32 data pins, 32 data channels multiplexed for transmitting various types of interconnect signals may be formed between the first semiconductor unit 2 and the second semiconductor unit 3, in addition, pins for transmitting a TX signal, an RX signal, a VDD signal, a CLK signal, a VCC signal, and a VSS signal should be included between the first semiconductor unit 2 and the second semiconductor unit 3, and at this time, 38 transmission channels are formed between the first semiconductor unit 2 and the second semiconductor unit 3.
Compared with the first embodiment, the present embodiment provides a specific structure of the first interface and the second interface.
A third embodiment of the present invention relates to a package structure, please refer to fig. 1 to 5, wherein the package structure includes a communication interface, a first semiconductor unit 2 and a second semiconductor unit 3 in the first embodiment or the second embodiment.
In the present embodiment, the first semiconductor unit 2 includes a first chip, and the second semiconductor unit 3 includes a second chip; the first interface 11 is located on the first semiconductor unit 2, and the second interface 12 is located on the second semiconductor unit 3, that is, the first interface 11 and the second interface 12 are respectively located on two different chips, so as to implement communication interconnection between the two chips, and multiplex M transmission channels in multiple transmission channels between the two chips to transmit multiple types of interconnection signals.
In another example, the first semiconductor unit 2 may be a first chip and the second semiconductor unit 3 may be a second chip.
For example, the first chip may be a microprocessor main control chip or a memory chip, and the second chip may be a microprocessor main control chip or a memory chip.
In this embodiment, the first semiconductor unit 2 is taken as a microprocessor main control chip, the second semiconductor unit 3 is taken as a Memory chip, that is, an External Memory chip of the microprocessor main control chip is taken as an example, at this time, the communication interface may be referred to as an MCU External Memory Physical interface (MEMPHY interface for short), the MEMPHY interface includes a MEMPHYMaster (first interface) connected to the microprocessor main control chip and a MEMPHYSlave (second interface) connected to the Memory chip, a plurality of transmission channels are formed between the MEMPHYMaster and the MEMPHYSlave, that is, a plurality of connection lines between the MEMPHYMaster and the MEMPHYSlave form a plurality of transmission channels. The second semiconductor unit 3 may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a FLASH memory (FLASH ROM), a static memory (SRAM), a dynamic memory (DRAM), or the like.
It should be noted that, if the first semiconductor unit 2 is a microprocessor main control chip and the second semiconductor unit 3 is a memory chip, after the two are packaged together, data can be written into the microprocessor main control chip through the memory chip to adjust parameters of the microprocessor main control chip, which is called Trimming. In the Trimming process, the interconnection between the memory chips of different processes and the same microprocessing main control chip or the interconnection between the same memory chip and the microprocessing main control chips of different processes can be realized through the configuration of Trimming information in the memory chips and the time sequence configuration of interconnection signals between the microprocessing main control chips and the memory chips.
The present embodiment and the following embodiments all include various types of interconnect signals: the operation instruction, the address signal and the data signal are transmitted in time-sharing mode, that is, for M transmission channels multiplexed in the MEMPHY interface, the M transmission channels may be used to transmit the operation instruction, the address signal and the data signal in time-sharing mode.
In this embodiment, the power signal, the operation instruction, the address signal, the data signal, the clock signal, the input control signal, and the output control signal of the memory chip (the second semiconductor unit 3) are all from the microprocessor main control chip (the first semiconductor unit 2), and the microprocessor main control chip can realize read-write, sleep, and other test operations on the memory chip through the MEMPHY interface. The clock signal can select the clock frequency of the main clock in the microprocessing main control chip, and no additional clock source is needed to be set, so that the cost is reduced.
It should be noted that, in this embodiment, multiplexing of the MEMPHY interfaces may be implemented by selecting the memory chips of the same type, that is, the microprocessor main control chip may be connected to a plurality of memory chips through one MEMPHY interface.
In one example, the parasitic capacitance between any two transmission channels in the plurality of transmission channels in the MEMPHY interface is less than a predetermined capacitance threshold. That is, the parasitic capacitance generated by any two of the multiple connection lines between the MEMPHYMaster and the MEMPHYSlave in the memphyy interface is smaller than the preset capacitance threshold, and the parasitic capacitance includes the capacitance of the connection line to the ground and the adjacent wiring, thereby effectively reducing the power consumption and improving the signal transmission speed, realizing the high-speed transmission with low power consumption between two chips, and enabling the externally-hung stored chip to realize the performance of an Embedded Flash memory (Embedded Flash), therefore, the processing technology of the Embedded Flash memory wafer can be replaced by using the packaging structure, thereby being beneficial to reducing the cost, and the chip design scheme of the packaging structure is more flexible and standardized according to the storage requirements of different capacities.
In this embodiment, the MEMPHYMaster and the MEMPHYSlave have the same structure; each interface (MEMPHYMaster or MEMPHYSlave) comprises a logic control unit, a register unit and a driving unit which are connected with each other, and each driving unit forms a plurality of pins on the corresponding interface; the pins of the first interface are in one-to-one correspondence with and connected with the pins of the second interface to form a plurality of transmission channels.
In one example, the first semiconductor unit 2 and the second semiconductor unit 3 may be Flip-Chip (FC) packaged by using a Flip-Chip technology to connect a plurality of pins of the MEMPHYMaster and a plurality of pins of the MEMPHYSlave in the memphyy interface, so that a circuit connection path between the MEMPHYMaster and the MEMPHYSlave is effectively shortened, and a parasitic capacitance between any two transmission channels of the MEMPHYMaster and the MEMPHYSlave is smaller than a preset capacitance threshold. After FC packaging is adopted, except for power supply signals (including VDD, VCC and VSS), other signals can not be directly led out to packaged pins, so that the total number of packaged pins is reduced.
Compared with the first embodiment, the present embodiment provides a package structure to which the communication interface in the first embodiment or the second embodiment is applied; the number of transmission channels is reduced in the communication interface, so that the wiring area of the packaging structure is reduced, the size of the packaging structure is favorably reduced, and the cost is reduced; also, high-speed transmission with low power consumption between the first semiconductor unit and the second semiconductor unit is realized.
The fourth embodiment of the present invention relates to a package structure, and the present embodiment is mainly different from the first embodiment in that: a specific implementation of the interconnection communication between modules of the same semiconductor unit is provided.
Referring to fig. 6 (taking the communication interface in fig. 1 as an example), the first semiconductor unit 2 and the second semiconductor unit 3 are both located on the third semiconductor unit 4, and the communication interface is located on the third semiconductor unit 4; the first interface 11 and the second interface 12 are connected to each other by a plurality of metal lines on the third semiconductor unit 4, which form a plurality of transmission channels between the first interface 11 and the second interface 12.
In this embodiment, the third semiconductor unit 4 includes one chip or one wafer (the wafer includes a plurality of chips), and taking the third semiconductor unit 4 as one chip as an example, the first semiconductor unit 2 and the second semiconductor unit 3 are two modules in the chip, for example, the first semiconductor unit 2 is an analog signal module, the second semiconductor unit 3 is a digital signal module, the analog signal module is connected to the first interface 11 through a trace in the chip, the digital signal module is connected to the second interface 12 through a trace in the chip, and the first interface 11 and the second interface 12 are connected to each other through a plurality of traces in the chip, so that the two modules realize interconnection communication through a plurality of transmission channels formed by the plurality of traces, thereby reducing the area of the traces in the chip and further reducing the interference between the traces.
Compared with the third embodiment, the present embodiment provides a specific implementation manner for implementing interconnection communication between modules of the same semiconductor unit; the wiring area in the third semiconductor unit is reduced, so that the packaging volume of the third semiconductor unit is reduced.
It will be understood by those skilled in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention in practice.
Claims (16)
1. A communication interface, comprising: the first interface is connected with the first semiconductor unit, the second interface is connected with the second semiconductor unit, the first interface is matched and connected with the second interface, and a plurality of transmission channels are formed between the first semiconductor unit and the second semiconductor unit;
in one clock cycle of the communication interface, M transmission channels in the plurality of transmission channels are multiplexed to transmit interconnection signals of multiple types between the first semiconductor unit and the second semiconductor unit, wherein M is an integer greater than 8.
2. The communication interface of claim 1, wherein the first interface is structurally identical to the second interface; each interface comprises a logic control unit, a register unit and a driving unit which are connected with each other; the driving unit of the first interface is connected to the driving unit of the second interface to form a plurality of transmission channels;
the logic control unit is used for acquiring the interconnection signal to be transmitted from the register unit and outputting the interconnection signal to be transmitted through the driving unit;
the logic control unit is further configured to store the interconnection signal received through the driving unit into the register unit.
3. The communication interface of claim 2, wherein the register unit comprises: an input state register, an input address register, an input data register and an output data register;
the logic control unit is used for judging whether the interface is in an output state according to the flag bit in the input state register;
the logic control unit is used for acquiring the interconnection signal to be transmitted from the output data register when the interface to which the logic control unit belongs is judged to be in an output state, and outputting the interconnection signal to be transmitted through the driving unit;
the logic control unit is used for controlling the driving unit to be in a receiving state when the interface to which the logic control unit belongs is judged to be in an input state, and receiving the interconnection signal through the driving unit;
and the logic control unit is used for storing the received interconnection signals into the input data register according to the address information in the input address register.
4. The communication interface of claim 2, wherein each of said drive units forms a plurality of pins on said interface; the pins of the first interface are in one-to-one correspondence with and connected with the pins of the second interface to form a plurality of transmission channels; the plurality of pins comprise M data pins; the transmission channel multiplexed is the transmission channel formed between the data pin of the first interface and the data pin of the second interface.
5. The communication interface of claim 1, wherein the first interface and the second interface use the same operating frequency, the operating frequency being an internal clock frequency of the first semiconductor unit or an internal clock frequency of the second semiconductor unit.
6. The communication interface of claim 1, wherein M is greater than or equal to a bit width of any of said interconnect signals of said plurality of types of interconnect signals.
7. The communication interface of claim 1, wherein M is equal to a maximum bit width among bit widths of the plurality of types of interconnect signals.
8. The communication interface of claim 1, wherein the plurality of transmission channels includes the transmission channel for transmitting a power signal, and the transmission channel for transmitting a power signal does not overlap the M transmission channels.
9. The communication interface of any of claims 1 to 8, wherein the plurality of types of interconnect signals comprises: operation instructions, address signals, and data signals.
10. The communication interface of claim 9, wherein the plurality of types of interconnect signals further comprises: communicating the handshake signals.
11. A package structure, comprising: the communication interface of any one of claims 1 to 10, the first semiconductor unit and the second semiconductor unit.
12. The package structure of claim 11, wherein the first semiconductor unit and the second semiconductor unit are a main control chip and a memory chip, respectively.
13. The package structure of claim 11, wherein a parasitic capacitance between any two of the transmission channels is less than a predetermined capacitance threshold.
14. The package structure of claim 13, wherein the first interface is structurally identical to the second interface; each interface comprises a logic control unit, a register unit and a driving unit which are connected with each other, and each driving unit forms a plurality of pins on the corresponding interface; the pins of the first interface are in one-to-one correspondence with and connected with the pins of the second interface to form a plurality of transmission channels;
and connecting the plurality of pins of the first interface and the plurality of pins of the second interface in a flip-chip packaging manner to form a plurality of transmission channels.
15. The package structure of claim 11, wherein the first semiconductor unit and the second semiconductor unit are both located on a third semiconductor unit, the communication interface being located on the third semiconductor unit;
the first interface and the second interface in the communication interfaces are connected through a wire on the third semiconductor unit.
16. The package structure of claim 15, wherein the third semiconductor unit is a chip, the first semiconductor unit is an analog signal module of the third semiconductor unit, and the second semiconductor unit is a digital signal module of the third semiconductor unit.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112041830A (en) * | 2020-01-21 | 2020-12-04 | 深圳市汇顶科技股份有限公司 | Communication interface and package structure |
| CN113254390A (en) * | 2021-06-09 | 2021-08-13 | 千芯半导体科技(北京)有限公司 | Reconfigurable computing structure, computing method and hardware architecture |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112041830A (en) * | 2020-01-21 | 2020-12-04 | 深圳市汇顶科技股份有限公司 | Communication interface and package structure |
| CN112041830B (en) * | 2020-01-21 | 2024-11-29 | 深圳市汇顶科技股份有限公司 | Communication interface and packaging structure |
| CN113254390A (en) * | 2021-06-09 | 2021-08-13 | 千芯半导体科技(北京)有限公司 | Reconfigurable computing structure, computing method and hardware architecture |
| CN113254390B (en) * | 2021-06-09 | 2021-10-29 | 千芯半导体科技(北京)有限公司 | Reconfigurable computing structure, computing method and hardware architecture |
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