CN211698170U - Signal detection device and radar system - Google Patents

Abstract

The utility model relates to the technical field of radar, in particular to a signal detection device and a radar system. The signal detection device provided by the utility model comprises a ring register link for updating the value of the corresponding data bit in the indication data according to each signal edge of the signal to be detected, and the frequency of the signal to be detected changes linearly within the detection interval; and a processing circuit, It is used to obtain the measurement value according to the start value and end value of the indication data in the detection interval, and obtain the detection result data according to the offset between the measurement value and the preset expected value corresponding to the detection interval, so that the detection result data can represent Whether the average value of the frequency of the signal to be detected within the detection interval satisfies the expected range. The radar system and the signal detection device provided by the present disclosure can monitor the frequency of the signal to be detected in real time, so as to determine whether the signal to be detected is in a normal state.

Description

Signal detection devices and radar systems

technical field

The utility model relates to the technical field of radar, and more particularly, to a signal detection device and a radar system.

Background technique

In a radar system, the frequency difference between the echo signal and the transmitted signal can be obtained by transmitting and receiving FM continuous waves, so as to obtain information such as the distance and speed of the target according to the frequency difference. This modulation method using frequency-modulated continuous waves has outstanding advantages such as simple implementation structure, simple signal processing process, low cost and low power, so it has been widely used in automotive radar and other fields.

Since the frequency of the FM CW changes continuously during the working process of the radar system, the frequency state of the FM CW can be used to judge whether the modules such as the phase-locked loop in the radar system are in normal working state.

Based on this, it is desirable to provide a frequency detection scheme of frequency-modulated continuous waves for judging whether the radar system is in a normal operation state.

Utility model content

In order to solve the above problems in the prior art, the present invention provides a radar system and a signal detection device, which can monitor the frequency of the signal to be detected in real time, thereby judging whether the frequency change of the signal to be detected is in a normal state.

According to a first aspect of the embodiments of the present invention, a signal detection device is provided, comprising: a ring register link for updating the value of a corresponding data bit in the indication data according to each signal edge of the signal to be detected, the to-be-detected signal The frequency of the signal changes linearly in the detection interval; and a processing circuit is used to obtain a measurement value according to the start value and end value of the indication data in the detection interval, and according to the measurement value corresponding to the detection interval The detection result data is obtained by the offset between the preset expected values, so that the detection result data represents whether the average value of the frequency of the signal to be detected within the detection interval satisfies the expected range.

Optionally, each rising edge and/or each falling edge of the signal to be detected is the signal edge, and for each detection interval, the ring register link is adapted to: at each of the signal edges The value of each data bit of the indication data is sequentially and cyclically updated under the triggering of the signal edge; and the value of a corresponding data bit in the indication data is updated under the triggering of each of the signal edges.

Optionally, the ring register link includes a plurality of registers cascaded in sequence, the registers at each level are respectively used to provide different data bits in the indication data, and the registers at each level are suitable for The detection signal and the input signal of the register provide the output signal of the register of this stage, and according to the signal to be detected and the input signal of the register of this stage and/or according to the output signal of the register to provide the corresponding in the indication data. The data bits, wherein, in the cascaded multiple registers: the first-level register obtains the input signal of this first-level register according to the inverted signal of the output signal provided by the last-level register; And Each level of registers other than the first level register obtains the input signal of the level register according to the output signal provided by the cascaded register at the previous level.

Optionally, the register at each stage updates the corresponding first data bit in the indication data according to the rising edge of the signal to be detected, and updates the corresponding first data bit in the indication data according to the falling edge of the signal to be detected. Two data bits.

Optionally, the registers at each level include: cascaded sample-hold module links, including at least a first-level sample-and-hold module and a second-level sample-and-hold module, the first-level sample-and-hold module in the sampling state an input signal of a stage register is sampled to generate a transfer signal, the second-stage sample-and-hold module samples the transfer signal in a sampling state to generate an output signal of the stage register; and a buffer module provides the transfer signal according to the transfer signal The first data bit is provided, and the second data bit is provided according to the output signal, wherein the first-level sample-and-hold module and the second-level sample-and-hold module enter alternately according to the level state of the signal to be detected sampling status.

Optionally, the detection result data includes a first result value, and the processing circuit includes: a sampling unit, configured to sample the indication data at the start time and end time of the detection interval to obtain the the start value and the end value of the indication data in the detection interval; a storage unit, used for pre-storing a relational look-up table, to indicate that a plurality of state values of the indication data are in the output logic of the ring register link respectively corresponding sequence numbers under the sequence, the plurality of state values include the start value and the end value, and the sequence numbers include a first sequence number corresponding to the start value and a first sequence number corresponding to the end value The second sequence number of the Threshold, if yes, then the first judgment unit sets the first result value as a valid state to indicate that the average value of the frequency of the signal to be detected in the detection interval does not meet the expected range, if not, then The first judging unit number sets the first result value as an invalid state to indicate that the average value of the frequency of the to-be-detected signal within the detection interval satisfies the expected range.

Optionally, the preset expected value is: based on the total number of the plurality of state values and the expected number of occurrences of the signal edge of the signal to be detected in the detection interval, the obtained data value is calculated.

Optionally, for each detection interval: the measured value is equal to the difference value, and the preset expected value is equal to twice the set value corresponding to the detection interval divided by the total number of the plurality of state values. The obtained remainder, the set value, is equal to the product of the expected average value of the frequency of the signal to be detected in the detection interval and the duration of the detection interval.

Optionally, the processing circuit further includes: a counter, configured to provide a count value according to the first bit result value, and the counter increases the count value by 1 in response to the first bit result value of the valid state , and in response to the first result value of the invalid state to reset the count value to an initial value; and a comparator for judging whether the count value is greater than the second threshold, if so, the comparator will The second bit result value of the detection result data is set to a valid state to indicate that the frequency change of the to-be-detected signal is in an abnormal state, if not, the comparator sets the second bit result value to an invalid state to It indicates that the frequency change of the signal to be detected is in a normal state.

Optionally, the signal to be detected is a frequency modulated continuous wave signal with a frame period, and the signal to be detected changes linearly in the linear interval of each frame period and is detected in the waiting interval of each frame period. Reset to the initial level, each of the detection intervals is included in the corresponding linear interval, and for each of the detection intervals, the processing circuit samples the to-be-detected signal according to the sampling clock signal to obtain The start value and the end value of the indication data in the detection interval, and the start time and end time of the detection interval are respectively two adjacent and same-direction clock edges in the sampling clock signal correspond.

Optionally, the signal detection device further includes: a frequency reduction circuit, which is cascaded before the ring register link and used to reduce the frequency of the to-be-detected signal according to a set frequency division ratio; and/or a shaping circuit, It is cascaded before the ring register link, and is used to shape the signal to be detected into a square wave, and the ring register link is based on the down-converted signal to be detected, or the shaped signal to be detected. , or the down-converted and shaped signal to be detected provides the indication data.

According to a second aspect of the embodiments of the present invention, a radar system is provided, including: a phase-locked loop structure, including a voltage-controlled oscillator, the voltage-controlled oscillator generates a frequency sweep signal according to a frequency control voltage, and the frequency sweep signal has a The frequency varies with the voltage value of the frequency control voltage; the signal detection device disclosed in any embodiment of the present invention is used to use the frequency sweep signal or the clock signal as the signal to be detected, and the frequency of the clock signal a set proportional to the frequency of the swept frequency signal; and a radar transceiver for providing a transmit signal and/or processing an echo signal according to the swept frequency signal.

For example, when the calculated offset is less than/equal to the first threshold, the signal detection device disclosed in the embodiment of the present invention can determine that the phase-locked loop structure is in a normal working state, otherwise it is in an abnormal working state; The accuracy of the judgment, the signal detection device disclosed in the embodiment of the present invention can respectively perform judgment processing for multiple detection intervals, and only in all or preset ratio detection intervals, the offset is less than/equal to the above-mentioned first The phase-locked loop structure is judged to be in a normal working state only when the threshold value and at the same time exhibit a certain regular change or a small change range. The determination of the magnitude of the variation range can be set based on actual accuracy requirements.

In addition, for the phase-locked loop structure in an abnormal working state, the signal detection device provided by the embodiment of the present invention can further analyze and judge the variation law of the offsets obtained in different detection intervals to determine whether the phase-locked loop structure is in a state of A locked state or an unstable state (that is, in this embodiment of the present application, the abnormal working state may include a locked state and an unstable state). For example, when the offset obtained in the adjacent sampling period (corresponding to the adjacent detection interval) changes randomly or the change range is relatively large, it can be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, at this time It can be considered that some devices in the phase-locked loop structure may be damaged; otherwise, it can be considered that the phase-locked loop structure is in a locked state in an abnormal state at this time.

According to the radar system and the signal detection device provided by the embodiment of the present invention, by updating each data bit in the indication data according to the signal edge of the signal to be detected, it is possible to judge the indication data according to the start value and end value of the indication data in the detection interval. Check whether the average value of the frequency of the detection signal in the detection interval conforms to the expected range, so as to realize the real-time monitoring of the frequency change of the signal to be detected. In the radar system of the embodiment of the present invention, since the frequency of the signal to be detected changes in proportion to the frequency sweep signal generated by the signal source, the detection result data provided by the signal detection device can indicate whether the signal source is working abnormally and whether the radar system is working abnormal.

Description of drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

1 shows a schematic structural diagram of a radar system according to an embodiment of the present invention;

FIG. 2 shows a schematic structural diagram of an embodiment of the signal source in FIG. 1;

Fig. 3 shows the waveform schematic diagram of the frequency sweep signal and the frequency control voltage in the embodiment of the present invention;

4 shows a schematic block diagram of a signal detection apparatus according to an embodiment of the present invention;

5 shows a schematic block diagram of a signal detection apparatus according to another embodiment of the present invention;

6 shows a schematic structural diagram of a ring register link according to an embodiment of the present invention;

Fig. 7 shows the circuit structure schematic diagram of each register in Fig. 6;

FIG. 8 shows a schematic block diagram of an implementation of the processing circuit in FIG. 4 or 5;

Figure 9 shows a schematic block diagram of another implementation of the processing circuit in Figure 4 or 5;

FIG. 10 shows a schematic flowchart of a signal detection method according to an embodiment of the present invention.

Detailed ways

The present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, like elements are designated by like reference numerals. For the sake of clarity, various parts in the figures have not been drawn to scale. Additionally, some well-known parts may not be shown in the drawings.

System Overview

FIG. 1 shows a schematic structural diagram of a radar system according to an embodiment of the present invention. FIG. 2 shows a schematic structural diagram of an embodiment of the signal source in FIG. 1 . FIG. 3 shows a schematic diagram of waveforms of the signal to be detected and the frequency control voltage in the embodiment of the present invention.

As shown in FIG. 1 , the radar system of the embodiment of the present invention includes: a transceiver antenna, a receiving channel, a transmitting channel, a signal source, a signal processing module, and a signal detection device. The transceiver antenna, receiving channel, transmitting channel and signal processing module are used as radar transceivers, and the radar transceiver provides transmit signals and/or processes echo signals according to the frequency sweep signal provided by the signal source.

Each part of the radar system based on the FM continuous wave system of this embodiment will be described below with reference to FIGS. 1 to 3 . However, the embodiments of the present invention are not limited thereto, and one/some unmentioned conventional structures or modules may also be included in the radar system of the embodiments of the present invention.

Transceiver antenna

The transceiver antenna includes a transmit antenna 1 and a receive antenna 2 . The transmitting antenna 1 provides space radiated electromagnetic wave based on the transmitting signal, the electromagnetic wave is reflected on the surface of the target, and the reflected electromagnetic wave is captured by the receiving antenna, so that the receiving antenna 2 obtains the echo signal. Since in the radar system 100 of the embodiment of the present invention, the transmission signal is a frequency-modulated continuous wave whose frequency is constantly changing, the radar system 100 of the frequency-modulated continuous wave system can obtain the target object's frequency difference according to the frequency difference between the transmission signal and the echo signal. Information such as distance, speed, etc., where the speed of the target object can be calculated and obtained through multiple distance measurements, for example.

signal source

The signal source 6 is used to generate a frequency sweep signal SFM whose frequency is constantly changing. The frequency of the frequency sweep signal changes in a trend such as a triangular wave or a sawtooth wave, and has a linear change trend in the detection interval. The frequency sweep signal SFM may be a periodic signal or an aperiodic signal, which is not limited in this application.

As an optional embodiment, the signal source 6 is, for example, the phase-locked loop structure (Phase Locked Loop, referred to as PLL) shown in FIG. 2, including a charge pump (Charge Pump, referred to as CP) 610, a loop filter ( Loop Filter (LP for short) 620, Voltage Controlled Oscillator (VCO for short) 630, Feedback Divider 640, Phase Frequency Detector (PFD for short) 650 and other modules.

The frequency discriminator 650 , the charge pump 610 , the loop filter 620 and the voltage controlled oscillator 630 are cascaded in sequence, and the output end of the voltage controlled oscillator 630 provides the output frequency sweep signal SFM. The feedback frequency divider 640 receives the frequency sweep signal SFM output by the voltage controlled oscillator 630, divides the frequency sweep signal SFM to obtain the frequency reduction frequency scan signal SFM_div, and provides the frequency reduction frequency scan signal SFM_div to the frequency discriminator 650, Thus, a feedback control loop in the phase-locked loop structure is formed.

The feedback frequency divider 640 is, for example, a multi-modulus frequency divider (Multi-Modulus Divider, referred to as MMD for short), and the multi-modulus frequency divider can divide the frequency of the sweep signal SFM according to the frequency division ratio set by the mode control signal to obtain Down-sweep the signal SFM_div, so as to realize the programmable frequency division function. When the frequency dividing ratio set by the mode control signal is constantly changing, the frequency of the scanning signal SFM can be continuously changed.

The frequency and phase detector 650 compares the frequency and phase of the reference signal Fref with the frequency and phase of the down-frequency scanning signal SFM_div to generate a first state signal Qa and a second state signal Qb representing the comparison result. As an example, the reference signal Fref may be provided by a crystal oscillator, or may be provided by other circuits or modules, which are not limited in this application.

The charge pump 610 generates the analog voltage signal Vo according to the received first state signal Qa and the second state signal Qb. The first state signal Qa and the second state signal Qb are respectively used to increase and decrease the voltage value of the analog voltage signal Vo.

The analog voltage signal Vo is filtered by the loop filter 620 to obtain the frequency control voltage Vc, so that the voltage controlled oscillator 630 generates a frequency sweep signal SFM under the control of the frequency control voltage Vc, and the frequency of the frequency sweep signal SFM corresponds to the frequency control voltage Vc corresponding to the voltage value. Under the control of the above phase-locked loop structure, as shown in FIG. 3 , the voltage value of the frequency control voltage Vc has a linear trend in each linear interval Tchrip_up, for example: the frequency control voltage Vc is at the starting moment of each linear interval Linearly increasing from the preset voltage, the frequency sweep signal provided by the voltage controlled oscillator 630 under the action of the preset voltage has a minimum frequency FL; at the end of each linear interval, the frequency control voltage Vc reaches the highest voltage, and the voltage controlled oscillation The frequency sweep signal provided by the device 630 under the action of the highest voltage has the maximum frequency FH; in the waiting interval between every two adjacent linear intervals, the frequency control voltage Vc is reset to the preset voltage. Therefore, the frequency of the frequency sweep signal SFM provided by the voltage controlled oscillator 630 varies linearly with the frequency control voltage Vc in each linear interval.

In some optional embodiments, the duration of each linear interval Tchrip_up is equal and the duration of each waiting interval is equal, and each linear interval and each waiting interval are alternately distributed in the time domain, so that the frequency control voltage Vc has a frame period and is A triangle wave or sawtooth wave occurs within a frame period.

In this embodiment, the signal source 6 is described by taking the above phase-locked loop structure as an example. However, the signal source in the embodiment of the present invention is not limited to this, and the signal source 6 can also be realized by other circuits capable of generating frequency sweep signals.

When the radar system is working, it is necessary to ensure that the phase-locked loop structure including the voltage-controlled oscillator is in a normal working state. Therefore, how to detect the working state of the phase-locked loop structure (or the signal source of other structures) is the key to ensure the normal operation of the radar system. The utility model monitors whether the phase-locked loop structure is in a normal working state by detecting the frequency-sweeping signal or the frequency-reduced signal of the frequency-sweeping signal, thereby ensuring the normal operation of the radar system.

Receive and transmit channels

The transmit channel 3 and the receive channel 4 are coupled to the transmit antenna 1 and the receive antenna 2, respectively. The transmit channel 3 is connected to the signal source 6 to receive the frequency sweep signal SFM, and the transmit channel 3 provides the transmit signal to the transmit antenna 1 according to the frequency sweep signal SFM, and processes the frequency sweep signal SFM to generate the first signal S1. The receiving channel 4 is connected to the receiving antenna 2 to receive the echo signal, and the echo signal is processed by filtering and the like, thereby generating the second signal S2.

mixing unit

The mixing unit 5 is connected with the transmitting channel 3 and the receiving channel 4 to receive the first signal S1 and the second signal S2, thereby obtaining the beat signal SD according to the first signal S1 and the second signal S2. The frequency of the beat signal SD is the difference between the frequency of the first signal S1 and the frequency of the second signal S2, so as to represent the difference between the time when the echo signal is received and the time when the transmit signal is transmitted, and the difference is the same as the target Information such as distance and speed of objects. The frequency of the beat signal SD is, for example, proportional to the distance between the target and the radar.

Signal processing module

The signal processing module 8 receives the beat signal SD provided by the mixing unit 5, and obtains the detection result Sdata according to the frequency of the beat signal SD. The detection result Sdata includes information such as the distance and speed of the target relative to the radar system.

The signal processing module 8 includes, for example, modules such as an analog-to-digital converter for generating a corresponding digital signal according to the beat signal SD, and an arithmetic unit for performing calculation processing on the digital signal.

Signal detection device

The radar system according to the embodiment of the present invention further includes a signal detection device 7, and the signal detection device 7 detects the to-be-detected signal STST provided by the signal source 6, and the to-be-detected signal STST (as shown in FIG. 3) may be a frequency sweep signal The SFM can also be a down-frequency signal of the frequency sweep signal SFM.

As an example, the to-be-detected signal STST is, for example, the down-frequency scanning signal SFM_div provided by the feedback frequency divider 640 in the signal source 6 .

As another example, as shown in FIG. 2 , the signal source 6 further includes a frequency divider 660, which is coupled to the output end of the voltage-controlled oscillator 630 to receive the frequency sweep signal SFM, and is used for dividing the frequency sweep signal The frequency of the SFM is down-converted to obtain the signal to be detected STST, in order to make the frequency of the signal to be detected STST conform to the operating frequency range of the signal detection device 7 .

It should be noted that the frequency divider 660 can be set in a hardware module for realizing the signal source 6, or can be set in a different hardware module from the components included in the signal source 6 such as the voltage-controlled oscillator 630, or can be combined with The signal detection device 7 is provided in the same hardware module, or exists in other forms, which is not limited in this embodiment of the present invention.

The signal detection device 7 is used to provide the indication data Dstate, and in the detection interval, according to each signal edge of the signal to be detected STST (that is, the edge of the level change of the signal STST to be detected, it can include each rising edge and/or each falling edge. ) to update the indication data Dstate, so that it can be judged whether the average value of the frequency of the to-be-detected signal STST in the detection interval meets the expected range according to the start value and end value of the indication data Dstate in the detection interval. For example, the signal detection device 7 can update the corresponding data bits in the indication data Dstate at each rising edge and every falling edge of the signal to be detected STST, or can only update the corresponding data bit in the indication data Dstate at each rising edge or every falling edge of the signal STST to be detected. Each falling edge updates the corresponding data bit in the indicated data Dstate.

It should be noted that, in the embodiment of the present invention, the linear interval Tchrip_up shown in FIG. 3 can be directly used as the detection interval. However, the embodiments of the present invention are not limited thereto, and in other embodiments, the detection interval may also be a part of the linear interval Tchrip_up.

FIG. 4 shows a schematic block diagram of a signal detection apparatus according to an embodiment of the present invention. The signal detection device 7 of this embodiment will be described in detail below according to FIG. 4 .

As shown in FIG. 4 , the signal detection device 7 includes a ring register chain 7100 and a processing circuit 7200 .

The ring register link 7100 is used to provide the indication data Dstate with multiple data bits, and update each data bit D1-Dn in the indication data Dstate according to the signal edge of the signal to be detected STST, where n is a natural number greater than 1.

For example, when a rising edge occurs on the signal to be detected STST, it indicates that the logic state of a corresponding data bit Di in the data Dstate changes (from 1 to 0 or from 0 to 1, referred to as the ith update for short), and then , when the signal STST to be detected has a falling edge, the logic state of another data bit Dj in the instruction data Dstate after the i-th update changes (referred to as the j-th update), and so on, it can be seen that: in each In the frame period, a rising edge and a falling edge appear on the signal STST to be detected, indicating that the data Dstate can be updated twice, that is, it indicates that the data Dstate has two corresponding data bits to be updated. Among them, i and j are non-zero natural numbers less than or equal to n, respectively.

In some optional embodiments, when i is less than n, j is equal to i+1, and when i is equal to n, j is equal to 1, so that each data bit D1 to Dn is updated cyclically.

In the above description, the ith update of the indication data Dstate occurs when the signal to be detected STST has a rising edge. It should be noted that, in some other equivalent embodiments, the ith update of the indication data Dstate may occur When a falling edge of the signal to be detected STST occurs, correspondingly, the j-th update of the indication data Dstate can occur when a rising edge of the signal to be detected STST occurs. In addition, in the description of the embodiments of the present invention, the update of a data bit in the indication data Dstate means that the logic value of the data bit is updated from 1 to 0 or from 0 to 1.

Various data values that may be provided by the indication data Dstate in the process of continuous updating are referred to herein as various state values of the indication data Dstate.

Processing circuit 7200 is connected to the output of ring register link 7100 to receive indication data Dstate. The processing circuit 7200 is used to obtain the preset expected value of the indication data Dstate corresponding to each detection interval, and judge the signal to be detected according to the start value and end value of the indication data Dstate in each detection interval and the preset expected value corresponding to the detection interval Whether the average value of the frequency of STST in the detection interval satisfies the expected range.

As an optional embodiment, in the linear interval, the processing circuit 7200 may sample the indication data Dstate under the trigger of the clock edge (rising edge or falling edge) of the sampling clock signal, so as to obtain the indication data Dstate in each detection interval start value and end value inside. In this case, each detection interval corresponds to a corresponding sampling period in the sampling clock signal, and the start moment and the end moment of each detection interval correspond to two adjacent and same-direction clock edges of the sampling clock signal. This embodiment will be described in detail below. However, the embodiment of the present invention is not limited to this. Each detection interval is not limited to corresponding to one sampling period of the sampling clock signal, but can also correspond to a plurality of consecutive sampling periods. It is related to other signals used to indicate the start time and end time of the detection interval.

Specifically, in each detection interval, the processing circuit 7200 can sample and obtain the initial value of the indication data Dstate at the start time of the detection interval. The data bits D1-Dn are updated cyclically; the processing circuit 7200 obtains the end value of the indication data Dstate at the termination time of the detection interval, and it can be known that the difference between the end value and the start value is related to the number of times the indication data Dstate is updated, that is, , which is related to the total number of signal edges that the to-be-detected signal STST appears in the detection interval. Therefore, the difference between the start value and the end value of the indication data Dstate in the detection interval is related to the average frequency of the signal to be detected STST in the detection interval. Based on this, the processing circuit 7200 can obtain the measurement value according to the difference between the start value and the end value of the indication data Dstate in each detection interval, and provide the detection result data Sout according to the measurement value and the preset expected value corresponding to the sampling period , so that the detection result data Sout can represent whether the average value of the frequency of the signal STST to be detected in each detection interval satisfies the expected range.

It should be noted that the "start value" disclosed herein refers to the data value indicating the data Dstate at the starting moment of the detection interval; the "end value" refers to the data value indicating the data Dstate at the ending moment of the detection interval data value. The start value and the end value are respectively one of the state values of the indication data Dstate.

In some optional embodiments, the preset expected value may represent the expected number of occurrences of the signal edge of the signal to be detected STST in the detection interval, for example, an expected average value of the frequency of the signal to be detected STST in the detection interval. Based on this, the processing circuit 7200 can calculate and obtain the predicted end value of the indication data Dstate within the detection interval according to the initial value of the indication data in the detection interval, the preset expected value corresponding to the detection interval, and the duration of the detection interval; Subsequently, the processing circuit 7200 can compare the end value obtained by sampling with the predicted end value obtained by calculation. If the two are consistent within the allowable error range, it means that the average value of the frequency of the signal to be detected STST within the detection interval meets expectations If the two are inconsistent within the allowable error range, it means that the average value of the frequency of the signal STST to be detected in the detection interval does not meet the expected range, the signal source 6 (as shown in Figure 1) and the radar system is abnormal.

In some other optional embodiments, the preset expected value may be a value calculated according to the total number of possible state values provided by the specified data Dstate and the expected number of occurrences of the signal edge of the signal STST to be detected in the detection interval. Based on this, for each detection interval, the processing circuit 7200 can determine the frequency of the to-be-detected signal STST according to the difference between the start value and the end value of the to-be-detected signal STST in the detection interval and the preset expected value corresponding to the detection interval Whether the average value within the detection interval meets the expected range. This embodiment will be described in detail later, and will not be repeated here.

In the embodiment shown in FIG. 4 , the ring register link 7100 has a clock terminal, and the clock terminal directly receives the to-be-detected signal STST, so that the ring-register link uses the to-be-detected signal STST as the clock signal clk. As mentioned above, since the signal to be detected STST is the frequency-sweeping signal SFM or the frequency-reduced signal of the frequency-sweeping signal SFM, it can be provided according to the known frequency ratio between the signal to be detected STST and the frequency-sweeping signal SFM and the processing circuit 7200 provides The detection result data Sout is to know whether the average value of the frequency of the frequency sweep signal SFM in the detection interval satisfies the expected frequency range, that is, the detection result data Sout provided by the processing circuit 7200 can also indicate that the frequency of the frequency sweep signal SFM is within the detection interval. whether the average of , is within the expected range. When the detection result data Sout indicates that the average value of the frequency of the signal STST to be detected within the detection interval meets the expected range, it means that the signal source is working normally and the frequency of the sweeping signal SFM changes correctly, and the radar system can work normally; when the detection result When the data indicates that the average value of the frequency of the signal to be detected STST in the detection interval does not meet the expected range, it indicates that the signal source is working abnormally and the frequency change of the frequency sweep signal SFM does not meet the expected range. At this time, the radar system is working abnormally.

FIG. 5 shows a schematic block diagram of a signal detection apparatus according to another embodiment of the present invention.

In the above description, the ring register link 7100 directly uses the to-be-detected signal STST as the clock signal clk, but the embodiment of the present invention is not limited to this, the clock end of the ring register link 7100 can receive the frequency and the frequency of the frequency sweep signal SFM any related signal. For example, in some alternative embodiments, as shown in FIG. 5 , the signal detection apparatus 7 further includes a driving circuit 7300 for down-converting and/or reshaping the to-be-detected signal STST, and converting the down-frequency and/or reshaping to-be-detected signal STST. The detection signal STST serves as the clock signal clk of the ring register link 7100 .

As shown in FIG. 5 , the driving circuit 7300 includes, for example, a shaping circuit, which is used for buffering and/or shaping the signal to be detected, so that the signal to be detected input to the ring register link 7100 is a square wave signal, which can improve the ring shape The detection accuracy of the signal to be detected by the register chain 7100.

The driving circuit 7300 may further include a frequency reduction circuit (for example, implemented by a frequency dividing circuit structure), and the frequency reduction unit may be cascaded before the shaping circuit or after the shaping circuit, so as to reduce the frequency to be used according to the set frequency division ratio. The frequency of the detection signal is further improved, thereby further improving the detection accuracy of the ring register link 7100 for the signal to be detected, and reducing the performance requirements for the ring register link 7100 .

It should be noted that the above-mentioned frequency divider 660 (as shown in FIG. 2 ) has the same function as the frequency reduction circuit in the drive circuit 7300 (as shown in FIG. 5 ), both of which are to allow the input to the ring register link The frequency of the signal to be detected 7100 is reduced to within the operating frequency range of the ring register link 7100 . Therefore, the frequency divider 660 (as shown in FIG. 2 ) and the frequency reduction circuit in the driving circuit 7300 (as shown in FIG. 5 ) may exist at the same time, or may be set by one, which is not limited in this application.

Take the application of millimeter wave radar as an example: the form of the swept frequency signal SFM in the time domain is Frequency Modulated Continuous Wave (FMCW for short), and its frequency varies, for example, in the frequency range of 30GHz to 300GHz, while the ring register link The operating frequency of each register in the 7100 is at the megahertz level, so the frequency of the sweep signal SFM needs to be down-converted to obtain the signal to be detected, so that the frequency of the clock signal clk input to the ring register link 7100 falls within the ring register link 7100 Within the operating frequency range of , the frequency reduction process can be implemented by the frequency divider 660 shown in FIG. 2 and/or the frequency dividing circuit in the driving circuit 7300 shown in FIG. 5 ; Usually it needs to be triggered by the clock signal clk in the form of a square wave. When the frequency sweep signal SFM is a FM continuous wave in the form of a sine wave, the signal to be detected input to the ring register link 7100 can be shaped into a square wave and used as the clock signal clk, The shaping process can be implemented by the shaping circuit in the driving circuit 7300 shown in FIG. 5 . As mentioned above, the shaping process proposed here may be performed before the frequency reduction process, or may be performed after the frequency reduction process, which is not limited in this application.

In the embodiment shown in FIG. 5 , the ring register link 7100 and the processing circuit 7200 are the same as or similar to the embodiment shown in FIG. 4 , and thus will not be described again.

The ring register link 7100 and the processing circuit 7200 in the embodiment of the present invention will be described in detail below.

ring register link

FIG. 6 shows a schematic structural diagram of a ring register link according to an embodiment of the present invention. FIG. 7 shows a schematic diagram of the circuit structure of each register in FIG. 6 . The ring register link of the embodiment of the present invention will be described in detail below with reference to FIG. 6 and FIG. 7 .

As shown in FIG. 6 , the ring register link 7100 includes a plurality of registers 7110 that are cascaded in sequence, and the last level of registers is cascaded before the first level of registers to form a ring link.

Each stage of register 7110 generates the output signal DOUT of the current stage and the corresponding data bit in the indication data Dstate according to the clock signal clk, the inverted clock signal clkb and the input signal DIN of the current stage. different data bits.

The ring register chain 7100 also includes an odd number of inverters INV1 cascaded between the first-stage register and the last-stage register, so that the first-stage register can obtain the present invention according to the inverted signal of the output signal provided by the last-stage register. level input signal. Each level of registers other than the first level register obtains the input signal of the current level according to the output signal provided by the cascaded register of the previous level.

The ring register chain 7100 also includes an odd number of inverters INV0 for generating the inverted clock signal clkb from the clock signal clk, so that the inverted clock signal clkb is the inverted signal of the clock signal clk.

In an optional embodiment, as shown in FIG. 6 , the data bit n of the indication data Dstate is a non-zero even number, and the registers 7110 of all levels correspond to the corresponding two adjacent data bits in the indication data Dstate, for example The first level register 7110 is used for outputting the data bit D1 and the data bit D2 in the indication data Dstate, the second level register 7110 is used for outputting the data bit D3 and the data bit D4 in the indication data Dstate, and so on.

As an example, each stage of the register 7110 may update the corresponding first data bit Dk (output from the DF1 terminal of the register) in the indication data Dstate according to the rising edge of the clock signal clk, and update the indication data Dstate according to the falling edge of the clock signal clk The corresponding second data bit Dp in (output by the DF2 terminal of the register of this stage). Wherein, k and p are non-zero natural numbers less than or equal to n respectively, and p is preferably equal to k+1.

In other embodiments, each level of registers 7110 may update the corresponding first data bit Dk in the indication data Dstate according to the falling edge of the clock signal clk, and update the corresponding second data bit Dstate in the indication data Dstate according to the rising edge of the clock signal clk The principle of the bit Dp is the same as that of the above-mentioned embodiment, and details are not repeated here.

It should be noted that "updating a data bit" described in this article refers to resetting the corresponding data bit according to the current state of each relevant signal, that is, updating the corresponding data bit in the indication data Dstate may make the data bit The logical state of the device does or does not change.

As an optional embodiment, as shown in FIG. 7 , each level of register 7110 includes at least two levels of sample-and-hold modules. The number of cascaded sample-and-hold modules in each level of register 7110 may be the same as the number of bits of indication data corresponding to each level of register. In this embodiment, each level of register corresponds to 2 data bits, and each level of register includes a first-level sample-and-hold module and a second-level sample-and-hold module as an example for description, but the embodiment of the present application is not limited to this.

As shown in FIG. 7 , the first-stage sample and hold module 7111 samples the input signal DIN of the register of this stage in the sampling state to generate the transfer signal DZ, and the second-stage sample-and-hold module 7112 samples the transfer signal DZ in the sampling state to generate The output signal DOUT of the register of this stage.

The first-stage sampling and holding module 7111 has a sampling state and a holding state, and alternately enters the sampling state and the holding state according to the clock signal clk. In the sampling state, the first-stage sample-and-hold module 7111 updates the transfer signal DZ according to the input signal DIN of the register of this stage; in the hold state, the first-stage sample-and-hold module 7111 keeps the transfer signal unchanged.

As an optional embodiment, the first-stage sample-and-hold module 7111 may include a transmission gate controlled by the clock signal clk. The transmission gate includes, for example, field effect transistors M11 and M12, the sources of the field effect transistors M11 and M12 are connected and receive the input signal DIN of the register 7110 of this stage, and the drains of the field effect transistors M11 and M12 are connected and provide the transfer signal DZ; field effect The gates of the transistors M11 and M12 receive the clock signal clk and the inverted clock signal clkb, respectively.

The first-stage sample-and-hold module 7111 may further include an even number of inverters (NOT gates) for buffering the input signal DIN input to the transmission gate, and/or buffering the transmission signal DZ output by the transmission gate.

The second-stage sample-and-hold module 7112 and the first-stage sample-and-hold module 7111 may have the same circuit structure. For example, the second-stage sample-and-hold module 7112 includes a transmission gate composed of field effect transistors M21 and M22. The source is connected to and receives the transfer signal DZ provided by the first-stage sampling and holding module 7111, the drains of the field effect transistors M21 and M22 are connected and provide the output signal DOUT of the register of this stage, and the gates of the field effect transistors M21 and M22 respectively receive the clock signal clk and the inverted clock signal clkb. The second-stage sample-and-hold module 7112 may also include an even number of inverters for buffering the transfer signal DZ input to the transmission gate, and/or buffering the output signal DOUT provided by the register of this stage.

In an optional embodiment, the transmission gate in the first-stage sample-and-hold module 7111 is cascaded between two inverters, and the transmission gate in the second-stage sample-and-hold module 7112 is cascaded between the other two inverters Therefore, a simple circuit structure can be used to achieve an accurate sample-and-hold function.

In order to make the working state of the second-stage sample-hold module 7112 and the first-stage sample-and-hold module 7111 different at the same time, that is, the first-stage sample-and-hold module 7112 and the first-stage sample-and-hold module 7111 alternately enter the sampling state and alternately enter the holding state , the transmission gate in the second-stage sampling and holding module 7112 and the transmission gate in the first-stage sampling and holding module 7111 are alternately turned on under the control of the clock signal clk.

As an optional embodiment, the gates of the field effect transistors M12 and M21 receive the inverted clock signal clkb, the gates of the field effect transistors M11 and M22 receive the clock signal clk, and the field effect transistors M11 and M21 are, for example, PMOS transistors, The field effect transistors M12 and M22 are, for example, NMOS transistors. Therefore, when the clock signal clk is at a low level, the transmission gate in the first-stage sampling and holding module 7111 is turned on, so that the transmission signal DZ is the same as the input signal DIN received by the current-stage register. At this time, the first-stage sampling and holding module 7111 Working in the sampling state, the second-stage sampling and holding module 7112 works in the holding state; when the clock signal clk is at a high level, the transmission gate in the second-stage sampling and holding module 7112 is turned on, so that the output signal DOUT provided by the register at this stage is The transmission signal DZ provided by the first-level sample-and-hold module 7111 is the same. At this time, the first-level sample-and-hold module 7111 works in the hold state, and the second-level sample-and-hold module 7112 works in the sampling state.

As shown in FIG. 7 , each level of register 7110 further includes a first-level buffer module 7113 and a second-level buffer module 7114 . The first-stage buffer module 7113 buffers the transfer signal DZ output by the first-stage sample and hold module 7111 to drive/shape to obtain the first data bit Dk corresponding to the register of this stage in the indication data Dstate, and the second-stage buffer module 7114 The output signal DOUT provided by the second-level sample-and-hold module 7112 is buffered to drive/shape to obtain the second data bit Dp corresponding to the register of this level in the indication data Dstate. The first-stage buffer module 7113 and the second-stage buffer module 7114 respectively include, for example, an even number of cascaded inverters (NOT gates).

In the above-mentioned embodiment, the sample and hold modules of all levels and the buffer modules of all levels receive the same power supply voltage, for example, the high-level power supply voltage VDD and the low-level voltage VSS.

processing circuit

FIG. 8 shows a schematic block diagram of an implementation of the processing circuit in FIG. 5 or FIG. 4 .

The following describes and illustrates the processing circuit of the embodiment of the present invention according to the implementation shown in FIG. 8 . However, the embodiment of the present invention is not limited to this. Other implementation principles of the processing circuit are described above, and those skilled in the art can also use Other judgment methods judge whether the average value of the frequency of the signal to be detected in the detection interval is within the expected range.

As shown in FIG. 8 , the processing circuit 7200 includes a sampling unit 7210 , a storage unit 7220 and a first judgment unit 7230 .

The sampling unit 7210 is configured to sample the indication data Dstate provided by the ring register link 7100 at the start time of the detection interval to obtain the start value Dstate_ini of the indication data in the detection interval, and to perform sampling on the ring at the end time of the detection interval. The indication data Dstate provided by the register link 7100 is sampled to obtain the end value Dstate_end of the indication data within the detection interval. The sampling unit 7210 receives the sampling clock signal clk_cs, the frequency of the sampling clock signal clk_cs is lower than the frequency of the clock signal clk of the ring register link 7100, and the sampling period Tsample of the sampling clock signal clk_cs corresponds to a detection interval, so the sampling unit 7210 can The start value Dstate_ini and the end value Dstate_end are obtained by sampling under the control of the sampling clock signal clk_cs.

The storage unit 7220 is used to pre-store various possible state values Dstate_1 to Dstate_2n of the indication data, and store the corresponding sequence numbers of the various state values of the indication data in the logical order of the output of the ring register link, so as to establish the relationship between the different state values. The relationship lookup table between the sequence numbers is, for example, the relationship lookup table shown in Table 1 below.

Table 1 Lookup table for the relationship between different state values stored in advance and each sequence number

In each detection interval, the first judgment unit 7230 is configured to obtain the sequence number a2 corresponding to the end value Dstate_end of the indication data in the detection interval and corresponding to the start value Dstate_ini of the indication data in the detection interval according to the above relationship lookup table The difference Δa between the sequence numbers a1 of , and the measured value of the detection interval is obtained according to the difference Δa. Further, the first judging unit 7230 can be used to judge whether the offset a_os between the measured value of the detection interval and the preset expected value a_ref is greater than the first threshold, and if so, set the first result value of the detection result data Sout Sout[0] is a valid state (for example, 1, and can also be 0 in other embodiments), if not, set the first result value Sout[0] of the detection result data to an invalid state (for example, 0, other implementations In the example, it can also be 1), so that the first result value Sout[0] can represent whether the average value of the frequency of the signal to be detected in the detection interval meets the expected range, and the reasons are as follows:

As mentioned above, the clock signal clk of the ring register link 7100 is the signal to be detected, the down-frequency signal of the signal to be detected, the signal to be detected after square wave shaping, or the signal to be detected after square wave shaping and frequency reduction, etc. Therefore, There is a set ratio Ndiv between the frequency of the frequency sweep signal provided by the signal source and the frequency of the clock signal clk, and the set ratio is usually a positive real number greater than or equal to 1.

Assuming that the frequency of the sweep signal SFM in the detection interval is fixed as f0, and the duration of the detection interval is equal to one sampling period Tsample of the sampling clock signal clk_cs, then in the detection interval, the frequency of the clock signal clk is f0/Ndiv, The number of times the indication data Dstate provided by the ring register link 7100 is updated in the detection interval is equal to:

2*Tsample/[1/(f0/N _div )]

However, since the frequency sweep signal SFM actually increases linearly in each detection interval, between every two adjacent sampling points, the expected number of times the indication data Dstate output by the ring register link 7100 is updated is equal to:

{2*Tsample/[1/(F _y-1 /N _div )]+2*Tsample/[1/(F _y /N _div )]}/2

which is:

Tsample*(F _y-1 +F _y )/N _div

Where y is a natural number greater than or equal to 1, Fy and Fy-1 are the expected frequency of the sweep signal SFM corresponding to the current sampling point (the current clock edge of the sampling clock signal clk_cs) and the adjacent previous sampling point (the sampling clock signal The expected frequency of the sweep signal SFM corresponding to the next clock edge of clk_cs). Fy-1 and Fy correspond, for example, to frequencies F1 and F2 shown in FIG. 3 , respectively.

Table 1 shows 16 (ie, 2n) state values of the ring register link 7100 by taking the 8-bit indication data Dstate (ie, n=8) as an example. In this example, the ring register link may include 4-level registers, and each The stage register corresponds to the corresponding 2 data bits in the indication data. The ring register link 7100 uses 16 outputs as a cycle, and outputs 16 state values of the indication data Dstate cyclically according to the output logic sequence, and these 16 state values correspond to the sequence numbers 1 to 1 according to the output logic sequence of the ring register link 7100. 16.

According to the above analysis, two adjacent clock edges in the sampling clock signal can define a detection interval, and the remainder obtained by dividing the expected number of times the indicated data Dstate is updated in the detection interval divided by 16 can be calculated to obtain the corresponding detection interval. The preset expected value a_ref represents the ideal value of the difference Δa calculated and obtained by the first judgment unit 7230 .

Based on this, the first judging unit 7230 can judge whether the offset a_os between the difference Δa (ie the measured value) and the preset expected value a_ref is greater than the first threshold. If so, it means that the deviation between the difference Δa and the preset expected value a_ref is too large and exceeds the allowable range determined by the first threshold value. At this time, the first judgment unit 7230 can set the first result value Sout[ 0] is set to the valid state to indicate that the average value of the frequency of the signal STST to be detected in the detection interval does not meet the expected range, so that the signal source and the radar system can be known according to the first result value Sout[0] of the valid state is in an abnormal working state; if not, it means that the deviation between the difference Δa and the preset expected value a_ref is within the allowable range determined by the first threshold, at this time the first judgment unit 7230 can set the first digit of the detection result data Sout The result value Sout[0] is set to the invalid state to indicate that the average value of the frequency of the signal STST to be detected in the detection interval meets the expected range, so that the signal source and The radar system is in normal working condition.

As an optional embodiment, the first judging unit 7230 may include: a search module for searching the corresponding sequence numbers a1 and a2 in the storage unit 7220 according to the start value and end value provided by the sampling unit 7210; a calculation module for using Calculate the difference Δa according to the sequence numbers a1 and a2, and calculate the offset between the difference Δa and the preset expected value a_ref; the comparison module is used to compare the offset with the first threshold to generate the first bit result Value Sout[0].

FIG. 9 shows a schematic block diagram of yet another implementation of the processing circuit in FIG. 6 .

As a further optimized embodiment, as shown in FIG. 9 , in addition to the sampling unit 7210 , the storage unit 7220 and the first determination unit 7230 described in the above embodiments, the processing circuit 7200 may further include a second determination unit 7240 . The second judging unit 7240 is configured to provide the second bit result value Sout[1] in the detection result data Sout, so as to further provide the detection result information of the signal to be detected.

As shown in FIG. 9 , the second judgment unit 7240 is configured to generate the second result value Sout[1] according to the first result value Sout[0], and the second judgment unit 7240 includes a counter 7241 and a comparator 7242 .

Among them, the counter 7241 is used to provide the count value num according to the first bit result value Sout[0]. When the first result value Sout[0] is in the valid state, the counter 7241 adds 1 to the count value num; and when the first result value Sout[0] received by the counter 7241 is in the invalid state, the counter 7241 will count the value num is reset to its initial value. Therefore, the count value num can represent the number of sampling cycles in which the first result value Sout[0] continuously represents the abnormal working state, that is, the number of sampling cycles in which the frequency of the sweep signal SFM does not conform to the preset frequency continuously.

The comparator 7242 is used to compare the count value num provided by the counter 7241 with the second threshold max_ref to obtain the second bit result value Sout[1]. When the count value num is greater than the second threshold max_ref, the comparator 7242 will output the second result value Sout[1] of the valid state to indicate that the frequency of the signal to be detected STST exceeds the expected number of consecutive detection intervals/sampling periods The average value in , does not meet the expected range, which means that the signal source and the radar system are in abnormal working state for a long time and are not easy to return to normal by themselves; and when the count value num is less than/equal to the second threshold max_ref, the output of the comparator 7242 is invalid The second bit result value of the state, Sout[1], is used to indicate that the frequency changes of the signal to be detected and the related frequency sweep signal are as expected.

In an optional embodiment, the post-stage circuit connected to the comparator 7242 can be triggered by the second result value Sout[1] of the valid state to initiate an early warning prompt, and the early warning prompt includes but is not limited to sound prompts, pop-up window prompts, Optical tips, etc. When the second bit result value Sout[1] is in an invalid state, the post-stage circuit does not need to initiate an early warning prompt.

The present invention also provides a signal detection device according to the above embodiments, which is used for judging whether the average value of the frequency of the signal to be detected in each detection interval conforms to a desired range.

According to the radar system and the signal detection device provided by the embodiment of the present invention, by updating each data bit of the indication data according to the signal edge of the signal to be detected, the signal to be detected can be judged according to the start value and end value of the indication data in the detection interval Whether the average value of the frequency in each detection interval conforms to the expected range, so as to realize real-time monitoring of the frequency of the signal to be detected. In the radar system of the embodiment of the present invention, since the frequency of the signal to be detected changes in proportion to the frequency sweep signal generated by the signal source, the detection result data provided by the signal detection device can be used to indicate whether the signal source and the radar system are in normal state working status.

In some optional embodiments, the signal detection apparatus can use a sampling clock signal to sample the indication data, so as to obtain the start value of the indication data at the start of the detection interval, and obtain the end of the indication data at the end of the detection interval value, and obtain the corresponding measurement value according to the start value and end value, so that the average frequency of the signal to be detected in the detection interval can be judged according to the offset between the measurement value corresponding to each detection interval and the preset expected value Whether the value is within the expected range to enable real-time monitoring of the frequency of the signal to be detected.

For example, for a signal source including a phase-locked loop structure, when the calculated offset is less than or equal to the first threshold, it can be determined that the phase-locked loop structure is in a normal working state, otherwise it is in an abnormal working state; and in order to improve The accuracy of the judgment, the signal detection device and the radar heartache according to the embodiment of the present invention can respectively perform judgment processing for multiple detection intervals, and only in all or preset ratio detection intervals, the offset is less than/equal to the above-mentioned The phase-locked loop structure is judged to be in a normal working state only when the first threshold value exhibits a certain regular change or the change range is small at the same time. The determination of the magnitude of the variation range can be set based on actual accuracy requirements.

In addition, for the phase-locked loop structure in an abnormal working state, the signal detection device and the radar system disclosed in the embodiments of the present invention can also determine the phase-locked loop by further analyzing and judging the variation law of the offsets obtained in different detection intervals. Whether the structure is in a locked state or an unstable state (that is, in the embodiment of the present application, the abnormal working state may include a locked state and an unstable state). For example, when the offset obtained in the adjacent sampling period (for example, corresponding to the adjacent detection interval) changes randomly or the change range is large, it can be determined that the phase-locked loop structure is in an unstable state in an abnormal state at this time, that is, this At this time, it can be considered that some devices in the phase-locked loop structure may be damaged; otherwise, it can be considered that the phase-locked loop structure is in a locked state in an abnormal state at this time.

FIG. 10 shows a schematic flowchart of a signal detection method according to an embodiment of the present invention. Steps S810 to S850 are included. This method is applied to, for example, the signal detection device and the radar system of the above embodiments.

In step S810, the to-be-detected signal is provided according to the frequency sweep signal, so that the frequency of the to-be-detected signal and the frequency of the frequency sweep signal are in a set ratio. The frequency of the sweeping signal changes linearly within the detection interval, so that the frequency of the signal to be detected also changes linearly within the detection interval.

In step S820, the indication data having a plurality of data bits is provided, and the corresponding data bits in the indication data are updated according to the signal edge of the signal to be detected.

As an optional embodiment, each rising edge and/or each falling edge of the signal to be detected may be used as a signal edge for updating the indication data. Step S820 may include: sequentially cyclically updating the value of each data bit of the indication data under the trigger of each signal edge; and updating the value of a corresponding data bit in the indication data under the trigger of each signal edge.

In step S830, the indication data is sampled at the start time and the end time of the detection interval to obtain the start value and end value of the indication data within the detection interval, and the corresponding detection interval is obtained according to the start value and the end value measured value.

In step S840, for each detection interval, a corresponding preset expected value is calculated, and an offset between the measured value corresponding to the detection interval and the preset expected value is obtained.

In step S850, the detection result data is obtained according to the offset to represent whether the average value of the frequencies of the signal to be detected and the frequency sweep signal in the detection interval meets the expected range.

It should be noted that the signal detection method provided by the embodiment of the present invention may include the technical details and features proposed in the description of the signal detection device and the radar system of each embodiment above, and the same parts will not be repeated here.

In the signal detection method provided by the embodiment of the present invention, by updating each data bit in the indication data according to the signal edge of the signal to be detected, it is possible to judge whether the frequency of the signal to be detected is within Whether the average value in the detection interval conforms to the expected range, so as to realize real-time monitoring of the frequency of the signal to be detected. Since the frequency of the signal to be detected changes in proportion to the frequency sweep signal, the detection result data generated by the signal detection method of the embodiment of the present invention can be used to indicate whether the signal source and the radar system are in normal working state.

In some optional embodiments, the signal detection method can use a sampling clock signal to sample the indication data, so as to obtain the start value of the indication data at the start of the detection interval, and obtain the end of the indication data at the end of the detection interval value, and obtain the corresponding measurement value according to the start value and end value, so that the average frequency of the signal to be detected in the detection interval can be judged according to the offset between the measurement value corresponding to each detection interval and the preset expected value Whether the value is within the expected range to enable real-time monitoring of the frequency of the signal to be detected.

It should be noted that, herein, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements, It also includes other elements not expressly listed or inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Embodiments according to the present invention are described above, and these embodiments do not describe all the details, nor do they limit the present invention to only the specific embodiments described. Obviously, many modifications and variations are possible in light of the above description. This specification selects and specifically describes these embodiments in order to better explain the principle and practical application of the present utility model, so that those skilled in the art can make good use of the present utility model and modifications based on the present utility model. . The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. a signal detection device, is characterized in that, comprises: a ring register link, receiving the signal to be detected, configured to update the value of the corresponding data bit in the indication data according to each signal edge of the signal to be detected, the frequency of the signal to be detected changing linearly within the detection interval; and a processing circuit, connected to the ring register link to receive the indication data, configured to obtain a measurement value based on a start value and an end value of the indication data within the detection interval, and to obtain a measurement value based on the measurement value The detection result data is obtained by the offset between the preset expected values corresponding to the detection interval, so that the detection result data represents whether the average value of the frequency of the signal to be detected in the detection interval meets the expected range. 2. The signal detection device according to claim 1, wherein each rising edge and/or each falling edge of the signal to be detected is the signal edge, For each of the detection intervals, the ring register link is adapted to: Under the triggering of each of the signal edges, the value of each data bit of the indication data is sequentially and cyclically updated; and The value of a corresponding data bit in the indication data is updated under the triggering of each of the signal edges. 3 . The signal detection device according to claim 1 , wherein the ring register link comprises a plurality of registers cascaded in sequence, and the registers at each level are respectively used to provide different data bits in the indication data. 4 . , the register of each stage is adapted to provide the output signal of the register of this stage according to the signal to be detected and the input signal of the register, and according to the signal to be detected and the input signal of the register of this stage and/or according to the the output signal of the register provides the corresponding data bit in the indication data, Wherein, among the multiple registers cascaded in sequence: The first stage register obtains the input signal of the first stage register according to the inversion signal of the output signal provided by the last stage register; and Each level of registers other than the first level register obtains the input signal of the level register according to the output signal provided by the cascaded register at the previous level. 4 . The signal detection device according to claim 3 , wherein the register at each stage is configured to update the corresponding first data bit in the indication data according to the rising edge of the signal to be detected, and according to the The falling edge of the signal to be detected updates the corresponding second data bit in the indication data. 5. The signal detection device according to claim 4, wherein the registers at each level comprise: The cascaded sample-hold module chain includes at least a first-stage sample-and-hold module and a second-stage sample-and-hold module, wherein the first-stage sample-and-hold module samples the input signal of the register in the sampling state to generate a transfer signal, The second-stage sample-and-hold module samples the transfer signal in a sampling state to generate an output signal of this stage of register; and a buffer module that provides the first data bits according to the transfer signal, and provides the second data bits according to the output signal, Wherein, the first-level sampling and holding module and the second-level sampling and holding module alternately enter the sampling state according to the level state of the signal to be detected. 6. The signal detection device according to claim 1, wherein the detection result data comprises a first bit result value, and the processing circuit comprises: a sampling unit, configured to sample the indication data at the start time and end time of the detection interval to obtain the start value and the end value of the indication data in the detection interval; The storage unit is used for pre-storing a relationship look-up table to indicate the sequence numbers corresponding to the plurality of state values of the indication data in the output logical sequence of the ring register link, and the plurality of state values include the start a start value and the end value, the sequence numbers include a first sequence number corresponding to the start value and a second sequence number corresponding to the end value; and a first judging unit, configured to obtain the measured value according to the difference between the first sequence number and the second sequence number, and judge whether the offset is greater than a first threshold, If yes, then the first judgment unit sets the first result value as a valid state to indicate that the average value of the frequency of the to-be-detected signal within the detection interval does not meet the expected range, If not, the first judging unit number sets the first result value as an invalid state to indicate that the average value of the frequency of the to-be-detected signal within the detection interval satisfies the expected range. 7. The signal detection device according to claim 6, wherein the processing circuit further comprises: a counter for providing a count value based on the first bit result value, the counter being responsive to the first bit result value of a valid state to increment the count value by one, and responsive to the first bit result value of an invalid state bit result value to reset the count value to the initial value; and a comparator for judging whether the count value is greater than the second threshold, If so, the comparator sets the result value of the second bit of the detection result data to a valid state to indicate that the frequency change of the to-be-detected signal is in an abnormal state, If not, the comparator sets the result value of the second bit to an invalid state to indicate that the frequency change of the signal to be detected is in a normal state. 8. The signal detection device according to claim 1, wherein, The signal to be detected is a frequency modulated continuous wave signal with a frame period, and the signal to be detected changes linearly in the linear interval of each frame period and is reset to the initial power level in the waiting interval of each frame period. flat, each said detection interval is included in the corresponding said linear interval, For each detection interval, the processing circuit samples the to-be-detected signal according to the sampling clock signal to obtain the start value and the end value of the indication data within the detection interval, and the The start time and the end time of the detection interval respectively correspond to two adjacent and same-direction clock edges in the sampling clock signal. 9. The signal detection device according to claim 1, wherein the signal detection device further comprises: A frequency reduction circuit, cascaded before the ring register link, for reducing the frequency of the to-be-detected signal according to a set frequency division ratio; and/or A shaping circuit, cascaded before the ring register link, is used for shaping the to-be-detected signal into a square wave, The ring register link provides the indication data according to the down-converted signal to be detected, or the reshaped signal to be detected, or the down-converted and reshaped signal to be detected. 10. A radar system, comprising: The phase-locked loop structure includes a voltage-controlled oscillator, the voltage-controlled oscillator generates a frequency sweep signal according to a frequency control voltage, and the frequency of the frequency sweep signal changes with the voltage value of the frequency control voltage; The signal detection device according to any one of claims 1 to 9, wherein the frequency sweep signal or the clock signal is used as the signal to be detected, and the frequency of the clock signal and the frequency of the frequency sweep signal are set to proportional; and a radar transceiver, providing a transmit signal and/or processing an echo signal according to the swept frequency signal.

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