CN211669572U - Clock quality monitoring circuit - Google Patents
Clock quality monitoring circuit Download PDFInfo
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- CN211669572U CN211669572U CN202020371210.2U CN202020371210U CN211669572U CN 211669572 U CN211669572 U CN 211669572U CN 202020371210 U CN202020371210 U CN 202020371210U CN 211669572 U CN211669572 U CN 211669572U
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Abstract
The utility model provides a clock quality monitoring circuit, include: a phase-locked loop, a phase adjuster and a comparator; the input end of the phase-locked loop is used for inputting a clock signal to be measured; the phase adjuster is used for shifting the phase of the measured clock signal output by the phase-locked loop forward by a preset phase to obtain a first displacement signal, and is used for shifting the phase of the measured clock signal output by the phase-locked loop backward by the preset phase to obtain a second displacement signal; the comparator is used for sampling the measured clock shift signal to obtain a first sampling signal and a second sampling signal when the first shift signal and the second shift signal meet corresponding first preset conditions and second preset conditions; and judging whether the values of the first sampling signal and the second sampling signal are preset values or not, and outputting prompt information for representing the abnormity of the measured clock signal when the values of the first sampling signal and the second sampling signal are not preset values, so that the abnormity of the quality of the clock signal can be timely monitored.
Description
Technical Field
The utility model relates to an electronic circuit technical field, concretely relates to clock quality monitoring circuit.
Background
The clock is a very important part of the electronic product system, and almost all electronic components operate synchronously under the action of the clock. Therefore, the quality of the clock signal directly affects the stability of the electronic product system. At present, electronic product systems generally monitor the quality of clock signals.
In the prior art, clock signal quality monitoring is mainly realized by calculating an average value of clock signal frequency in a period of time. Specifically, the average value of the frequency of the clock signal over a period of time is calculated, and when the average value exceeds a certain threshold range, the clock signal is abnormal. However, such an implementation mode is that after the quality of the clock signal becomes poor, the clock signal can be monitored after a period of time, and the monitoring effectiveness is poor.
Therefore, it is desirable to provide a clock quality real-time monitoring circuit, which can timely monitor the quality abnormality of the clock signal compared with the prior art.
SUMMERY OF THE UTILITY MODEL
In view of this, embodiments of the present invention provide a clock quality monitoring circuit to realize reliable monitoring of abnormal signal condition of the measured clock signal.
In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:
a clock quality monitoring circuit comprising:
the phase-locked loop comprises a phase-locked loop, a phase adjuster, a signal collector and a comparator;
the input end of the phase-locked loop is used for inputting a clock signal to be measured;
the input end of the phase adjuster is connected with the output end of the phase-locked loop and is used for outputting a measured clock signal with a phase shifted forward by a preset phase, recording the measured clock signal as a first displacement signal, and outputting a measured clock signal with a phase shifted backward by the preset phase, recording the measured clock signal as a second displacement signal;
the input end of the signal collector is connected with the output end of the phase adjuster, when the first displacement signal meets a first preset condition, the measured clock signal is sampled to obtain a first sampling signal, and when the second displacement signal meets a second preset condition, the measured clock signal is sampled to obtain a second sampling signal;
and the input end of the comparator is connected with the output end of the signal collector and is used for judging whether the values of the first sampling signal and the second sampling signal are preset values or not.
Optionally, in the clock quality monitoring circuit, the signal collector includes:
a first sampler and a second sampler;
the first sampler is to: when the first displacement signal meets a first preset condition, sampling the measured clock signal to obtain a first sampling signal;
the second sampler to: and when the second displacement signal meets a second preset condition, sampling the measured clock signal to obtain a second sampling signal.
Optionally, in the clock quality monitoring circuit, the phase adjuster includes:
a first phase adjuster and a second phase adjuster;
the input end of the first adjuster is connected with the output end of the phase-locked loop and is used for advancing the phase of the slowly-changed measured clock signal output by the phase-locked loop by a preset phase to obtain a first displacement signal;
and the input end of the second regulator is connected with the output end of the phase-locked loop and is used for shifting the phase of the slowly-changed measured clock signal output by the phase-locked loop back by a preset phase to obtain a second displacement signal.
Optionally, in the clock quality monitoring circuit, the signal collector is specifically configured to sample the measured clock signal to obtain a first sampling signal when a rising edge and/or a falling edge of the first displacement signal arrives, and sample the measured clock signal to obtain a second sampling signal when a rising edge and/or a falling edge of the second displacement signal arrives.
Optionally, in the clock quality monitoring circuit, when the first preset condition is that a rising edge of a first shift signal arrives and the second preset condition is that a rising edge of a second shift signal arrives, the comparator is specifically configured to:
judging whether the values of the first sampling signals are all first preset values;
and judging whether the values of the second sampling signals are all second preset values.
The embodiment of the utility model provides an above-mentioned scheme, at first through the phase-locked loop to being measured clock signal VInSmoothing to obtain a slowly-changed clock signal to be measured, and then respectively shifting the phase of the slowly-changed clock signal to be measured by a preset phase △ phi and a preset phase △ phi through a phase adjuster to obtain a first shift signal and a second shift signal, wherein the value of the preset phase △ phi can be determined according to the clock signal to be measured VInAnd the value of said preset phase should be adjusted at said measured clock signal VInIs not greater than the measured clock signal VInThe maximum jitter value of. And then respectively detecting the states of the first displacement signal and the second displacement signal, sampling the measured clock signal to obtain a first sampling signal when the first displacement signal meets a first preset condition, sampling the measured clock signal to obtain a second sampling signal when the second displacement signal meets a second preset condition, and finally judging the values of the first sampling signal and the second sampling signal in real time through a comparator. When the values of the two sampling signals are not preset values, the clock signal V to be measured is indicatedInAn anomaly (e.g., a jitter or missed beat) occurs. The circuit provided by the embodiment is simple to realize, can timely monitor the clock signal quality abnormity, and has good effectiveness.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a clock quality monitoring circuit disclosed in an embodiment of the present application;
FIG. 2 is a schematic diagram showing the variation of the signals involved in the clock quality monitoring circuit when the measured clock signal is normal;
FIG. 3 is a schematic diagram showing the variation of the signals involved in the clock quality monitoring circuit when the measured clock signal is abnormal;
fig. 4 is a schematic structural diagram of a clock quality monitoring circuit according to another embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Example 1:
referring to fig. 1, fig. 1 is a schematic structural diagram of a clock quality monitoring circuit disclosed in an embodiment of the present application.
In the technical solution disclosed in the embodiment of the present application, the clock quality monitoring circuit described with reference to fig. 1 includes a phase-locked loop 100, a phase adjuster 200, a comparator 300, and a signal collector 400;
the input end of the phase-locked loop 100 is used for inputting a clock signal to be measured, and the phase-locked loop is used for acquiring a clock signal V to be measuredInFor the clock signal V to be measuredInAfter the smoothing treatmentOutputting a slowly varying clock signal V0；
The input terminal of the phase adjuster 200 is connected to the output terminal of the phase locked loop for adjusting the slowly varying clock signal V0Performing a phase adjustment comprising applying the ramp clock signal V0Performing phase forward shift and phase backward shift, specifically, during the adjustment, shifting the phase of the measured clock signal forward by a preset phase △ phi to obtain a first shift signal V1-For shifting the phase of the measured clock signal backward by a predetermined phase △ phi to obtain a second shift signal V1+Wherein the value of the predetermined phase △ phi can be determined according to the measured clock signal VInIs adjusted as long as it is ensured that the value of the preset phase △ phi is larger than the measured clock signal V under the current circumstancesInThe maximum jitter value of (2). For example, if the clock signal V to be measuredInIs 50ps, then the value of the predetermined phase delta phi needs to be larger than 50 ps.
The input end of the signal collector 400 is connected to the output end of the phase adjuster, and is configured to: when the first displacement signal V1-When a first preset condition is met, sampling is carried out on the clock signal to be measured to obtain a first sampling signal V2When the second displacement signal V is1+When a second preset condition is met, the clock signal to be measured is sampled to obtain a second sampling signal V3；
The input terminal of the comparator 300 is connected to the output terminal of the signal collector 400, and two comparison circuits may be included therein for respectively determining the first sampling signal V2And a second sampling signal V3If the value is not the preset value, outputting prompt information for representing the abnormity of the measured clock signal.
In this scheme, the setting mode of the first preset condition and the second preset condition may be set according to a user requirement, for example, it may refer to a rising edge or a falling edge of a signal, and when the first preset condition and the second preset condition arrive, the measured clock output by the phase-locked loop is measuredThe signal is sampled. In this scheme, the first preset condition and the second preset condition may refer to when the set time of the first displacement signal arrives and when the set time of the second displacement signal arrives; in the scheme, the rising edges of the first displacement signal and the second displacement signal are used as corresponding first preset condition and second preset condition, namely, when the rising edge of the first displacement signal arrives and the rising edge of the second displacement signal arrives, the clock signal output by the phase-locked loop and measured by the phase-locked loop is sampled to obtain a first sampling signal V2Sampling the clock signal to be measured output by the phase-locked loop to obtain a second sampling signal V3In practical use, if the measured clock signal is normal, the value V of the first sampling signal is collected2And a second sampling signal V3Will satisfy a predetermined rule by determining the first sampling signal V2And a second sampling signal V3Can judge whether the measured clock signal is abnormal or not by judging whether the value of (V) is a preset value or not, and when the first sampling signal V is abnormal2And/or the second sampling signal V3And when the clock signal is not a preset value, outputting prompt information for representing the abnormity of the measured clock signal, otherwise, indicating that the measured clock signal is normal.
In this embodiment, the preset rule may be to determine the first sampling signal V2And a second sampling signal V3Whether the preset value is a preset value or not is different according to different preset conditions, and taking the preset condition as a rising edge as an example, the preset rule specifically includes: first sampling signal V2Is kept to 0, the second sampling signal V3The value of (d) remains 1. I.e. when the clock signal V is measured, see fig. 2InIn normal condition, the first sampling signal V2Is always 0, the second sampling signal V3Has a value of 1. When the value of the first sampling signal is 0, the second sampling signal V3When the value of (1) is greater than the first threshold value, the first sampling signal V2And said second sampling signal V3Satisfies the predetermined rule, see fig. 3, when the clock signal V is measuredInWhen the abnormal condition occurs, the abnormal condition is detected,the first sampling signal V2Will become 1 or the second sampling signal V3It becomes 0. Therefore, as long as the condition (first sampling signal V) is not satisfied20 and the second sampling signal V31), the comparator considers the measured clock signal V as the measured clock signal VInAn exception occurs.
The scheme for monitoring the clock quality in real time provided by the embodiment includes that firstly, a clock signal V to be measured is subjected to phase-locked loopInSmoothing to obtain slowly-changed clock signal V to be measured0Then, the phase adjuster respectively shifts the phase of the slowly-changed measured clock signal forward by a preset phase △ phi and backward by a preset phase △ phi to obtain a first shift signal V1-And a second displacement signal V1+Wherein the value of the predetermined phase △ phi can be determined according to the measured clock signal VInAnd the value of the preset phase should be larger than the value of the clock signal V to be measuredInThe maximum jitter value of. Detecting the signal states of the first displacement signal and the second displacement signal, and performing edge sampling on the measured clock signal when the first displacement signal meets a first preset condition and the second displacement signal meets a second preset condition to obtain a first sampling signal V2Edge sampling is carried out on the measured clock signal to obtain a second sampling signal V3Finally, the first sampling signal V is judged in real time through a comparator2And a second sampling signal V3The value of (c). When the values of the two sampling signals are not in the preset value range, the clock signal V to be measured is indicatedInAn anomaly (e.g., a jitter or missed beat) occurs. The circuit provided by the embodiment is simple to realize, can timely monitor the clock signal quality abnormity, and has good effectiveness.
In the technical solution disclosed in the embodiment of the present application, the structure of the comparator may be selected according to a user requirement, for example, referring to fig. 4, in the technical solution disclosed in the embodiment of the present application, the signal collector 400 may include:
a first sampler 400a, a second sampler 400 b;
the first sampler 400a is configured to: when the first displacement signal satisfies the firstSampling the measured clock signal to obtain a first sampling signal V under a preset condition2；
The second sampler 400b is configured to: when the second displacement signal meets a second preset condition, the measured clock signal is sampled to obtain a second sampling signal V3。
The phase adjuster 200 may be implemented by one independent phase adjuster or by two phase adjusters, for example, referring to fig. 4, in which case the phase adjuster may comprise a first phase adjuster 200a and a second phase adjuster 200b, the first phase adjuster 200a being used for a slowly varying measured clock signal V to be output via the phase locked loop0The phase is shifted by a predetermined phase △ phi to obtain a first shift signal V1-The second adjuster 200b is used for adjusting the slowly-varying measured clock signal V output via the phase-locked loop0The phase is shifted backward by a preset phase △ phi to obtain a second shift signal V1+。
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A clock quality monitoring circuit, comprising:
the phase-locked loop comprises a phase-locked loop, a phase adjuster, a signal collector and a comparator;
the input end of the phase-locked loop is used for inputting a clock signal to be measured;
the input end of the phase adjuster is connected with the output end of the phase-locked loop and is used for outputting a measured clock signal with a phase shifted forward by a preset phase, recording the measured clock signal as a first displacement signal, and outputting a measured clock signal with a phase shifted backward by the preset phase, recording the measured clock signal as a second displacement signal;
the input end of the signal collector is connected with the output end of the phase adjuster, when the first displacement signal meets a first preset condition, the measured clock signal is sampled to obtain a first sampling signal, and when the second displacement signal meets a second preset condition, the measured clock signal is sampled to obtain a second sampling signal;
and the input end of the comparator is connected with the output end of the signal collector and is used for judging whether the values of the first sampling signal and the second sampling signal are preset values or not.
2. The clock quality monitoring circuit of claim 1, wherein the signal collector comprises:
a first sampler and a second sampler;
the first sampler is to: when the first displacement signal meets a first preset condition, sampling the measured clock signal to obtain a first sampling signal;
the second sampler to: and when the second displacement signal meets a second preset condition, sampling the measured clock signal to obtain a second sampling signal.
3. The clock quality monitoring circuit of claim 1, wherein the phase adjuster comprises:
a first phase adjuster and a second phase adjuster;
the input end of the first phase adjuster is connected with the output end of the phase-locked loop and is used for shifting the phase of the slowly-changed measured clock signal output by the phase-locked loop forward by a preset phase to obtain a first displacement signal;
and the input end of the second phase adjuster is connected with the output end of the phase-locked loop and is used for shifting the phase of the slowly-changed measured clock signal output by the phase-locked loop back by a preset phase to obtain a second displacement signal.
4. The clock quality monitoring circuit according to claim 1, wherein the signal collector is specifically configured to sample the clock signal under measurement to obtain a first sampled signal when a rising edge and/or a falling edge of the first shift signal arrives, and sample the clock signal under measurement to obtain a second sampled signal when a rising edge and/or a falling edge of the second shift signal arrives.
5. The clock quality monitoring circuit of claim 4, wherein when the first predetermined condition is arrival of a rising edge of a first shift signal and the second predetermined condition is arrival of a rising edge of a second shift signal, the comparator is specifically configured to:
judging whether the values of the first sampling signals are all first preset values;
and judging whether the values of the second sampling signals are all second preset values.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111240402A (en) * | 2020-03-19 | 2020-06-05 | 合肥新港海岸科技有限公司 | A clock quality monitoring circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111240402A (en) * | 2020-03-19 | 2020-06-05 | 合肥新港海岸科技有限公司 | A clock quality monitoring circuit |
| CN111240402B (en) * | 2020-03-19 | 2024-11-19 | 合肥新港海岸科技有限公司 | A clock quality monitoring circuit |
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