CN211669516U - Novel double-frequency electric wave clock - Google Patents

Abstract

The utility model provides a novel dual-frenquency electric wave clock, include: the antenna comprises an antenna receiving module, a core processing module, a display module and a power supply module; the antenna receiving module is used for receiving clock electric waves sent by a national time service center and an atomic clock, and comprises an antenna loop receiving circuit, a double-frequency crystal oscillator circuit, a key awakening circuit and a double-frequency receiving chip; the display module is used for displaying correct time information and comprises a liquid crystal display screen, and the output end of the core processing module is connected with the input end of the liquid crystal display screen; the power module includes chargeable call and voltage stabilizing circuit, chargeable call with the voltage stabilizing circuit electricity is connected and is the system power supply, the utility model discloses the structure is succinct, and the suitability is high, can be used to a plurality of frequency to receive to adopt awakening circuit to reduce the circuit consumption.

Description

A new type of dual-frequency radio clock

technical field

The utility model relates to the technical field of clock equipment, in particular to a novel dual-frequency radio clock.

Background technique

The radio clock is a precise timing instrument based on wireless long-wave signal communication. In 2007, the National Time Service Center of the Central Palace Museum established a BPC time code radio wave transmission center with a base frequency of 68.5KHz in Shangqiu City, Henan Province. After several years of development, the long-wave timing technology has become more and more mature. After transmitting, at the receiving end, the antenna and frequency selective amplifier circuit are used for demodulation and decoding, and the accurate time signal is obtained and displayed. The existing radio clocks have poor anti-interference ability, low applicability to a single acceptance frequency, and high circuit power consumption.

To sum up, how to provide a novel dual-frequency radio clock with simple structure, high applicability, and low power consumption for receiving multiple frequencies is a problem to be solved by those skilled in the art.

Utility model content

In view of the above-mentioned problems and demands, this solution proposes a new type of dual-frequency radio clock, which can solve the above-mentioned technical problems by adopting the following technical solutions.

In order to achieve the above purpose, the utility model provides the following technical solutions: a novel dual-frequency radio clock, comprising: an antenna receiving module, a core processing module, a display module and a power supply module;

The antenna receiving module is used to receive the clock radio waves sent by the National Time Service Center and the atomic clock. The antenna receiving module includes an antenna ring receiving circuit, a dual-frequency crystal oscillator circuit, a button wake-up circuit and a dual-frequency receiver chip. The button wake-up circuit includes a a selection switch, the antenna loop receiving circuit, the dual-frequency crystal oscillator circuit and the key-press wake-up circuit are all electrically connected to the dual-frequency receiving chip, and the antenna receiving module is electrically connected to the core processing module;

The core processing module includes a core processor; the display module is used to display correct time information, the display module includes a liquid crystal display screen, and an output end of the core processor is connected to an input end of the liquid crystal display screen;

The power module includes a rechargeable battery and a voltage stabilizing circuit, and the rechargeable battery is electrically connected to the voltage stabilizing circuit to supply power to the system.

Further, the model of the dual-frequency receiving chip is CME6005.

Further, the antenna loop receiving circuit includes an antenna loop, a capacitor C1 and a capacitor C2, the capacitor C1 and the capacitor C2 are connected in parallel at both ends of the antenna loop to form an oscillation receiving circuit, and the capacitor C2 is connected in parallel at the two ends of the antenna loop. on pins 6 and 7 of the dual-frequency receiving chip.

Further, the dual-frequency crystal oscillator circuit includes a crystal oscillator X1, a crystal oscillator X2 and a compensation capacitor C3, and the crystal oscillator X1 and the crystal oscillator X2 are connected in parallel on pins 2 and 4 of the dual-frequency receiving chip, so The capacitor C3 is connected in parallel to the pins 1 and 2 of the dual-frequency receiving chip.

Further, the static contact of the selection switch is connected to the pin 12 of the dual-frequency receiving chip, one moving contact of the selection switch is grounded, and the other moving point of the selection switch is connected to the power supply, When the selection switch is grounded, that is, connected to a low level, the dual-frequency receiving chip is in a receiving mode, and when the selection switch is connected to a power supply, that is, a high level, the dual-frequency receiving chip is in a sleep mode.

Further, the output port of the dual-frequency receiving chip is connected to the timer interface of the core processor, and the timer performs BPC decoding on the encoded signal sent by the dual-frequency receiving chip; The output port is connected to the AGC lock port of the dual-frequency receiving chip to control the AGC automatic gain action of the dual-frequency receiving chip.

Further, if the output port of the core processor is at a high level, the AGC automatic gain works normally, and if the output port of the core processor is at a low level, the response of the AGC automatic gain is static to avoid external pulse interference.

Further, the model of the liquid crystal display screen is LCM12864, and the liquid crystal display screen and the core processor adopt a parallel control communication mode.

Further, the voltage regulator circuit includes a voltage regulator chip, an anti-backflow diode D1, a capacitor C6, a capacitor C7, a capacitor C8 and a resistor R2, and the positive electrode of the anti-backflow diode D1 is connected to the negative electrode of the rechargeable battery. The anode of the anti-backflow diode D1 is connected to one end of the capacitor C7 and one end of the resistor R2, and the other end of the capacitor C7 is connected to the anode of the rechargeable battery, one end of the capacitor C6, and the voltage regulator. Pin 2 and pin 4 of the chip are grounded, and the other end of the capacitor C6 is connected to the other end of the resistor R2 and then connected to the pin 1 of the voltage regulator chip.

The beneficial effect of the utility model is that the utility model has a simple structure, high applicability, can be used for multiple frequency reception, and the wake-up button circuit can make the system in a dormant state when not in use, thereby reducing circuit power consumption.

Hereinafter, the preferred embodiments for implementing the present invention will be described in more detail with reference to the accompanying drawings, so that the features and advantages of the present invention can be easily understood.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the accompanying drawings of the embodiments of the present invention will be briefly introduced hereinafter. The accompanying drawings are only used to illustrate some embodiments of the present invention, rather than limiting all the embodiments of the present invention thereto.

FIG. 1 is a schematic diagram of the circuit interface of the antenna receiving module in the utility model.

FIG. 2 is a schematic diagram of a circuit interface of a display module in the utility model.

FIG. 3 is a schematic diagram of the circuit interface of the voltage stabilizing circuit in the utility model.

Detailed ways

In order to make the purpose, technical solutions and advantages of the technical solutions of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the specific embodiments of the present invention. The same reference numbers in the figures represent the same parts. It should be noted that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

As shown in Figures 1 to 3, the present invention provides a new dual-frequency radio clock with simple structure, high applicability, which can be used for receiving multiple frequencies and has low power consumption. The new dual-frequency radio clock includes: : Antenna receiving module, core processing module, display module and power supply module. The antenna receiving module is used to receive the clock radio waves sent by the National Time Service Center and the atomic clock. The antenna receiving module includes an antenna ring receiving circuit, a dual-frequency crystal oscillator circuit, a button wake-up circuit and a dual-frequency receiver chip. The button wake-up circuit includes a selection switch, the antenna loop receiving circuit, the dual-frequency crystal oscillator circuit and the key-press wake-up circuit are all electrically connected to the dual-frequency receiving chip, the model of the dual-frequency receiving chip is CME6005, and the antenna loop receiving circuit Including an antenna loop, a capacitor C1 and a capacitor C2, the capacitor C1 and the capacitor C2 are connected in parallel at both ends of the antenna loop to form an oscillation receiving circuit, and the capacitor C2 is connected in parallel with the pin 6 of the dual-frequency receiving chip and pin 7; the dual-frequency crystal oscillator circuit includes a crystal oscillator X1, a crystal oscillator X2 and a compensation capacitor C3, and the crystal oscillator X1 and the crystal oscillator X2 are connected in parallel on pins 2 and 4 of the dual-frequency receiving chip , the capacitor C3 is connected in parallel on the pins 1 and 2 of the dual-frequency receiving chip; the static contact of the selection switch is connected with the pin 12 of the dual-frequency receiving chip, and the selection switch One moving contact of the selector switch is grounded, and the other moving contact of the selector switch is connected to the power supply. When the selector switch is grounded and connected to a low level, the dual-frequency receiver chip is in the receiving mode, and the selector switch is connected to the power source. When the level is high, the dual-frequency receiving chip is in a sleep mode. The antenna receiving module is electrically connected to the core processing module, the output port of the dual-frequency receiving chip is connected to the timer interface of the core processor, and the timer is used for encoding signals sent by the dual-frequency receiving chip. Perform BPC decoding; the output port of the core processor is connected to the AGC lock port of the dual-frequency receiving chip to control the AGC automatic gain action of the dual-frequency receiving chip, wherein the output port of the core processor is a high-power Normally, the AGC automatic gain works normally, and the output port of the core processor is at a low level, and the response of the AGC automatic gain is static to avoid external pulse interference.

The core processing module includes a core processor; the display module is used to display correct time information, and the display module includes a liquid crystal display screen. As shown in FIG. 2 , the output end of the core processor is connected to the liquid crystal display. The input end of the screen is connected, the model of the liquid crystal display screen is LCM12864, and the liquid crystal display screen and the core processor adopt a parallel control communication mode.

As shown in FIG. 3 , the power module includes a rechargeable battery and a voltage stabilizing circuit, the rechargeable battery is electrically connected to the voltage stabilizing circuit to supply power to the system, and the voltage stabilizing circuit includes a voltage stabilizing chip and an anti-backflow diode D1 , capacitor C6, capacitor C7, capacitor C8 and resistor R2, the positive electrode of the anti-backflow diode D1 is connected to the negative electrode of the rechargeable battery, and the positive electrode of the anti-backflow diode D1 is connected to one end of the capacitor C7 and the resistor. One end of R2 is connected to the ground, the other end of the capacitor C7 is grounded with the positive electrode of the rechargeable battery, one end of the capacitor C6, pins 2 and 4 of the voltage regulator chip, and the other end of the capacitor C6 is grounded. One end is connected to the other end of the resistor R2 and then connected to the pin 1 of the voltage regulator chip.

In this embodiment, the quartz crystal oscillator in the dual-frequency crystal oscillator circuit is to improve the frequency selectivity, and it plays a role of serial resonance with the input frequency on the entire circuit.

It should be noted that the embodiments described in the present invention are only the preferred ways to realize the present invention, and those which belong to the overall concept of the present invention, but are only obvious changes, should all fall within the protection scope of the present invention.

Claims (9)

1. A novel dual-frequency electric wave clock is characterized by comprising: the antenna comprises an antenna receiving module, a core processing module, a display module and a power supply module;

the antenna receiving module is used for receiving clock electric waves sent by a national time service center and an atomic clock, the antenna receiving module comprises an antenna loop receiving circuit, a dual-frequency crystal oscillator circuit, a key awakening circuit and a dual-frequency receiving chip, the key awakening circuit comprises a selection switch, the antenna loop receiving circuit, the dual-frequency crystal oscillator circuit and the key awakening circuit are all electrically connected with the dual-frequency receiving chip, and the antenna receiving module is electrically connected with the core processing module;

the core processing module comprises a core processor; the display module is used for displaying correct time information and comprises a liquid crystal display screen, and the output end of the core processor is connected with the input end of the liquid crystal display screen;

the power supply module comprises a rechargeable storage battery and a voltage stabilizing circuit, and the rechargeable storage battery is electrically connected with the voltage stabilizing circuit to supply power to the system.

2. The novel dual-frequency wave clock according to claim 1, wherein the type of the dual-frequency receiving chip is CME 6005.

3. The novel dual-frequency wave clock as claimed in claim 2, wherein the antenna loop receiving circuit comprises an antenna loop, a capacitor C1 and a capacitor C2, the capacitor C1 and the capacitor C2 are connected in parallel to form an oscillation receiving circuit at two ends of the antenna loop, and the capacitor C2 is connected in parallel to the pin 6 and the pin 7 of the dual-frequency receiving chip.

4. The novel dual-frequency wave clock as claimed in claim 2, wherein the dual-frequency crystal oscillator circuit comprises a crystal oscillator X1, a crystal oscillator X2 and a compensation capacitor C3, the crystal oscillator X1 and the crystal oscillator X2 are connected in parallel to the pin 2 and the pin 4 of the dual-frequency receiving chip, and the capacitor C3 is connected in parallel to the pin 1 and the pin 2 of the dual-frequency receiving chip.

5. The novel dual-frequency wave clock as claimed in claim 2, wherein the fixed contact of the selector switch is connected to the pin 12 of the dual-frequency receiving chip, one movable contact of the selector switch is grounded, the other movable contact of the selector switch is connected to the power supply, when the selector switch is grounded, i.e., at a low level, the dual-frequency receiving chip is in a receiving mode, and when the selector switch is connected to the power supply, i.e., at a high level, the dual-frequency receiving chip is in a sleep mode.

6. The novel dual-frequency wave clock as claimed in claim 2, wherein the output port of the dual-frequency receiving chip is connected to the timer interface of the core processor, and the timer performs BPC decoding on the encoded signal transmitted by the dual-frequency receiving chip; and the output port of the core processor is connected with the AGC locking port of the dual-frequency receiving chip to control the AGC automatic gain action of the dual-frequency receiving chip.

7. The novel dual-frequency wave clock as claimed in claim 6, wherein the AGC is normally operated when the output port of the core processor is at a high level, and the reaction of the AGC is quiescent to avoid external impulse interference when the output port of the core processor is at a low level.

8. The novel dual-frequency electric wave clock as claimed in claim 1, wherein the liquid crystal display screen is LCM12864, and the liquid crystal display screen and the core processor adopt a parallel control communication mode.

9. The novel dual-frequency wave clock as claimed in claim 1, wherein the voltage-stabilizing circuit comprises a voltage-stabilizing chip, a back-flow prevention diode D1, a capacitor C6, a capacitor C7, a capacitor C8 and a resistor R2, wherein the positive electrode of the back-flow prevention diode D1 is connected with the negative electrode of the rechargeable battery, the positive electrode of the back-flow prevention diode D1 is connected with one end of the capacitor C7 and one end of the resistor R2, the other end of the capacitor C7 is connected with the positive electrode of the rechargeable battery, one end of the capacitor C6, a pin 2 and a pin 4 of the voltage-stabilizing chip, and the other end of the capacitor C6 is connected with the other end of the resistor R2 and then connected with the pin 1 of the voltage-stabilizing chip.

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