CN211352181U - Multichannel DA signal synchronizer based on FPGA - Google Patents
Multichannel DA signal synchronizer based on FPGA Download PDFInfo
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- CN211352181U CN211352181U CN202020484193.3U CN202020484193U CN211352181U CN 211352181 U CN211352181 U CN 211352181U CN 202020484193 U CN202020484193 U CN 202020484193U CN 211352181 U CN211352181 U CN 211352181U
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Abstract
The utility model discloses a multichannel DA signal synchronizer based on FPGA, include: the synchronous plate and two or more DAC plates; the synchronous board is provided with a first FPGA signal unit and a first clock chip signal unit; the first clock chip signal unit is in one-way signal connection with the first FPGA signal unit; the DAC board is provided with a second FPGA signal unit, a second clock chip signal unit and two or more DA chip signal units; the second clock chip signal unit is in one-way signal connection with the second FPGA signal unit; the second clock chip signal unit is respectively connected with two or more DA chip signal units in a one-way signal mode; the two or more DA chip signal units are respectively provided with one end connected with the corresponding signal channel; the first FPGA signal unit is in bidirectional signal connection with the second FPGA signal unit and is used for signal handshake interaction; and the first clock chip signal unit is in one-way signal connection with the second clock chip signal unit.
Description
Technical Field
The utility model relates to a signal synchronizer, concretely relates to multichannel DA signal synchronizer and method based on FPGA.
Background
With the rapid development of signal and information processing technologies, multichannel signal generation technologies are widely used in the fields of military, industry, aviation, and the like. DDS is an english abbreviation of "direct digital frequency synthesis", which is a technique for directly synthesizing a desired waveform with a given reference frequency starting from a phase concept. The requirement for synchronization of the generation of multi-channel DA signals is constantly increasing. In the existing multichannel DA signal synchronization application, the hard synchronization method mainly adopts an independent clock chip to provide a clock, and the generated DDS data is also independently generated and then sent to the DA chip.
The synchronization of the DA signal is critical: one is the synchronization of the clocks and the other is the synchronization of the generation of the DDS signal. The independent clock chip is adopted to provide the clock, the clock phase cannot be guaranteed to be fixed every time after the clock chip is electrified, and the phase difference among the clocks of a plurality of clock chips can be changed after the clock chips are electrified repeatedly. Because the generation of multi-path DDS signals needs a plurality of FPGA chips, the DDS data generated by the chips which run independently can not be generated at the same time due to inconsistent starting sequence.
SUMMERY OF THE UTILITY MODEL
The utility model discloses the technical problem that will solve is how to realize the DDS signal phase synchronization of sending, and aim at provides a multichannel DA signal synchronizer and method based on FPGA, solves the problem of DDS signal phase synchronization. The utility model discloses can be used to the multichannel DA signal phase place synchronization field that high integrated level, the number of channels are many, the phase accuracy requires height.
The utility model discloses a following technical scheme realizes:
a multichannel DA signal synchronizer based on FPGA includes: the synchronous plate and two or more DAC plates;
the synchronous board is provided with a first FPGA signal unit and a first clock chip signal unit; the first clock chip signal unit is in one-way signal connection with the first FPGA signal unit;
the DAC board is provided with a second FPGA signal unit, a second clock chip signal unit and two or more DA chip signal units; the second clock chip signal unit is in one-way signal connection with the second FPGA signal unit; the second clock chip signal unit is respectively connected with two or more DA chip signal units in a one-way signal mode; the two or more DA chip signal units are respectively provided with one end connected with the corresponding signal channel;
the first FPGA signal unit is in bidirectional signal connection with the second FPGA signal unit and is used for signal handshake interaction; and the first clock chip signal unit is in one-way signal connection with the second clock chip signal unit.
Furthermore, the operating clock frequency between the first clock chip signal unit and the first FPGA signal unit is 100 Mhz; the running clock frequency between the second clock chip signal unit and the second FPGA signal unit is 100Mhz or 300 Mhz; the operating clock frequency between the second clock chip signal unit and the two or more DA chip signal units is 100 Mhz; the running clock frequency between the first clock chip signal unit and the second clock chip signal unit is 100 Mhz.
Further, the first clock chip and the second clock chip both use the same source clock.
Further, the first clock chip and the second clock chip are both LMK04828 clock chips.
Further, the two or more DA chip signal units are 4 DA chip signal units.
Further, the two or more DAC plate signal units are 4 DAC plate signal units.
Further, the DA chip is a DAC9739 chip.
All clock chips use the same source clock.
Compared with the prior art, the utility model, following advantage and beneficial effect have:
the utility model relates to an adopt FPGA to realize multichannel DA chip phase synchronization, all interact through the signal of shaking hands in the production step of clock and signal, ensure that each flow all accomplishes the reentrant next flow after. The phase of the clock chip is unstable after the configuration is completed, and the design automatically performs one SYNC operation after the configuration of the LMK04828 is completed to ensure that the phase can be relatively fixed after each power-on.
All clocks of the whole system are homologous clocks, so that the processing of signals in the chip and between the chips can be synchronously carried out. The problem caused by phase difference of the operation clock is effectively avoided, the DDS enable command can be ensured to arrive at the same time when the synchronous board sends the DDS enable command to the DAC board, and finally phase synchronization of the sent DDS signals is realized.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention:
fig. 1 is a schematic diagram of the overall system framework.
Detailed Description
To make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the following examples and drawings, and the exemplary embodiments and descriptions thereof of the present invention are only used for explaining the present invention, and are not intended as limitations of the present invention.
Examples
As shown in FIG. 1, the design adopts an FPGA + LMK04828+ DAC9739 architecture to realize the synchronization of the multi-channel DA signals, and the error accuracy of the signals can reach +/-5 degrees under 1 GHz.
The utility model comprises a synchronous board and two or more DAC boards; the synchronous board is provided with a first FPGA signal unit and a first clock chip signal unit; the first clock chip signal unit is in one-way signal connection with the first FPGA signal unit;
the DAC board is provided with a second FPGA signal unit, a second clock chip signal unit and two or more DA chip signal units; the second clock chip signal unit is in one-way signal connection with the second FPGA signal unit; the second clock chip signal unit is respectively connected with two or more DA chip signal units in a one-way signal mode; the two or more DA chip signal units are respectively provided with one end connected with the corresponding signal channel;
the first FPGA signal unit is in bidirectional signal connection with the second FPGA signal unit and is used for signal handshake interaction; and the first clock chip signal unit is in one-way signal connection with the second clock chip signal unit.
Furthermore, the operating clock frequency between the first clock chip signal unit and the first FPGA signal unit is 100 Mhz; the running clock frequency between the second clock chip signal unit and the second FPGA signal unit is 100Mhz or 300 Mhz; the operating clock frequency between the second clock chip signal unit and the two or more DA chip signal units is 100 Mhz; the running clock frequency between the first clock chip signal unit and the second clock chip signal unit is 100 Mhz.
The first clock chip and the second clock chip both use homologous clocks; further, the first clock chip and the second clock chip are both LMK04828 clock chips.
Further, the two or more DA chip signal units are 4 DA chip signal units.
Further, the two or more DAC plate signal units are 4 DAC plate signal units.
Further, the DA chip is a DAC9739 chip.
All clock chips use the same source clock.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A multichannel DA signal synchronizer based on FPGA is characterized by comprising a synchronization board and two or more DAC boards;
the synchronous board is provided with a first FPGA signal unit and a first clock chip signal unit; the first clock chip signal unit is in one-way signal connection with the first FPGA signal unit;
the DAC board is provided with a second FPGA signal unit, a second clock chip signal unit and two or more DA chip signal units; the second clock chip signal unit is in one-way signal connection with the second FPGA signal unit; the second clock chip signal unit is respectively connected with two or more DA chip signal units in a one-way signal mode; the two or more DA chip signal units are respectively provided with one end connected with the corresponding signal channel;
the first FPGA signal unit is in bidirectional signal connection with the second FPGA signal unit and is used for signal handshake interaction; and the first clock chip signal unit is in one-way signal connection with the second clock chip signal unit.
2. The device of claim 1, wherein the operating clock frequency between the first clock chip signal unit and the first FPGA signal unit is 100 Mhz; the running clock frequency between the second clock chip signal unit and the second FPGA signal unit is 100Mhz or 300 Mhz; the operating clock frequency between the second clock chip signal unit and the two or more DA chip signal units is 100 Mhz; the running clock frequency between the first clock chip signal unit and the second clock chip signal unit is 100 Mhz.
3. The FPGA-based multi-channel DA signal synchronizing device of claim 1 wherein the first clock chip and the second clock chip both use a same source clock.
4. The FPGA-based multi-channel DA signal synchronization device of claim 3, wherein the first clock chip and the second clock chip are both LMK04828 clock chips.
5. The FPGA-based multi-channel DA signal synchronizing device of claim 1, wherein the two or more DA chip signal units are 4 DA chip signal units.
6. The FPGA-based multi-channel DA signal synchronizing device of claim 1 wherein the two or more DAC plate signal units are 4 DAC plate signal units.
7. The FPGA-based multi-channel DA signal synchronizing device of claim 1 wherein the DA chips are DAC9739 chips.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202020484193.3U CN211352181U (en) | 2020-04-03 | 2020-04-03 | Multichannel DA signal synchronizer based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111277265A (en) * | 2020-04-03 | 2020-06-12 | 四川鸿创电子科技有限公司 | Multi-channel DA signal synchronization device and method based on FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111277265A (en) * | 2020-04-03 | 2020-06-12 | 四川鸿创电子科技有限公司 | Multi-channel DA signal synchronization device and method based on FPGA |
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