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CN211297117U - Multilayer circuit board structure - Google Patents

Multilayer circuit board structure Download PDF

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Publication number
CN211297117U
CN211297117U CN201921723788.3U CN201921723788U CN211297117U CN 211297117 U CN211297117 U CN 211297117U CN 201921723788 U CN201921723788 U CN 201921723788U CN 211297117 U CN211297117 U CN 211297117U
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CN
China
Prior art keywords
board
plate
circuit board
inner plate
semi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201921723788.3U
Other languages
Chinese (zh)
Inventor
金立山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Printed Circuit Board Co Ltd
Original Assignee
Digital Printed Circuit Board Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Printed Circuit Board Co Ltd filed Critical Digital Printed Circuit Board Co Ltd
Priority to CN201921723788.3U priority Critical patent/CN211297117U/en
Application granted granted Critical
Publication of CN211297117U publication Critical patent/CN211297117U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model provides a pair of multilayer circuit board structure, which comprises a circuit board, the circuit board includes top plate, first prepreg, first inner plate, second prepreg, second inner plate, third prepreg, third inner plate, fourth prepreg, the lower plate that from the top down set gradually, the top plate lower extreme with first recess has all been seted up to first inner plate up end, both ends all are equipped with fill in first arch in the first recess about the first prepreg, top plate, first inner plate, second inner plate, third inner plate, lower plate upper end edge all are equipped with the number of piles label. The utility model discloses a multilayer circuit board structure, stable in structure can avoid the off normal problem that takes place between each connection interface.

Description

Multilayer circuit board structure
Technical Field
The utility model relates to a circuit board technical field, concretely relates to multilayer circuit board structure.
Background
Circuit boards are providers of electrical connections for electronic components. Its development has been over 100 years old; the design of the method is mainly layout design; the circuit board has the main advantages of greatly reducing errors of wiring and assembly and improving the automation level and the production labor rate. The circuit board is developed from a single layer to a double-sided board and a multi-layer board, and the development trend of the circuit board production and manufacturing technology in the future is to develop the circuit board in the directions of high density, high precision, fine aperture, fine conducting wire, small space, high reliability, multilayering, high-speed transmission, light weight and thin type in performance. For some circuit boards with complex winding displacement, the number of layers of the circuit board is large, and each layer of board is usually connected by a prepreg with good heat conduction and insulation properties.
SUMMERY OF THE UTILITY MODEL
To above problem, the utility model provides a multilayer circuit board structure, stable in structure can avoid the off normal problem that takes place between each connection interface.
In order to achieve the above object, the present invention provides the following technical solutions:
a multilayer circuit board structure comprises a circuit board, wherein the circuit board comprises an upper board, a first semi-cured board, a first inner board, a second semi-cured board, a second inner board, a third semi-cured board, a third inner board, a fourth semi-cured board and a lower board which are sequentially arranged from top to bottom, first grooves are formed in the lower end face of the upper board and the upper end face of the first inner board, first bulges filled in the first grooves are arranged at the upper end and the lower end of the first semi-cured board, second grooves are formed in the lower end face of the first inner board and the upper end face of the second inner board, second bulges filled in the second grooves are arranged at the upper end and the lower end of the second semi-cured board, third grooves are formed in the lower end face of the second inner board and the upper end face of the third inner board, third bulges filled in the third grooves are arranged at the upper end and the lower end of the third semi-cured board, the terminal surface under the third inner plate with the fourth recess has all been seted up to lower floor's board up end, both ends all are equipped with fill about the fourth prepreg in fourth arch in the fourth recess, upper plate, first inner plate, second inner plate, third inner plate, lower floor's board upper end edge all are equipped with the number of piles label.
Specifically, waterproof films are covered on the upper end face and the lower end face of the circuit board.
Specifically, copper foils are arranged on the upper end face of the upper layer plate, the upper end face of the first inner layer plate, the upper end face of the second inner layer plate, the upper end face of the third inner layer plate and the lower end face of the lower layer plate.
Specifically, a first gold dissolving hole is formed between the upper plate and the first inner plate, a second gold dissolving hole is formed between the first inner plate and the second inner plate, a third gold dissolving hole is formed between the second inner plate and the third inner plate, and a fourth gold dissolving hole is formed between the third inner plate and the lower plate.
Specifically, the upper end of the upper plate is connected with a plurality of electronic elements.
The utility model has the advantages that:
the utility model discloses a circuit board has multilayer structure, has increased recess and arch in the interface department of each layer, can avoid two-layer panel to take place the offset to improve multilayer circuit board's structural stability, and increased the label that is used for discerning the number of piles at the top plate, lower plywood and each inner plating upside edge, make things convenient for operating personnel to carry out the number of piles discernment when lamination man-hour.
Drawings
Fig. 1 is a schematic structural diagram of a multilayer circuit board structure according to the present invention.
The reference signs are: the multilayer printed circuit board comprises an upper layer board 11, a first semi-cured board 12, a first inner layer board 13, a second semi-cured board 14, a second inner layer board 15, a third semi-cured board 16, a third inner layer board 17, a fourth semi-cured board 18, a lower layer board 19, a first groove 21, a first protrusion 22, a layer number label 23, a waterproof film 24, a copper foil 25, a first gold dissolving hole 26, a second gold dissolving hole 27, a third gold dissolving hole 28, a fourth gold dissolving hole 29 and an electronic element 31.
Detailed Description
The present invention will be described in further detail with reference to the following examples and drawings, but the present invention is not limited thereto.
As shown in fig. 1:
a multilayer circuit board structure comprises a circuit board, the circuit board comprises an upper plate 11, a first semi-solidified plate 12, a first inner plate 13, a second semi-solidified plate 14, a second inner plate 15, a third semi-solidified plate 16, a third inner plate 17, a fourth semi-solidified plate 18 and a lower plate 19 which are arranged in sequence from top to bottom, a first groove 21 is formed on the lower end surface of the upper plate 11 and the upper end surface of the first inner plate 13, first protrusions 22 filled in the first groove 21 are arranged at the upper end and the lower end of the first semi-solidified plate 12, second grooves are formed on the lower end surface of the first inner plate 13 and the upper end surface of the second inner plate 15, second protrusions filled in the second grooves are arranged at the upper end and the lower end of the second semi-solidified plate 14, third grooves are formed on the lower end surface of the second inner plate 15 and the upper end surface of the third inner plate 17, third protrusions filled in the third grooves are arranged at the upper end and the lower end of the third semi, fourth recess has all been seted up to terminal surface and 19 up ends of lower floor's board under the third inner plate 17, both ends all are equipped with the fourth arch of filling in the fourth recess about the fourth prepreg 18, utilize recess and bellied limiting displacement between each layer panel, can avoid two-layer panel to take place the offset, thereby improve the structural stability of multilayer circuit board, upper plate 11, first inner plate 13, second inner plate 15, third inner plate 17, 19 upper end edges of lower plate all are equipped with number of piles label 23, make things convenient for operating personnel to carry out the number of piles discernment when lamination is processed.
Preferably, the upper and lower end faces of the circuit board are also covered with waterproof films 24, and the waterproof films 24 can improve the waterproof performance of the circuit board.
Preferably, the upper end surface of the upper board 11, the upper end surface of the first inner board 13, the upper end surface of the second inner board 15, the upper end surface of the third inner board 17, and the lower end surface of the lower board 19 are provided with copper foils 25, and the copper foils 25 form circuit layers by etching.
Preferably, a first gold hole 26 is formed between the upper plate 11 and the first inner plate 13, copper is plated on the inner wall of the first gold hole 26, the first gold hole 26 is connected between the upper plate 11 and the circuit layer at the upper end of the first inner plate 13, so as to realize the electrical connection between the upper plate 11 and the first inner plate 13, a second gold hole 27 is formed between the first inner plate 13 and the second inner plate 15, copper is plated on the inner wall of the second gold hole 27, the second gold hole 27 is connected between the first inner plate 13 and the circuit layer at the upper end of the second inner plate 15, so as to realize the electrical connection between the first inner plate 13 and the second inner plate 15, a third gold hole 28 is formed between the second inner plate 15 and the third inner plate 17, copper is plated on the inner wall of the third gold hole 28, the third gold hole 28 is connected between the second inner plate 15 and the circuit layer at the upper end of the third inner plate 17, so as to realize the electrical connection between the second inner plate 15 and the third inner plate 17, a fourth gold hole 29 is formed between the third inner layer board 17 and the lower layer board 19, copper is plated on the inner wall of the fourth gold hole 29, and the fourth gold hole 29 is connected between the upper end of the third inner layer board 17 and the circuit layer at the lower end of the lower layer board 19, so that the electric connection between the third inner layer board 17 and the lower layer board 19 is realized.
Preferably, a plurality of electronic components 31 such as resistors and capacitors are connected to the upper end of the upper plate 11.
The above embodiments only represent one embodiment of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.

Claims (5)

1. A multilayer circuit board structure comprises a circuit board and is characterized in that the circuit board comprises an upper plate (11), a first semi-cured board (12), a first inner plate (13), a second semi-cured board (14), a second inner plate (15), a third semi-cured board (16), a third inner plate (17), a fourth semi-cured board (18) and a lower plate (19) which are sequentially arranged from top to bottom, wherein first grooves (21) are respectively formed in the lower end surface of the upper plate (11) and the upper end surface of the first inner plate (13), first bulges (22) filled in the first grooves (21) are respectively arranged at the upper end and the lower end of the first semi-cured board (12), second grooves are respectively formed in the lower end surface of the first inner plate (13) and the upper end surface of the second inner plate (15), second bulges filled in the second grooves are respectively arranged at the upper end and the lower end of the second semi-cured board (14), the multilayer composite board is characterized in that a third groove is formed in the upper end face of the third inner board (17) and the lower end face of the second inner board (15), a third groove is formed in the upper end face of the third inner board (17), a fourth groove is formed in the upper end face of the third prepreg (16), a third protrusion filled in the third groove is formed in the upper end face of the third inner board (17), a fourth protrusion filled in the fourth groove is formed in the upper end face of the fourth prepreg (18), and layer number labels (23) are arranged on the upper end edges of the upper board (11), the first inner board (13), the second inner board (15), the third inner board (17) and the lower board (19).
2. A multilayer circuit board structure according to claim 1, characterized in that the upper and lower end faces of the circuit board are covered with waterproof films (24).
3. A multilayer circuit board structure according to claim 1, characterized in that the upper side of the upper board (11), the upper side of the first inner board (13), the upper side of the second inner board (15), the upper side of the third inner board (17) and the lower side of the lower board (19) are provided with copper foils (25).
4. A multilayer circuit board structure according to claim 1, characterized in that a first metallizing hole (26) is provided between the upper board (11) and the first inner board (13), a second metallizing hole (27) is provided between the first inner board (13) and the second inner board (15), a third metallizing hole (28) is provided between the second inner board (15) and the third inner board (17), and a fourth metallizing hole (29) is provided between the third inner board (17) and the lower board (19).
5. A multilayer circuit board structure according to claim 1, characterized in that several electronic components (31) are connected to the upper end of the upper plate (11).
CN201921723788.3U 2019-10-15 2019-10-15 Multilayer circuit board structure Expired - Fee Related CN211297117U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201921723788.3U CN211297117U (en) 2019-10-15 2019-10-15 Multilayer circuit board structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201921723788.3U CN211297117U (en) 2019-10-15 2019-10-15 Multilayer circuit board structure

Publications (1)

Publication Number Publication Date
CN211297117U true CN211297117U (en) 2020-08-18

Family

ID=72014708

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201921723788.3U Expired - Fee Related CN211297117U (en) 2019-10-15 2019-10-15 Multilayer circuit board structure

Country Status (1)

Country Link
CN (1) CN211297117U (en)

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GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20200818

CF01 Termination of patent right due to non-payment of annual fee