CN210926003U

CN210926003U - Semiconductor structure

Info

Publication number: CN210926003U
Application number: CN201922167224.2U
Authority: CN
Inventors: 平尔萱; 周震
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-12-06
Filing date: 2019-12-06
Publication date: 2020-07-03
Anticipated expiration: 2029-12-06

Abstract

The present disclosure provides a semiconductor structure. The semiconductor structure includes: the substrate comprises an active region and a shallow trench isolation region which are arranged at intervals; a plurality of isolation structures located on the surface of the substrate; the grooves are positioned among the isolation structures, the bottoms of the grooves are provided with first inclined planes, and the first inclined planes are formed in the active area; and the conductive plug is positioned in the groove. The embodiment of the disclosure can avoid forming air gaps in the polysilicon during the manufacturing process of the storage contact plug structure.

Description

Semiconductor structure

Technical Field

The present disclosure relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure capable of avoiding generating an air gap.

Background

A Storage Node Contact (SNC) is a Contact structure, usually polysilicon, used to connect a transistor and a Storage capacitor in a DRAM structure. The SNC is usually connected to the substrate and the STI (Shallow trench isolation) at the same time at the bottom, and connected to the metal at the top, and the sidewall is a sidewall of an isolation structure, such as a bit line structure or a dielectric layer structure.

In the related art, since the bit line structure is fabricated in advance, it is necessary to fabricate a dielectric layer structure as an isolation structure to fabricate the other two sidewalls of the SNC trench, and to fill the trench with polysilicon to fabricate the SNC. Because the dielectric layer side walls have high hardness and can only be manufactured by deposition, trenches between the deposited dielectric layer side walls are generally in a trapezoidal structure (refer to fig. 3 in the specification), the trenches are narrow at the top and wide at the bottom, deposition uniformity is difficult to control in a polycrystalline silicon deposition process, air gaps are often formed inside the SNC, electrical properties of the SNC are changed, element faults are generated, and the yield is reduced.

It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

SUMMERY OF THE UTILITY MODEL

It is an object of the present disclosure to provide a semiconductor structure for overcoming, at least to some extent, the problem of air gaps inside polysilicon during the fabrication of a memory contact plug structure due to the limitations of the related art.

According to a first aspect of the present disclosure, there is provided a semiconductor structure comprising:

the substrate comprises an active region and a shallow trench isolation region which are arranged at intervals;

a plurality of isolation structures located on the surface of the substrate;

the grooves are positioned among the isolation structures, the bottoms of the grooves are provided with first inclined planes, and the first inclined planes are formed in the active area;

and the conductive plug is positioned in the groove.

In an exemplary embodiment of the present disclosure, the groove has a top area smaller than a bottom area.

In an exemplary embodiment of the present disclosure, the first inclined surface has an inclination angle of 30 ° to 40 °.

In an exemplary embodiment of the present disclosure, the bottom of the groove further has a second slope, and the second slope is formed on the shallow trench isolation region.

In an exemplary embodiment of the present disclosure, the second inclined surface has an inclination angle of 20 ° to 60 °.

In one exemplary embodiment of the present disclosure, the isolation structure includes a bit line structure and a dielectric layer structure.

In an exemplary embodiment of the present disclosure, a cross-section of the plurality of grooves includes one or more of a square shape, a polygonal shape, a circular shape, or an elliptical shape.

In an exemplary embodiment of the present disclosure, the plurality of grooves are arranged in an array.

In an exemplary embodiment of the present disclosure, the first slope is a curved surface.

In an exemplary embodiment of the present disclosure, the second slope is a curved surface.

According to the embodiment of the disclosure, the slope is arranged on the exposed part of the active region at the bottom of the groove for accommodating the SNC structure, and the polysilicon is grown in the groove by taking the slope as a substrate, so that a storage contact plug structure without an air gap can be quickly formed, the failure rate of elements is reduced, and the yield is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.

Fig. 1 is a schematic diagram of one arrangement of SNC structures in an exemplary embodiment of the present disclosure.

Fig. 2 is a schematic diagram of another arrangement of SNC structures in an exemplary embodiment of the present disclosure.

Fig. 3 is a schematic view of a manufacturing process of an SNC structure in the related art.

Fig. 4 is a schematic diagram of a semiconductor structure in an embodiment of the disclosure.

Fig. 5 is a flow chart of a method of manufacturing an SNC structure in an embodiment of the present disclosure.

FIGS. 6A-6D are schematic process diagrams of the steps shown in FIG. 5.

Fig. 7A and 7B are schematic diagrams of the slope morphology of the SNC structure in the embodiments of the present disclosure.

Fig. 8A and 8B are schematic slope morphology diagrams of another angular cross-section of the SNC structure in an embodiment of the disclosure.

Fig. 9A is one of the schematic diagrams of the undesirable effects of polysilicon growth.

FIG. 9B is a second schematic diagram illustrating the undesirable effects of polysilicon growth.

Fig. 10 is a schematic diagram of the SNC structure after the etch-back process is performed.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the subject matter of the present disclosure can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and the like. In other instances, well-known technical solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.

Further, the drawings are merely schematic illustrations of the present disclosure, in which the same reference numerals denote the same or similar parts, and thus, a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in the form of software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The following detailed description of exemplary embodiments of the disclosure refers to the accompanying drawings.

The structure on the right side of fig. 1 is a cross-sectional view taken along the a-a position of the structure shown on the left side of fig. 1. In a DRAM structure, the A-A locations are perpendicular to the Bit Lines (BL), parallel to the Word lines (Word Line, WL). In fig. 1, a storage contact plug Structure (SNC)11 is located between sidewalls of two bit line structures 12 at corresponding positions in two adjacent rows of word lines, and a source region 14 and a shallow trench isolation Structure (STI)13 are connected to the bottom of the storage contact plug structure.

The structure on the right side of fig. 2 is a cross-sectional view taken along the B-B position of the structure shown on the left side of fig. 2. In the DRAM structure, the B-B position is vertical to Word Lines (WL) and parallel to Bit Lines (BL), adjacent SNC structures are isolated by an isolation structure 15, and the isolation structure 15 comprises a dielectric layer structure. It is understood that the storage contact plug Structure (SNC)11 in fig. 2 is still connected with the source region 14 and the shallow trench isolation structure 13 at the bottom as in fig. 1. It is understood that the line B-B is shifted to make the cross-sectional positions different, the proportions of the active region 14 and the shallow trench isolation structure 13 in the cross-section are different, and the embodiment of the disclosure only uses the area positions and proportions as shown in fig. 2 for simplifying the illustration, but the disclosure is not limited thereto.

Referring to fig. 3, since the isolation structure between the SNCs includes the bit line structure and the dielectric layer sidewall, the dielectric layer sidewall needs to be formed when the groove for accommodating the SNC structure is manufactured. However, since the dielectric layer sidewall has a generally high hardness and is difficult to be formed by etching, in the related art, in the B-B direction shown in fig. 2, a trench (e.g., a) is often formed by etching the sacrificial layer material 31 (typically, an oxide, such as silicon dioxide, BPSG, BSG, etc.), and a dielectric layer structure 15 (e.g., B) is often formed by using a deposition technique; the remaining sacrificial layer material 31 (e.g., c) is then removed and polysilicon is deposited between the dielectric layer structures 15 to fabricate the SNC structure 11 (e.g., d). It will be appreciated that there are isolation structures both forward and rearward in the view of the figure (such as isolation structure 12 on the right side of figure 1) including the bit line structures that are typically formed prior to the formation of dielectric layer structure 15. In this technique, since the sacrificial layer material is etched in step a, the cross section of the remaining sacrificial layer material is trapezoidal, i.e. the last manufactured SNC structure also has a trapezoidal cross section with a narrow top and a wide bottom, it is difficult to achieve good polysilicon deposition, and air gaps (e.g. d) often exist in the SNC structure.

To this end, the embodiments of the present disclosure provide a semiconductor structure capable of avoiding the generation of an air gap in an SNC structure.

It should be noted that fig. 4 is a cross-sectional view taken along the B-B position of the structure shown on the left side of fig. 2, and there are isolation structures (such as isolation structure 12 on the right side of fig. 1) including the bit line structures both in front and behind the structure viewed in the direction of the drawing.

Referring to fig. 4, a semiconductor structure 400 may include:

a substrate 41 including an active region 14 and a shallow trench isolation region 13 arranged at an interval;

an isolation structure 15 located on the surface of the substrate 41;

a plurality of grooves 42 in the isolation structure 15, wherein the bottom of the groove 42 has a first inclined surface 43, and the first inclined surface 43 is formed in the active region 14;

and the conductive plug 11 is positioned in the groove 42.

Wherein, since fig. 4 is a cross-sectional view along the direction B-B in fig. 2, the isolation structure 15 marked in fig. 4 is actually a dielectric layer structure, i.e., the isolation structure 15 on the right side of fig. 2, but it can be understood by those skilled in the art that the isolation structure 15 of the embodiment of the present disclosure further includes the bit line structure 12 shown in fig. 1, and the bit line structure 12 is located in front of or behind the viewing direction of fig. 4. That is, the isolation structure 15 in the embodiment of the present disclosure includes four sidewall structures, such as two adjacent bit line structures and two adjacent dielectric layer structures, so as to surround and isolate the periphery of the groove 42.

In the embodiment shown in fig. 4, the top area of the grooves 42 is smaller than the bottom area, the cross section of the plurality of grooves 42 may be one or more of square, polygon, circle or ellipse, the plurality of grooves 42 are arranged in an array, and the array may be an aligned or staggered dot array. It is understood that, since two opposite sidewalls of the groove 42 are formed by isolation structures including bit line structures perpendicular to the substrate, the length of the top surface of the groove 42 may be equal to the length of the bottom surface, or the width of the top surface of the groove 42 may be equal to the width of the bottom surface, which is not limited in this disclosure.

In one embodiment of the present disclosure, the inclination angle of the first inclined surface 43 may be, for example, 30 ° to 40 °. Of course, there may be another region on the active region 14, which has a slope different from that of the first slope, such as a horizontal region (e.g., the bottom shape of the SNC structure 11 in the structure on the right side of fig. 1), and in another embodiment of the present disclosure, the first slope 43 may also be a curved surface formed by an etching process, which is not particularly limited by the present disclosure.

Fig. 5 is a flow chart of a method of fabricating the semiconductor structure shown in fig. 4.

Referring to fig. 5, a method 500 of fabricating a semiconductor structure may include:

step S1, providing a substrate, wherein the substrate comprises an active region and a shallow trench isolation region which are arranged at intervals, and forming a sacrificial layer material on the surface of the substrate;

step S2, etching part of the sacrificial layer material to form a plurality of first grooves;

step S3, after depositing a dielectric layer on the first groove, removing the residual sacrificial layer material to form a plurality of second grooves;

step S4, etching the bottom active region exposed portion of the second trench downward to form a first slope;

step S5, using the first slope as a substrate, performing an epitaxial silicon growth process in the second trench to fill the second trench.

In the embodiments of the present disclosure, the sacrificial layer is, for example, an oxide layer, including but not limited to an oxide (e.g., silicon dioxide), BPSG, BSG, and other materials. The first groove is, for example, an inverted trapezoidal groove with a wide top and a narrow bottom, and the second groove is, for example, a trapezoidal groove with a narrow bottom and a wide top. It should be understood by those skilled in the art that the first grooves with non-inverted trapezoid shape can be formed, and the specific shape is determined by the factors of the process means, the process conditions, etc.; the second groove may be a non-trapezoidal groove, and the specific shape is related to the shape of the first groove.

FIGS. 6A-6D are schematic process diagrams of the steps shown in FIG. 5.

As in fig. 2 and 4, for simplicity of description, the positions and the ratios of the active region and the shallow trench isolation region in fig. 6A to 6D are only schematic and are not used to limit the positions and the ratios of the active region and the shallow trench isolation region in an actual manufacturing process.

Referring to fig. 6A, as in step (a) of fig. 3, the embodiments of the present disclosure also etch a first trench 45 on the sacrificial layer 44 in preparation for the subsequent fabrication of the isolation structure. The bottom of the first trench 45 exposes both the active region 14 and the shallow trench isolation region 13. Since the bit line structures located at the front or rear in the viewing direction of the figure are usually formed, the step shown in fig. 6A is actually to fill the sacrificial layer between the bit line structures, and then etch the first trench 45 in the sacrificial layer, i.e. the front and rear sidewalls of the viewing direction of the first trench 45 are vertical and formed by the isolation structures including the bit line structures.

Referring to fig. 6B, as in step (B) of fig. 3, the isolation structure 15 is also fabricated by depositing a dielectric layer, such as silicon nitride.

Referring to fig. 6C, as in step (C) of fig. 3, the embodiment of the present disclosure creates a space for the SNC to be manufactured by also removing the sacrificial layer 44, forming the second trench 42, and exposing the active region 14 and the shallow trench isolation region 13 at the same time at the bottom of the second trench 42. It should be noted that, as can be seen from fig. 2, the ratio of the active area and the shallow trench isolation area exposed at the bottom of the second trench 42 is actually different when the cross-sectional position is different (i.e., the line B-B is shifted laterally). Therefore, although the embodiment of the disclosure only shows one exposed state of the active region and the shallow trench isolation region, in practical applications, the exposed states of the active region and the shallow trench isolation region may be multiple.

Referring to fig. 6D, the embodiment of the present disclosure provides that SNC is manufactured through an epitaxial silicon growth process, and therefore, in order to smoothly perform the epitaxial silicon growth process, the bottom of the second trench 42 is processed, that is, the first slope 43 is manufactured at the bottom of the second trench 42 through a dry etching process, a wet etching process, or the like. To fabricate the SNC, the bottom of the second trench 42 simultaneously exposes an active region, which is typically monocrystalline silicon, and a shallow trench isolation (referring to the left structure of fig. 2), which is typically oxide (e.g., silicon dioxide). Both provide completely different environments for epitaxial silicon growth. In the disclosed embodiments, single crystal silicon is typically grown on only one side of the single crystal silicon, is difficult to grow on the silicon dioxide side, or grows at a slow rate during this process. Therefore, in order to provide more crystal orientation for the growth of single crystal silicon, making the growth of single crystal silicon more uniform and faster, first bevel 43 is fabricated prior to the epitaxial silicon growth process in the disclosed embodiments.

In an exemplary embodiment of the present disclosure, the gas etching the first slope 43 may be sulfur hexafluoride (SF), for example₆) The first inclined surface 43 having an inclination angle of 30 to 40 ° can be etched by controlling parameters such as Bias (Bias) and Flow (Flow) of the etching gas. It should be noted that the etching process often cannot ensure a perfect plane, so in the actual process, the first step is to etch the waferThe slope 43 may also be a curved surface formed by an etching process, and the shape of the curved surface can be shown with reference to fig. 7A. Furthermore, in some embodiments, there may be other regions of the active region, such as a flat surface, i.e., the end point of the first slope 43 formed by etching does not coincide with the edge of the active region. At this time, the state of the active region may be referred to as shown in fig. 7B.

In addition, because the shallow trench isolation region is connected with the active region, when the exposed part of the active region is etched with an inclined surface, the exposed part of the shallow trench isolation region is easily etched at the same time. At this time, the etching selectivity may be controlled to a value of 1:1 or the like to form the second slope 46, and the inclination angle of the second slope 46 is, for example, 20 ° to 60 °. Of course, it will be understood by those skilled in the art that, due to process variations or selectivity ratios other than 1:1, the heights of the shallow trench isolation region and the active region are different after etching, but in order to prevent the heights of the shallow trench isolation region and the active region from being too different, the etching selection ratio is preferably not too different, so that an air gap is not generated in the epitaxial silicon growth process. As with the formation of the first slope 43, the second slope 46 may also be a cambered surface, or the edge of the second slope 46 does not coincide with the edge of the shallow trench isolation region, and these two states can be respectively shown in fig. 7A and fig. 7B.

It will be appreciated that the etching process is performed for the entire active area exposed portion and the entire shallow trench isolation exposed portion, and thus the slope of the bottom of the second trench 42 is substantially similar to a straight bowl, and the slope exists at the bottom of the second trench 42 both when viewed in cross-section along a-a in fig. 1 and when viewed in cross-section along B-B in fig. 2.

Referring to fig. 8A to 8B, the ratio of the active region 14 to the shallow trench isolation 13 may be different and the slope may be different as viewed from the cross section along the direction a-a on the left side of fig. 1.

In order to avoid the influence of the remaining impurities (native oxide layer, etching residues) (part 43 or part 46 in fig. 6D) on the electrical properties of the slope, and even cause the failure of the growth of the single crystal silicon, in some embodiments of the present disclosure, the first slope 43 may also be cleaned in situ by dry cleaning of oxide, dry cleaning for removing carbon-based residues, and the like, so as to ensure the purity of the single crystal silicon interface and obtain a high-quality growth effect.

After in-situ cleaning, single crystal silicon may be grown on the bevel as the substrate until the epitaxial silicon is controlled to fill the entire second trench 42 to form the conductive plug 11 as shown in fig. 4. In some embodiments, the conductive plug 11 is a storage contact plug Structure (SNC). Referring to the right side of fig. 1, the lower portion of conductive plug 11 (i.e., SNC structure 11) shown on the right side of fig. 1 is also beveled as viewed in cross-section from the a-a position.

It is noted that since the profile of the grown single crystal silicon is often not ideal (as shown in fig. 7), in yet another embodiment of the present disclosure, the selectivity of the polysilicon growth may be reduced while increasing the growth rate in step S4. For example, growth selectivity can be reduced by setting a suitable hydrochloric acid flow rate. The preferred hydrochloric acid concentration is, for example, 150 sccm. + -. 30%. The increase of the flow of the hydrochloric acid can inhibit the growth of polycrystal and tends to grow on the surface of the single crystal; the reduction of the hydrochloric acid flow rate can lead to the increase of the growth speed of the polycrystalline silicon and improve the yield. Therefore, in order to ensure the quality of the single crystal and improve the yield, an optimal hydrochloric acid flow range needs to be found, and therefore the embodiment of the present disclosure sets the above range.

In addition, since single crystal silicon and polycrystalline silicon may be simultaneously grown, the profile is not easily controlled, as shown in fig. 9A or 9B. At this time, the polysilicon may be removed by a wet process or a etchback (process Etch) method to leave only the single crystal silicon, and the top of the single crystal silicon is trimmed to a substantially planar shape (as shown in fig. 10), and the length of the conductive plug is adjusted for a subsequent metal connection process.

In one embodiment, the conductive plug is a storage contact plug. After forming the storage contact plug, a metal capacitor Landing Pad (bonding Pad) may be formed on the storage contact plug for subsequent fabrication of a capacitor on the interface platform. Since the landing pad of metal material is connected to the storage contact plug in the fabrication of the metal-semiconductor contact structure, in another embodiment of the present disclosure, after the second trench is filled, metal may be deposited on the surface of the conductive plug 11.

At the moment, the landing pad is in contact with the monocrystalline silicon, the contact conditions of the landing pad and the monocrystalline silicon are the same as those of the source electrode and the drain electrode of the transistor in the peripheral circuit region, metal is in contact with the monocrystalline silicon, the metallization process is realized, the optimal process conditions can be simultaneously achieved, the process condition requirements can be simpler, the performance of the contact structure is improved, and the contact resistance of the metal and the monocrystalline silicon is smaller under the condition of lower manufacturing cost.

In summary, in the embodiments of the present disclosure, a single crystal silicon is grown at the bottom of the groove to manufacture a storage contact plug structure (SNC structure) filling the groove, so that an air gap and a reduction in electrical performance in the SNC structure caused by depositing a polysilicon in the related art can be avoided; in addition, through making the monocrystalline silicon inclined plane bottom the recess to grow monocrystalline silicon on the monocrystalline silicon inclined plane, can avoid the growth that monocrystalline silicon growth process brought inhomogeneous, the not high scheduling problem of growth speed, effectively improve manufacturing efficiency when promoting the yields.

It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A semiconductor structure, comprising:

a plurality of isolation structures located on the surface of the substrate;

and the conductive plug is positioned in the groove.

2. The semiconductor structure of claim 1, wherein a top area of the recess is smaller than a bottom area.

3. The semiconductor structure of claim 1, wherein the first slope has an inclination of 30 ° to 40 °.

4. The semiconductor structure of claim 1, wherein the bottom of the recess further has a second bevel, the second bevel being formed in the shallow trench isolation region.

5. The semiconductor structure of claim 4, wherein the second slope has an inclination of 20 ° to 60 °.

6. The semiconductor structure of claim 1, wherein the isolation structure comprises a bitline structure and a dielectric layer structure.

7. The semiconductor structure of claim 1, wherein a cross-section of the plurality of recesses comprises one or more of a square, a polygon, a circle, or an ellipse.

8. The semiconductor structure of claim 7, wherein the plurality of recesses are arranged in an array.

9. The semiconductor structure of claim 1, wherein the first bevel is a curved surface.

10. The semiconductor structure of claim 4, wherein the second bevel is a curved surface.