CN210807222U - Signal processing device with small edge slope and signal counting equipment - Google Patents

Abstract

The utility model provides a along the little signal processing device of slope and signal counting equipment, wherein, a signal processing device that the slope is little includes along the slope: the input end of the frequency doubling module receives a clock signal and doubles the frequency of the clock signal; the clock end of the register module is connected with the output end of the frequency doubling module, and the register module receives a first signal input in series and then outputs a second signal in parallel; when each bit of the second signal is at a high level, the signal to be detected is at a high level, otherwise, the signal to be detected is at a low level; or, when each bit of the second signal is at a low level, the signal to be detected is at a low level, otherwise, the signal to be detected is at a high level. Adopt the utility model discloses a device doubles the frequency to clock clk, then multiplexing frequency multiplication clock is to the first signal sampling of input, rather than directly sampling with original clock, has realized avoiding the small noise influence at to a great extent when handling the too slow signal of level upset to make the processing result more accurate.

Description

A signal processing device and signal counting device with small edge slope

technical field

The utility model relates to the field of signal processing, in particular to a signal processing device with a small edge slope and a signal counting device.

Background technique

Signal input has the problem of noise tolerance. For signals with large edge slopes, that is, signals that complete the rising or falling process within one clock cycle, even if the sampling time of the signal is in the rising/falling process, the judgment result at this time may be Low level or high level, but it has no effect on the counting result of the rising/falling edge, because the time of the signal maintaining the low/high level before and after the rising/falling must be greater than one clock cycle.

If the input signal level flips too slowly, that is, the edge slope is too small, even if the input voltage noise is relatively small, it is possible that the edge judgment is wrong, resulting in inaccurate calculation of the rise/fall times of the signal. That is to say, when there is actually only one rising edge (or falling edge), the processing result of the FPGA becomes more than one edge, thus affecting the final result. For example, in practical applications, when the logic chip counts rising edges to measure the frequency, the number of rising/falling counts is inaccurate.

Utility model content

In view of the above problems, the present invention is proposed to provide a signal processing device and a signal counting device with a small edge slope that overcome the above problems or at least partially solve the above problems.

According to one aspect of the present utility model, a signal processing device with a small edge slope is provided, comprising:

a frequency multiplication module, the input end of the frequency multiplication module receives a clock signal and multiplies the clock signal;

a register module, the clock terminal of which is connected to the output terminal of the frequency multiplier module, the register module receives the serially input first signal and then outputs the second signal in parallel; wherein, when each bit of the second signal is When high level, the signal to be tested is high level, otherwise it is low level; or, when each bit of the second signal is low level, the signal to be tested is low level, otherwise it is high level flat.

Preferably, the device further comprises: a gate circuit, the input terminal of the gate circuit is connected to the output terminal of the register module to perform a logical operation on the second signal to obtain the third signal.

Preferably, the register module is a shift register.

Preferably, the shift register includes a plurality of flip-flops connected in series, and the number of the flip-flops is consistent with the frequency multiplication number of the frequency multiplication module.

Preferably, the gate circuit includes at least an OR gate circuit or an AND gate circuit.

Preferably, the output terminal of each flip-flop is connected to the input terminal of the gate circuit, and the output terminal of the flip-flop located in the previous stage is connected to the input terminal of the flip-flop located in the subsequent stage. The output end of the frequency multiplication module is respectively connected to the clock end of each of the flip-flops.

Preferably, the frequency multiplication module is a phase locked loop.

Preferably, the processing device is applied in an FPGA.

According to another aspect of the present invention, there is also provided a signal counting device with a small edge slope, comprising: the signal processing device as described above, and a counter for counting the number of edges of the signal to be measured.

The clock clk is multiplied by the processing device of the present invention, and then the multiplied clock is multiplexed to sample the input first signal, and then gate circuit processing is performed. The counting device according to the embodiment of the present invention counts the number of edges again, so that the influence of small noise can be avoided to a large extent when processing a signal whose level inversion is too slow, thereby making the counting result more accurate.

The above description is only an overview of the technical solution of the present invention, in order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the contents of the description, and in order to make the above-mentioned and other purposes, features and advantages of the present invention better. It is obvious and easy to understand, and the specific embodiments of the present invention are given below.

Description of drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are just some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative efforts.

1 is a schematic structural diagram of a signal processing device with a small edge slope in an embodiment of the present invention;

2 is a schematic structural diagram of a signal counting device with a small edge slope in an embodiment of the present utility model;

Fig. 3 is the time relation diagram of the first signal and the clock signal in the rising process;

FIG. 4 is a schematic diagram of signal output that has not been processed by the signal processing device according to the embodiment of the present invention;

FIG. 5 is a schematic diagram of signal output processed by the signal processing device according to the embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the implementations. example. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present invention.

An embodiment of the present utility model provides a signal processing device with a small edge slope, as shown in FIG. 1 , including:

A frequency multiplication module 10, the input terminal of the frequency multiplication module receives a clock signal and multiplies the frequency of the clock signal.

Among them, the larger the multiplier, the more accurate the counting. However, in actual operation, the specific frequency multiplier is determined according to the noise situation that may occur in the actual application scenario, the small slope of the signal to be measured, the FPGA chip's judgment performance for high and low levels, and the cost. For example, if the frequency multiplier is 4 and the input frequency is 50Mhz, then the main frequency of the clock signal can be multiplied to 200Mhz through the frequency multiplication module 10 .

The register module 20, the clock terminal of which is connected to the output terminal of the frequency multiplier module, the register module receives the serially inputted first signal and then outputs the second signal in parallel; specifically, the serially inputted first signal is in an analog state During the signal stage, the edge slope is too small for some reason, that is, the slope of the rising edge or the falling edge of the first signal is very small. The device described in the embodiment of the present invention is aimed at such a signal. The device according to the embodiment of the utility model directly measures the first signal, which may lead to false triggering of subsequent triggers. The main function of the register module is to output the first signal serially input in parallel to facilitate subsequent logic operations.

Wherein, when each bit of the second signal is high level, the signal to be tested is high level, otherwise it is low level; or, when each bit of the second signal is low level, all the The signal to be tested is low level, otherwise it is high level.

The device described in the embodiment of the present invention multiplies the clock frequency clk, for example, multiplies the frequency of the main clock of the calculation frequency meter when measuring the frequency, and then multiplexes the multiplied clock to sample the input signal to be measured. The state of the signal to be tested is judged according to the state of each bit of the second signal, so that the judgment result is more accurate, and the influence of small noise is largely avoided when processing a signal whose level inversion is too slow.

Preferably, the device according to the embodiment of the present invention further includes: a gate circuit 30, the input end of the gate circuit is connected to the output end of the register module to perform a logical operation on the second signal to obtain the third signal. Specifically, the function of the gate circuit 30 is to perform a logical operation on the output of the register module 20, and the number of its input terminals matches the number of the output terminals of the register module. After the logic operation of the gate circuit, the signal to be tested is counted to obtain the number of edges. The number of edges may include the number of rising edges or the number of falling edges.

In a preferred embodiment, the register module is a shift register, and the frequency multiplier module is a phase-locked loop.

In a preferred embodiment, the processing device is applied in an FPGA, and in some cases, can also be applied in a CPLD.

Preferably, the shift register includes a plurality of flip-flops connected in series, and the number of the flip-flops is consistent with the frequency multiplication number of the frequency multiplication module. For example, if the multiplier is N, then the number of flip-flops is also N, so as to avoid being mistakenly judged that there is no rise and fall due to rising and falling, and at the same time, it can improve the effect of processing small noise, thereby improving the accuracy.

In the signal processing device with a small edge slope according to the embodiment of the present invention, the gate circuit is at least an OR gate circuit or an AND gate circuit. Specifically, when the gate circuit is an OR gate, only when the outputs of the N flip-flops are all 0, the third signal output by the gate circuit is 0; and when the outputs of the N flip-flops are other In this case, that is, when not all of them are 0, the third signal output by the gate circuit is 1. For another example, when the gate circuit is an AND gate, only when the outputs of the N flip-flops are all 1, the third signal output by the gate circuit is 1; and when the outputs of the N flip-flops are other In this case, that is, when not all are 1, the third signal output by the gate circuit is 0. Or in order to unify the counting rules, the above process can be realized by using a NAND gate circuit or a NOR gate circuit, so the selection of the gate circuit is relatively wide, and the AND gate circuit or the OR gate circuit is not limited, and it is not repeated here. Repeat. The third signal output by the gate circuit is used to determine whether each bit of the second signal is at a high level or a low level, and finally the level of the signal to be tested is obtained. That is, when each bit of the second signal is at a high level, the signal to be tested is at a high level; otherwise, it is at a low level; or, when each bit of the second signal is at a low level, the signal to be tested is at a low level. The test signal is low level, otherwise it is high level.

In a preferred embodiment, the output of each flip-flop is connected to the input of the gate circuit, and the output of the flip-flop located in the previous stage is connected to the flip-flop located in the subsequent stage. The input end, the output end of the frequency multiplication module is respectively connected to the clock end of each of the flip-flops. Through the above structure, the serially input first signal is converted into the parallel output second signal, and the trigger clock of each flip-flop is provided by the frequency multiplied clock.

The embodiment of the present invention also provides a signal counting device with a small edge slope, as shown in FIG. 2 , including:

According to the signal processing apparatus described in any of the above specific embodiments, and the counter 40, the counter is used to count the number of edges of the signal to be measured, so that the exact number of edges can be counted. Hereinafter, a specific embodiment is used as the description of the above process, but the protection scope of the present invention is not limited by this embodiment.

As shown in FIG. 3 , it is a time relationship diagram of the signal pulse to be tested and the clock signal clk during the rising process. In the figure, during a rising process of the signal to be measured pulse, the edge slope is very small, and there is noise in the middle. The situation of the signal to be measured pulse in the digital signal stage (such as the signal situation after entering the FPGA chip) is shown in Figure 4. If this solution is not adopted, the signal to be measured pulse (count the number of rising or falling) is directly measured, that is When the signal pulse to be tested is sampled when the rising edge of the clock signal clk arrives, the result obtained will be low, low, high, low, high, high, and the count rises twice. However, according to FIG. 3, it can be seen that only one rising process is actually experienced, so the counting method in the prior art is prone to errors in this case.

If the processing device described in this embodiment is used to process the signal pulse to be measured and then measured or counted by a counting device, assuming that the number of flip-flops and the multiplier of the multiplier are both 4, the timing of each signal is shown in Figure 5 , pll_out_clk is the multiplied clock (the output of the PLL), reg0, reg 1, reg 2, and reg 3 are the signals output by each flip-flop respectively, and C_out is the third signal output by the gate circuit, that is, the pulse signal to be tested passes through this scheme. The processed signal is the third signal C_out, and then the measurement is performed again, that is, the third signal C_out is sampled when the rising edge of the clock signal clk arrives, and the result is low, low, low, low, low, high , its count is 1 rise, which will not be mistakenly counted as 2 rises.

To sum up, the processing device of the present invention multiplies the frequency of the clock clk, then multiplexes the multiplied clock to sample the input first signal, and then performs gate circuit processing. After counting the number of edges after passing through the device described in the embodiment of the present invention, or directly counting the number of edges by using the counting device in the embodiment of the present invention, it is possible to avoid to a large extent when processing signals whose level inversion is too slow. Small noise effects, thus making the processing results more accurate.

It should be understood that, in various embodiments of the present invention, the size of the sequence numbers of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its functions and internal logic, and should not be dealt with in the present invention. The implementation of the embodiments constitutes no limitation.

It should also be understood that, in this embodiment of the present invention, the term "and/or" is only an association relationship for describing associated objects, indicating that there may be three kinds of relationships. For example, A and/or B can mean that A exists alone, A and B exist at the same time, and B exists alone. In addition, the character "/" in this document generally indicates that the related objects are an "or" relationship.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system, device and unit described above may refer to the corresponding process in the foregoing method embodiments, which will not be repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical, mechanical or other forms of connection.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solutions of the embodiments of the present invention.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The principles and implementations of the present utility model are described with specific embodiments in the present utility model, and the descriptions of the above embodiments are only used to help understand the method and the core idea of the present utility model; meanwhile, for those skilled in the art , according to the idea of the present utility model, there will be changes in the specific implementation and application scope. To sum up, the content of this specification should not be construed as a limitation to the present utility model.

Claims (9)

1. A signal processing apparatus having a small slope, comprising:

the input end of the frequency doubling module receives a clock signal and doubles the frequency of the clock signal;

the clock end of the register module is connected with the output end of the frequency doubling module, and the register module receives a first signal input in series and then outputs a second signal in parallel; when each bit of the second signal is at a high level, the signal to be detected is at a high level, otherwise, the signal to be detected is at a low level; or, when each bit of the second signal is at a low level, the signal to be detected is at a low level, otherwise, the signal to be detected is at a high level.

2. The apparatus of claim 1, wherein the register module is a shift register.

3. The apparatus of claim 2, further comprising: and the input end of the gate circuit is connected with the output end of the register module so as to carry out logic operation on the second signal to obtain a third signal.

4. The apparatus of claim 3, wherein the shift register comprises a plurality of flip-flops connected in series, and the number of flip-flops is equal to the frequency of the frequency doubling module.

5. The apparatus according to claim 3, wherein the gate circuit comprises at least an OR gate circuit or an AND gate circuit.

6. The apparatus according to claim 4, wherein an output terminal of each of the flip-flops is connected to an input terminal of the gate circuit, an output terminal of the flip-flop at the previous stage is connected to an input terminal of the flip-flop at the subsequent stage, and an output terminal of the frequency doubling module is connected to a clock terminal of each of the flip-flops, respectively.

7. The apparatus of claim 1, wherein the frequency multiplier module is a phase locked loop.

8. The signal processing device with small slope according to any one of claims 1 to 7, wherein the processing device is applied in an FPGA.

9. A signal counting apparatus having a small slope, comprising: a signal processing apparatus according to any one of claims 2 to 8, and a counter for counting the number of edges of the signal under test.

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