CN210575115U - Sensitive amplifier - Google Patents
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- CN210575115U CN210575115U CN201922086501.7U CN201922086501U CN210575115U CN 210575115 U CN210575115 U CN 210575115U CN 201922086501 U CN201922086501 U CN 201922086501U CN 210575115 U CN210575115 U CN 210575115U
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Abstract
The utility model relates to a sensitive amplifier, sensitive amplifier includes: the precharge module, a first input/output end, a second input/output end, a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit and a second energy storage unit. The sensitive amplifier can compensate the offset voltage, so that the offset voltage of the sensitive amplifier is greatly reduced, and the sensitivity and the resolution of the sensitive amplifier are improved.
Description
Technical Field
The utility model relates to an integrated circuit technical field especially relates to a sensitive amplifier.
Background
Random mismatch existing among devices in the sense amplifier can cause mismatch of threshold voltages among the devices, which can cause offset voltage of the sense amplifier to be generated; the offset voltage causes a problem of low sensing threshold (low sense margin) when the sense amplifier reads, so that the sensitivity of the sense amplifier is low, the resolution is low, and reading errors are easily caused.
On the other hand, the small-signal differential input voltage of the sense amplifier is generated by a charge sharing effect (charge sharing), and as the bit line is longer and longer, the parasitic capacitance of the bit line is larger and larger, and at the same time, the storage capacitance is smaller and smaller, which causes the small-signal differential input voltage generated by the charge sharing effect to be smaller and smaller, so that the influence of the offset voltage is more and more significant.
SUMMERY OF THE UTILITY MODEL
In view of this, it is necessary to provide a sense amplifier for solving the problems of the prior art that the sense amplifier has an offset voltage, which results in a low sensitivity and a low resolution of the sense amplifier, and is prone to cause a read error.
The utility model provides a sensitive amplifier, include:
the method comprises the following steps: the device comprises a pre-charging module, a first input/output end, a second input/output end, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit and a second energy storage unit; wherein,
one end of the pre-charging module is connected with a first bit line, and the other end of the pre-charging module is connected with a second bit line, and the pre-charging module is used for pre-charging the first bit line and the second bit line to a preset voltage;
the first input/output end is connected with the first bit line; the second input/output end is connected with the second bit line;
the grid electrode of the first PMOS tube is connected with the second input/output end through the second switch unit, and the drain electrode of the first PMOS tube is connected with the first input/output end through the first switch unit; the grid electrode of the second PMOS tube is connected with the first input/output end through the first switch unit, and the drain electrode of the second PMOS tube is connected with the second input/output end through the second switch unit; the grid electrode of the first NMOS tube is connected with the second input/output end and the first input/output end through the third switch unit, and the drain electrode of the first NMOS tube is connected with the first input/output end through the third switch unit; the grid electrode of the second NMOS tube is connected with the first input/output end and the second input/output end through the fourth switch unit, and the drain electrode of the second NMOS tube is connected with the second input/output end through the fourth switch unit;
one end of the fifth switch unit is connected with a power supply voltage, and the other end of the fifth switch unit is connected with the first input/output end; one end of the sixth switching unit is connected with the power supply voltage, and the other end of the sixth switching unit is connected with the second input/output end;
one end of the first energy storage unit is connected with the first input and output end, and the other end of the first energy storage unit is grounded through the seventh switch unit; one end of the second energy storage unit is connected with the second input and output end, and the other end of the second energy storage unit is grounded through the eighth switching unit;
the first switch unit, the second switch unit, the third switch unit and the fourth switch unit are used for configuring the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor into an amplification mode or a diode mode.
The sensitive amplifier can compensate the offset voltage, so that the offset voltage of the sensitive amplifier is greatly reduced, and the sensitivity and the resolution of the sensitive amplifier are improved.
In an optional embodiment, the sense amplifier further comprises: a ninth switching unit and a tenth switching unit; one end of the ninth switch unit is connected with the first bit line, and the other end of the ninth switch unit is connected with one end of the first energy storage unit; one end of the tenth switch unit is connected with the second bit line, and the other end of the tenth switch unit is connected with one end of the second energy storage unit.
In an optional embodiment, the sense amplifier further comprises: an eleventh switching unit and a twelfth switching unit; one end of the eleventh switch unit is connected with the first bit line, and the other end of the eleventh switch unit is connected with the first input/output end; one end of the twelfth switch unit is connected with the second bit line, and the other end of the twelfth switch unit is connected with the second input/output end.
In an optional embodiment, the sense amplifier further comprises: a first driving pipe and a second driving pipe; one end of the first driving tube is connected with the power supply voltage, and the other end of the first driving tube is connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube; one end of the second driving tube is grounded, and the other end of the second driving tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube.
In an optional embodiment, the first driving transistor comprises a PMOS transistor, a source of the first driving transistor is connected to the power supply voltage, and a drain of the first driving transistor is connected to the source of the first PMOS transistor and the source of the second PMOS transistor; the second driving tube comprises an NMOS tube, the source electrode of the second driving tube is grounded, and the drain electrode of the second driving tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube.
In an optional embodiment, the sense amplifier further includes a first switching tube, a second switching tube, a third energy storage unit, and a fourth energy storage unit; one end of the first switching tube is connected with the first bit line, the other end of the first switching tube is connected with one end of the third energy storage unit, and the other end of the third energy storage unit is grounded; one end of the second switch tube is connected with the second bit line, the other end of the second switch tube is connected with one end of the fourth energy storage unit, and the other end of the fourth energy storage unit is grounded.
In an optional embodiment, the third switching unit comprises a third switching tube and a fifth switching tube, and the fourth switching unit comprises a fourth switching tube and a sixth switching tube;
one end of the third switching tube is connected with the first input/output end, the other end of the third switching tube is connected with the drain electrode of the first NMOS tube, one end of the fifth switching tube is connected with the drain electrode of the first NMOS tube, and the other end of the fifth switching tube is connected with the grid electrode of the first NMOS tube;
one end of the fourth switch tube is connected with the second input and output end, the other end of the fourth switch tube is connected with the drain electrode of the second NMOS tube, one end of the sixth switch tube is connected with the drain electrode of the second NMOS tube, and the other end of the sixth switch tube is connected with the grid electrode of the second NMOS tube.
In an optional embodiment, the third switching tube, the fourth switching tube, the fifth switching tube and the sixth switching tube are all NMOS tubes or transmission gates composed of NMOS tubes and PMOS tubes.
The utility model also provides a control method of sense amplifier in as above-mentioned arbitrary example, include:
a pre-charging stage: precharging the first bit line and the second bit line to a preset voltage;
offset voltage compensation stage: and adjusting the connection modes of the first PMOS tube, the second NMOS tube and the second NMOS tube, and compensating the offset voltage difference between the first input and output ends and the second input and output ends.
According to the control method of the sense amplifier, the offset voltage of the sense amplifier can be greatly reduced by compensating the offset voltage, so that the sensitivity and the resolution of the sense amplifier are improved.
In an alternative embodiment, the offset voltage compensation stage comprises the following steps:
at least the first switch unit, the second switch unit, the third switch unit and the fourth switch unit are placed in an off state, and the fifth switch unit, the sixth switch unit, the seventh switch unit and the eighth switch unit are placed in an on state, so as to charge the first input/output end and the second input/output end to the power supply voltage;
and placing the fifth switch unit and the sixth switch unit in an off state, and short-circuiting the grid electrode of the first NMOS tube with the drain electrode of the first NMOS tube and short-circuiting the grid electrode of the second NMOS tube with the drain electrode of the second NMOS tube so as to discharge the voltage of the first input/output end to the threshold voltage of the second NMOS tube and discharge the voltage of the second input/output end to the threshold voltage of the first NMOS tube.
In an optional embodiment, the offset voltage compensation stage further includes:
small signal amplification stage: connecting the first NMOS tube and the second NMOS tube into an amplification mode, and amplifying the voltage difference between the first input/output end and the second input/output end; connecting the first PMOS tube and the second PMOS tube into an amplification mode, and pulling up the voltage of the first input/output end or the second input/output end to the power supply voltage;
and a write-back stage: write back is performed on the first bit line.
Drawings
Fig. 1 is a circuit diagram of a sense amplifier provided in an embodiment of the present invention in a precharge state;
fig. 2 to fig. 3 are circuit diagrams of a sense amplifier provided in an embodiment of the present invention when the sense amplifier is in an offset voltage compensation state;
fig. 4 to 6 are circuit diagrams of a sense amplifier provided in an embodiment of the present invention when the sense amplifier is in a small signal amplification state;
fig. 7 is a circuit diagram of a sense amplifier in a write-back state according to an embodiment of the present invention.
Description of the reference numerals
11 precharge module
12 third switching unit
13 fourth switching unit
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In the description of the present invention, it is to be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the methods or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore, should not be construed as limiting the present invention.
In one embodiment, as shown in fig. 1-7, the present invention provides a sense amplifier comprising: the energy storage device comprises a precharging module 11, a first input/output end N1, a second input/output end N2, a first PMOS tube MP1, a second PMOS tube MP2, a first NMOS tube MN1, a second NMOS tube MN2, a first switch unit K1, a second switch unit K2, a third switch unit 12, a fourth switch unit 13, a fifth switch unit K5, a sixth switch unit K6, a seventh switch unit K7, an eighth switch unit K8, a first energy storage unit C1 and a second energy storage unit C2; one end of the pre-charging module 11 is connected to the first bit line BLT, and the other end is connected to the second bit line BLC, and the pre-charging module 11 is configured to pre-charge the first bit line BLT and the second bit line BLC to a predetermined voltage; the first input/output terminal N1 is connected to the first bit line BLT; the second input/output terminal N2 is connected to the second bit line BLC; the gate of the first PMOS transistor MP1 is connected to the second input/output terminal N2 through the second switch unit K2, and the drain of the first PMOS transistor MP1 is connected to the first input/output terminal N1 through the first switch unit K1; the gate of the second PMOS transistor MP2 is connected to the first input/output terminal N1 through the first switch unit K1, and the drain of the second PMOS transistor MP2 is connected to the second input/output terminal N2 through the second switch unit K2; the gate of the first NMOS transistor MN1 is connected to the second input/output terminal N2, and is connected to the first input/output terminal N1 through the third switching unit 12, and the drain of the first NMOS transistor N1 is connected to the first input/output terminal N1 through the third switching unit 12; the gate of the second NMOS transistor MN2 is connected to the first input/output terminal N1, and is connected to the second input/output terminal N2 through the fourth switching unit 13, and the drain of the second NMOS transistor MN2 is connected to the second input/output terminal N2 through the fourth switching unit 13; one end of the fifth switch unit K5 is connected to the power supply voltage VDD, and the other end is connected to the first input/output terminal N1; one end of the sixth switching unit K6 is connected to the power supply voltage VDD, and the other end is connected to the second input/output terminal N2; one end of the first energy storage unit C1 is connected to the first input/output end N1, and the other end is grounded via the seventh switch unit K7; one end of the second energy storage unit C2 is connected to the second input/output end N2, and the other end is grounded via the eighth switch unit K8; the first switch unit K1, the second switch unit K2, the third switch unit 12 and the fourth switch unit 13 are used for configuring the first PMOS transistor MP1, the second PMOS transistor MP2, the first NMOS transistor MN1 and the second NMOS transistor MN2 as an amplification mode or a diode mode.
The sensitive amplifier can compensate the offset voltage, so that the offset voltage of the sensitive amplifier is greatly reduced, and the sensitivity and the resolution of the sensitive amplifier are improved.
In one example, the sense amplifier further comprises: a ninth switching unit K9 and a tenth switching unit K10; one end of the ninth switching unit K9 is connected to the first bit line BLT, and the other end is connected to one end of the first energy storage unit C1; one end of the tenth switching unit K10 is connected to the second bit line BLC, and the other end is connected to one end of the second energy storing unit C2.
In one example, the sense amplifier further comprises: an eleventh switching unit K11 and a twelfth switching unit K12; one end of the eleventh switching unit K11 is connected to the first bit line BLT, and the other end is connected to the first input/output terminal N1; one end of the twelfth switching unit K12 is connected to the second bit line BLC, and the other end is connected to the second input/output terminal N2.
In the above example, the first switch unit K1, the second switch unit K2, the fifth switch unit K5, the sixth switch unit K6, the seventh switch unit K7, the eighth switch unit K8, the ninth switch unit K9, the tenth switch unit K10, the eleventh switch unit K11, and the twelfth switch unit K12 may each be an NMOS transistor or a transmission gate composed of an NMOS transistor and a PMOS transistor.
In one example, the sense amplifier further comprises: a first driving pipe M1 and a second driving pipe M2; one end of the first driving tube M1 is connected with a power voltage VDD, and the other end is connected with the source electrode of the first PMOS tube MP1 and the source electrode of the second PMOS tube MP 2; one end of the second driving tube M2 is grounded, and the other end is connected with the source electrode of the first NMOS tube MN1 and the source electrode of the second NMOS tube MN2
Specifically, the first driving transistor M1 includes a PMOS transistor, the source of the first driving transistor M1 is connected to the power voltage VDD, and the drain of the first driving transistor M1 is connected to the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP 2; the second driving transistor M2 includes an NMOS transistor, the source of the second driving transistor M2 is grounded, and the drain of the second driving transistor M2 is connected to the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN 2.
In one example, the sense amplifier further includes a first switch M3, a second switch M4, a third energy storage unit C3, and a fourth energy storage unit C4; one end of the first switching tube M3 is connected to the first bit line BLT, the other end is connected to one end of the third energy storage unit C3, and the other end of the third energy storage unit C3 is grounded; one end of the second switch transistor M4 is connected to the second bit line BLC, the other end is connected to one end of the fourth energy storage unit C4, and the other end of the fourth energy storage unit C4 is grounded
In one example, the first switch M3 may be an NMOS transistor, the drain of the first switch M3 is connected to the first bit line BLT, and the source of the first switch M3 is connected to the third energy storage unit C3; the second switch M4 may be an NMOS transistor, the drain of the second switch M4 is connected to the second bit line BLC, and the source of the second switch M4 is connected to the fourth energy storage unit C4.
In one example, the third switching unit 12 includes a third switching tube K31 and a fifth switching tube K32, and the fourth switching unit 13 includes a fourth switching tube K41 and a sixth switching tube K42; one end of a third switching tube K31 is connected with a first input/output end N1, the other end of the third switching tube K31 is connected with the drain electrode of a first NMOS tube MN1, one end of a fifth switching tube K32 is connected with the drain electrode of a first NMOS tube MN1, and the other end of the fifth switching tube K32 is connected with the gate electrode of a first NMOS tube MN 1; one end of a fourth switching tube K41 is connected with the second input/output end N2, the other end of the fourth switching tube K41 is connected with the drain electrode of the second NMOS tube MN2, one end of a sixth switching tube K42 is connected with the drain electrode of the second NMOS tube MN2, and the other end of the sixth switching tube K42 is connected with the gate electrode of the second NMOS tube MN 2.
In one example, the third switch tube K31, the fourth switch tube K41, the fifth switch tube K32 and the sixth switch tube K4 are all transmission gates composed of NMOS tubes or NMOS tubes and PMOS tubes.
The utility model also provides a control method of above-mentioned sensitive amplifier, include:
a pre-charging stage: precharging the first bit line BLT and the second bit line BLC to a predetermined voltage;
offset voltage compensation stage: the connection modes of the first PMOS transistor MP1, the second PMOS transistor MP2, the second NMOS transistor MN1 and the second NMOS transistor MN2 are adjusted to compensate the offset voltage difference between the first input/output terminal N1 and the second input/output terminal N2.
In one example, as shown in fig. 1, the first and second bit lines BLT and BLC are precharged to a predetermined voltage using a precharge (EQ) module 11. When the precharge is completed, the precharge module 11 is turned off. Specifically, the preset voltage may be a half of the power voltage, or a half of the preset voltage and a half of the threshold voltage of the first switch transistor M3 or the second switch transistor M4.
In one example, the offset voltage compensation phase comprises the following steps: first, at least the first switch unit K1, the second switch unit K2, the third switch unit 12, and the fourth switch unit 13 are turned off, specifically, the first switch unit K1, the second switch unit K2, the eleventh switch unit K11, the twelfth switch unit K12, the third switch unit 12, and the fourth switch unit 13 are all turned off, and the fifth switch unit K5, the sixth switch unit K6, the seventh switch unit K7, and the eighth switch unit K8 are turned on, as shown in fig. 2, so as to charge the first input/output terminal N1 and the second input/output terminal N2 to the power voltage VDD; then, the fifth switch unit K5 and the sixth switch unit K6 are turned off, the gate of the first NMOS transistor MN1 is shorted with the drain of the first NMOS transistor MN1, and the gate of the second NMOS transistor MN2 is shorted with the drain of the second NMOS transistor MN2 as shown in fig. 3, so as to discharge the voltage of the first input/output terminal N1 to the threshold voltage of the second NMOS transistor MN2, and discharge the voltage of the second input/output terminal N2 to the threshold voltage of the first NMOS transistor MN1, specifically, in this process, the threshold voltage of the first NMOS transistor MN1 is stored in the second energy storage unit C2, and the threshold voltage of the second NMOS transistor MN2 is stored in the first energy storage unit C1.
In one example, the offset voltage compensation stage further comprises:
small signal amplification stage: the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to be in an amplification mode, and the voltage difference between the first input/output end N1 and the second input/output end N2 is amplified; the first PMOS transistor MP1 and the second PMOS transistor MP2 are also connected to an amplifying mode, and the voltage of the first input/output terminal N1 or the second input/output terminal N2 is pulled up to the power voltage VDD;
and a write-back stage: write back is performed on the first bit line BLT.
Specifically, the small signal amplification stage specifically includes: first, the voltage of the control terminal of the first switch M3 is switched from low level to high level, so that the first switch M3 is turned on, and the third energy storage unit C3 is connected to the first bit line BLT, as shown in fig. 4, when the voltage of the third energy storage unit C3 is lower than the voltage of the first bit line BLT, the first bit line BLT charges the third energy storage unit C3, and when the voltage of the third energy storage unit C3 is higher than the voltage of the first bit line BLT, the third energy storage unit C3 charges the first bit line BLT; next, the ninth switch unit K9 and the tenth switch unit K10 are turned off, and the seventh switch unit K7 and the eighth switch unit K8 are turned on, as shown in fig. 5, since the voltages at the two ends of the first energy storage unit C1 and the second energy storage unit C2 cannot suddenly change, at this time, the voltage at the first input/output end N1 is the sum of the threshold voltage of the second NMOS transistor MN2 and the voltage at the first bit line BLT, the voltage at the second input/output end N2 is the sum of the threshold voltage of the first NMOS transistor NM1 and the voltage at the second bit line BLT, the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected in an amplification mode, so as to amplify the differential input signal, at this time, the first PMOS transistor MP1 and the second PMOS transistor MP2 are not involved in the amplification process, if the third energy storage unit C3 charges the first bit line BLT in the process of fig. 5, then the voltage at the first input/output end N1 is greater than the voltage at the second input/output end N2, if the third energy storage unit C3 in the process of fig. 4, the voltage at the first input/output terminal N1 is less than the voltage at the second input/output terminal N2 in the process of fig. 5; finally, the first switch unit K1 and the second switch unit K2 are closed to connect the first PMOS transistor MP1 and the second PMOS transistor MP2, as shown in fig. 6, the voltage SAP at the control end of the first driving transistor M1 is pulled down to turn on the first driving transistor M1, the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected in an amplification mode, and the first input/output terminal N1 or the second input/output terminal N2 is pulled up to the power supply voltage VDD by the first PMOS transistor MP1 and the second PMOS transistor MP 2; specifically, before the process shown in fig. 6, if the voltage of the first input/output terminal N1 is greater than the voltage of the second input/output terminal N2, the pull-up capability of the first PMOS transistor MP1 is enhanced, the pull-down capability of the first NMOS transistor MN1 is reduced, the voltage of the first input/output terminal N1 is pulled up to the power voltage VDD, meanwhile, the pull-up capability of the second PMOS transistor MP2 is reduced, the pull-down capability of the second NMOS transistor MN2 is enhanced, and the voltage of the second input/output terminal N2 is pulled down slowly to the ground voltage (GND); before the process shown in fig. 6, if the voltage of the first input/output terminal N1 is lower than the voltage of the second input/output terminal N2, the pull-up capability of the second PMOS transistor MP2 is enhanced, the pull-down capability of the second NMOS transistor MN2 is reduced, the voltage of the second input/output terminal N2 is pulled up to the power voltage VDD, meanwhile, the pull-up capability of the first PMOS transistor MP1 is reduced, the pull-down capability of the first NMOS transistor MN1 is enhanced, and the voltage of the first input/output terminal N1 is pulled down to the ground voltage. It should be noted that, during the small-signal amplification stage, since the voltage at the first input/output terminal N1 and the voltage at the second input/output terminal N2 are already separated by a larger value, that is, the voltage at the first input/output terminal N1 and the voltage at the second input/output terminal N2 are different from each other, the mismatch between the first PMOS transistor MP1 and the second PMOS transistor MP2 is not enough to cause a read error.
In one example, as shown in fig. 7, the write-back stage is specifically: placing eleventh switching unit K11 in a closed state to write back first bit line BLT; more specifically, the method comprises the following steps: the ninth switching unit S9 is turned off, and the eleventh switching unit K11 is turned on, and the first input and output terminal N1 charges the third energy storage unit C3 to implement the write back to the first bit line BLT.
It should be noted that, the tenth switching unit K10 may also be turned off, the twelfth switching unit K12 may also be turned on, and the second input/output terminal N2 charges the fourth energy storage unit C4, so as to implement write-back on the second bit line BLC.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only represent some embodiments of the present invention, and the description thereof is more specific and detailed, but not to be construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, without departing from the spirit of the present invention, several variations and modifications can be made, which are within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the appended claims.
Claims (8)
1. A sense amplifier, comprising: the device comprises a pre-charging module, a first input/output end, a second input/output end, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit, a sixth switch unit, a seventh switch unit, an eighth switch unit, a first energy storage unit and a second energy storage unit; wherein,
one end of the pre-charging module is connected with a first bit line, and the other end of the pre-charging module is connected with a second bit line, and the pre-charging module is used for pre-charging the first bit line and the second bit line to a preset voltage;
the first input/output end is connected with the first bit line; the second input/output end is connected with the second bit line;
the grid electrode of the first PMOS tube is connected with the second input/output end through the second switch unit, and the drain electrode of the first PMOS tube is connected with the first input/output end through the first switch unit; the grid electrode of the second PMOS tube is connected with the first input/output end through the first switch unit, and the drain electrode of the second PMOS tube is connected with the second input/output end through the second switch unit; the grid electrode of the first NMOS tube is connected with the second input/output end and the first input/output end through the third switch unit, and the drain electrode of the first NMOS tube is connected with the first input/output end through the third switch unit; the grid electrode of the second NMOS tube is connected with the first input/output end and the second input/output end through the fourth switch unit, and the drain electrode of the second NMOS tube is connected with the second input/output end through the fourth switch unit;
one end of the fifth switch unit is connected with a power supply voltage, and the other end of the fifth switch unit is connected with the first input/output end; one end of the sixth switching unit is connected with the power supply voltage, and the other end of the sixth switching unit is connected with the second input/output end;
one end of the first energy storage unit is connected with the first input and output end, and the other end of the first energy storage unit is grounded through the seventh switch unit; one end of the second energy storage unit is connected with the second input and output end, and the other end of the second energy storage unit is grounded through the eighth switching unit;
the first switch unit, the second switch unit, the third switch unit and the fourth switch unit are used for configuring the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor into an amplification mode or a diode mode.
2. The sense amplifier of claim 1, further comprising: a ninth switching unit and a tenth switching unit; one end of the ninth switch unit is connected with the first bit line, and the other end of the ninth switch unit is connected with one end of the first energy storage unit; one end of the tenth switch unit is connected with the second bit line, and the other end of the tenth switch unit is connected with one end of the second energy storage unit.
3. The sense amplifier of claim 1, further comprising: an eleventh switching unit and a twelfth switching unit; one end of the eleventh switch unit is connected with the first bit line, and the other end of the eleventh switch unit is connected with the first input/output end; one end of the twelfth switch unit is connected with the second bit line, and the other end of the twelfth switch unit is connected with the second input/output end.
4. The sense amplifier of claim 1, further comprising: a first driving pipe and a second driving pipe; one end of the first driving tube is connected with the power supply voltage, and the other end of the first driving tube is connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube; one end of the second driving tube is grounded, and the other end of the second driving tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube.
5. The sense amplifier of claim 4, wherein the first driving transistor comprises a PMOS transistor, a source of the first driving transistor is connected to the power supply voltage, and a drain of the first driving transistor is connected to the source of the first PMOS transistor and the source of the second PMOS transistor; the second driving tube comprises an NMOS tube, the source electrode of the second driving tube is grounded, and the drain electrode of the second driving tube is connected with the source electrode of the first NMOS tube and the source electrode of the second NMOS tube.
6. The sense amplifier of claim 1, further comprising a first switch tube, a second switch tube, a third energy storage unit, and a fourth energy storage unit; one end of the first switching tube is connected with the first bit line, the other end of the first switching tube is connected with one end of the third energy storage unit, and the other end of the third energy storage unit is grounded; one end of the second switch tube is connected with the second bit line, the other end of the second switch tube is connected with one end of the fourth energy storage unit, and the other end of the fourth energy storage unit is grounded.
7. The sense amplifier of claim 6, wherein the third switching unit comprises a third switching tube and a fifth switching tube, and the fourth switching unit comprises a fourth switching tube and a sixth switching tube;
one end of the third switching tube is connected with the first input/output end, the other end of the third switching tube is connected with the drain electrode of the first NMOS tube, one end of the fifth switching tube is connected with the drain electrode of the first NMOS tube, and the other end of the fifth switching tube is connected with the grid electrode of the first NMOS tube;
one end of the fourth switch tube is connected with the second input and output end, the other end of the fourth switch tube is connected with the drain electrode of the second NMOS tube, one end of the sixth switch tube is connected with the drain electrode of the second NMOS tube, and the other end of the sixth switch tube is connected with the grid electrode of the second NMOS tube.
8. The sense amplifier of claim 7, wherein the third, fourth, fifth and sixth switching tubes are all NMOS tubes or transmission gates composed of NMOS and PMOS tubes.
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