CN210516733U - vertical semiconductor device - Google Patents

Abstract

A vertical type semiconductor device is disclosed. According to an embodiment, a semiconductor device may include: a substrate; a first source/drain layer, a channel layer and a second source/drain layer sequentially stacked on the substrate; and a gate stack formed around a periphery of the channel layer. The channel layer includes a first semiconductor material layer and a second semiconductor material layer formed around the periphery of the first semiconductor material layer. The source/drain regions formed in the first source/drain layer and the second source/drain layer, respectively, are at least partially connected to the first source/drain layer, the channel layer and the second source/drain layer in the stacking direction of the first source/drain layer, the channel layer and the second source/drain layer. A layer of semiconductor material and a second layer of semiconductor material overlap such that a channel region can be formed in both the first layer of semiconductor material and the second layer of semiconductor material.

Description

Vertical semiconductor device

Technical Field

The present disclosure relates to the field of semiconductors, and in particular, to vertical type semiconductor devices.

Background

In a horizontal type device such as a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), a source, a gate, and a drain are arranged in a direction substantially parallel to a surface of a substrate. Due to this arrangement, the area occupied by the horizontal type device is not easily further reduced or the manufacturing cost is not easily further reduced. Unlike this, in the vertical type device, the source, the gate, and the drain are arranged in a direction substantially perpendicular to the substrate surface. Therefore, the vertical type device is more easily scaled down or the manufacturing cost is more easily reduced than the horizontal type device. Nanowire (nanowire) Vertical-type surrounding Gate Field Effect transistors (V-GAAFET, Vertical Gate-all-around Field Effect Transistor) are one of the candidates for future high performance devices.

However, for vertical devices, it is difficult to control the gate length, especially for monocrystalline channel materials. If a polycrystalline channel material is used, the channel resistance increases significantly relative to a single crystal material, making it difficult to stack multiple vertical devices, as this can result in too high a resistance. On the other hand, effectively adjusting the threshold voltage of the device and improving the performance of the device also face great challenges.

SUMMERY OF THE UTILITY MODEL

In view of the above, it is an object of the present disclosure, at least in part, to provide a vertical type semiconductor device having improved performance.

According to an aspect of the present disclosure, there is provided a semiconductor device including: a substrate; a first source/drain layer, a channel layer and a second source/drain layer sequentially stacked on a substrate; and a gate stack formed around an outer periphery of the channel layer. The channel layer includes a first semiconductor material layer and a second semiconductor material layer formed around an outer periphery of the first semiconductor material layer. The source/drain regions respectively formed in the first source/drain layer and the second source/drain layer at least partially overlap the first semiconductor material layer, the second semiconductor material layer in a stacking direction of the first source/drain layer, the channel layer, and the second source/drain layer, so that the channel region can be formed in both the first semiconductor material layer and the second semiconductor material layer.

According to an embodiment, the first semiconductor material layer, the second semiconductor material layer, and the gate dielectric layer in the gate stack may form a quantum well structure.

According to an embodiment, the second semiconductor material layer may form a heterojunction with respect to at least one of the first source/drain layer, the second source/drain layer, and the first semiconductor material layer.

According to an embodiment, an interfacial layer may be present between the first semiconductor material layer and the second semiconductor material layer.

According to an embodiment, the first semiconductor material layer may be aligned with the first and second source/drain layers in the stacking direction, and an outer circumference thereof may be recessed with respect to an outer circumference of the first and second source/drain layers, and the second semiconductor material layer may be at least partially formed in a recess formed in the outer circumference of the first semiconductor material layer with respect to the outer circumference of the first and second source/drain layers.

According to an embodiment, the second semiconductor material layer may be further formed on sidewalls of the second source/drain layer.

According to an embodiment, the thickness of the second semiconductor material layer may be about 2-10 nm.

According to an embodiment, the thickness of the second layer of semiconductor material may be smaller than the smallest dimension of the first layer of semiconductor material. For example, the first layer of semiconductor material may be a nanowire, and the smallest dimension may be a diameter of the nanowire; or the first layer of semiconductor material may be a nanoplate, and the smallest dimension may be the thickness of the nanoplate.

According to an embodiment, the source/drain regions comprise doped regions in the first and second source/drain layers, said doped regions extending into the first layer of semiconductor material.

According to embodiments of the present disclosure, heterojunctions may be used to improve device performance, such as enhancing mobility, improving short channel effects, and the like. In addition, due to the presence of the second semiconductor material layer (low doped or undoped), the capacitance between the gate and the source/drain can be reduced and thus the Alternating Current (AC) characteristics of the device can be improved.

According to an embodiment of the present disclosure, a gate stack is formed around an outer circumference of a channel layer and a channel is formed in the channel layer, such that a gate length is determined by a thickness of the channel layer. The channel layer may be formed by, for example, epitaxial growth, so that its thickness can be well controlled. Therefore, the gate length can be well controlled. The channel layer may be a single crystal semiconductor material and may have high carrier mobility and low leakage current, thereby improving device performance.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present disclosure with reference to the accompanying drawings, in which:

fig. 1 to 12 show schematic diagrams of a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure; and

fig. 13 and 14 show schematic diagrams of a middle staging section of a process for manufacturing a semiconductor device according to another embodiment of the present disclosure.

Throughout the drawings, the same or similar reference numerals denote the same or similar components.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

A vertical-type semiconductor device according to an embodiment of the present disclosure may include a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked in a vertical direction (e.g., substantially perpendicular to a substrate surface) on a substrate. The layers may be adjacent to each other, although other semiconductor layers, such as a leakage suppressing layer and an on-current enhancing layer (a semiconductor layer having a larger or smaller band gap than the adjacent layers) may be present in between. Source/drain regions of the device may be formed in the first source/drain layer and the second source/drain layer, and a channel region of the device may be formed in the channel layer. Such a semiconductor device may be a conventional Field Effect Transistor (FET) according to embodiments of the present disclosure. In the case of a FET, the source/drain regions formed in the first and second source/drain layers may have the same conductivity type (e.g., n-type or p-type) doping. A conductive path may be formed through the channel region between the source/drain regions at both ends of the channel region. Alternatively, such a semiconductor device may be a tunneling FET. In the case of a tunneling FET, the source/drain regions formed in the first and second source/drain layers may have different conductivity type (e.g., n-type and p-type, respectively) doping. In this case, charged particles, such as electrons, may tunnel from the source region through the channel region and into the drain region, thereby forming a conductive path between the source and drain regions. Although the conduction mechanisms in conventional FETs and tunneling FETs are not the same, they both exhibit electrical properties that allow control of conduction between source/drain regions via the gate. Thus, for conventional FETs and punch-through FETs, the terms "source/drain layer (source/drain region)" and "channel layer (channel region)" are collectively described, although there is no "channel" in the usual sense in a tunnel FET.

The gate stack may be formed around an outer periphery of the channel layer. The channel layer may include a first semiconductor material layer and a second semiconductor material layer formed around an outer periphery of the first semiconductor material layer. The second semiconductor material layer may include a semiconductor material having different material characteristics from the first semiconductor material layer. To match the two material layers, an interfacial layer may be present between them. The first and second layers of semiconductor material may have different doping characteristics (typically, they may be unintentionally doped or lightly doped as a channel region).

The second semiconductor material layer may form a heterojunction with respect to at least one of the first source/drain layer, the second source/drain layer, and the first semiconductor material layer. Due to such a heterojunction, device performance may be improved, for example, carrier mobility may be improved. For an n-type device, the electron concentration in the second semiconductor material layer in the on-state of the device may be greater than the electron concentration in the first semiconductor material layer, and thus for an n-type device, a semiconductor material with high electron mobility may be preferred as the second semiconductor material layer; for a p-type device, the hole concentration in the second semiconductor material layer in the on-state of the device may be greater than the hole concentration in the first semiconductor material layer, and therefore for a p-type device, a semiconductor material with large hole mobility may be preferred as the second semiconductor material layer. For example, for an n-type device, the conduction band energy level of the second semiconductor material layer may be lower than the conduction band energy level of the first semiconductor material layer; for a p-type device, the valence band energy level of the second semiconductor material layer may be higher than the valence band energy level of the first semiconductor material layer. By this band setting, carriers (electrons or holes) can be substantially confined in the second semiconductor material layer.

According to an embodiment, for an n-type device, an electron concentration profile in an on-state of the device due to the presence of the second semiconductor material layer is further from an interface between the gate dielectric layer and the semiconductor material layer than with the first semiconductor material layer alone to reduce scattering of electrons by the interface or to increase mobility of electrons, in which case the potential energy of electrons at the second semiconductor material layer is preferably higher than the potential energy at the first semiconductor material layer. Similarly, for a p-type device, the hole concentration profile in the on-state of the device due to the presence of the second semiconductor material layer is further from the interface between the gate dielectric layer and the semiconductor material layer than when only the first semiconductor material layer is used, to reduce scattering of holes by the interface or to increase mobility of holes, in which case it is preferable that the potential energy of holes is higher in the second semiconductor material layer than in the first semiconductor material layer.

In addition, the interface property between the gate dielectric material and the semiconductor material can be optimized by using the second semiconductor material layer, for example, the interface defect state is adjusted to achieve the purposes of adjusting the threshold value of the device and improving the performance of the device.

In addition, the gate dielectric, the second semiconductor material layer, and the first semiconductor material layer in the gate stack may form a quantum well structure. The first and second layers of semiconductor material may be formed and/or doped separately and thus may be relatively easily formed with different doping characteristics and/or different material characteristics (e.g., energy band characteristics to form a quantum well) as desired.

The first semiconductor material layer and the second semiconductor material layer included in the channel layer may be composed of a single crystal semiconductor material to improve device performance. Of course, the first and second source/drain layers may be formed of a single crystal semiconductor material. In this case, the single crystal semiconductor material of the channel layer and the single crystal semiconductor material of the source/drain layer may have the same crystal structure.

According to an embodiment of the present disclosure, the gate length may be determined by the thickness of the channel layer itself, rather than depending on the etching time as in the conventional art. The channel layer may be formed by, for example, epitaxial growth, so that its thickness can be well controlled. Therefore, the gate length can be well controlled.

The outer periphery of the first semiconductor material layer may be recessed inward with respect to the outer periphery of the first and second source/drain layers, and the second semiconductor material layer may be at least partially formed in the recess formed in the outer periphery of the first semiconductor material layer with respect to the outer periphery of the first and second source/drain layers.

In addition, the channel layer may be recessed inward as a whole with respect to outer peripheries of the first and second source/drain layers. In this way, the formed gate stack may be embedded in a recess of the channel layer with respect to the first and second source/drain layers, reducing or even avoiding overlap with the source/drain regions, which may help to reduce parasitic capacitance between the gate and the source/drain.

According to an embodiment of the present disclosure, the source/drain region may be formed in the first source/drain layer, the second source/drain layer, and may at least partially overlap the channel layer (including the first semiconductor material layer and the second semiconductor material layer) in the vertical direction, so that the channel region can be formed in both the first semiconductor material layer and the second semiconductor material layer. The doping for the source/drain regions may partially enter the channel layer (particularly the first layer of semiconductor material) near the ends of the source/drain regions. This helps to reduce the resistance between the source/drain region and the channel region when the device is on, thereby improving device performance.

According to an embodiment of the present disclosure, a channel layer (including a first semiconductor material layer and a second semiconductor material layer) may include a semiconductor material having an etch selectivity with respect to first and second source/drain layers. In this way, it is advantageous to process, e.g., selectively etch, the channel layer to be recessed with respect to the first and second source/drain layers. In addition, the first source/drain layer and the second source/drain layer may include the same semiconductor material.

For example, the first source/drain layer may be a semiconductor layer epitaxially grown on the substrate, the first semiconductor material layer may be a semiconductor layer epitaxially grown on the first source/drain layer, the second source/drain layer may be a semiconductor layer epitaxially grown on the channel layer, and the second semiconductor material layer may be a semiconductor layer epitaxially grown on the first semiconductor material layer. Due to epitaxial growth, at least a portion of adjacent layers may have a sharp crystalline interface therebetween.

Such a semiconductor device can be manufactured, for example, as follows. Specifically, a stack of a first source/drain layer, a first semiconductor material layer, and a second source/drain layer may be provided on a substrate. As described above, the stack may be formed by epitaxially growing a first source/drain layer on a substrate, epitaxially growing a first semiconductor material layer on the first source/drain layer, and epitaxially growing a second source/drain layer on the first semiconductor material layer. During epitaxial growth, the thickness of the grown layers, in particular the first layer of semiconductor material, can be controlled.

For the first source/drain layer, the first semiconductor material layer, and the second source/drain layer stacked, an active region may be defined therein. For example, they may be selectively etched into a desired shape in turn. In general, the active region may have a columnar shape (e.g., a cylindrical shape). In order to facilitate connection of source/drain regions formed in the first source/drain layer in a subsequent process, the first source/drain layer may be etched only for an upper portion of the first source/drain layer so that a lower portion of the first source/drain layer may extend beyond a periphery of the upper portion thereof. The outer perimeter of the first layer of semiconductor material may be recessed relative to the outer perimeter of the first and second source/drain layers to define a space to accommodate the second layer of semiconductor material, the gate stack. This can be achieved, for example, by selective etching. Then, a second semiconductor material layer may be formed in a recess formed in an outer periphery of the first semiconductor material layer with respect to outer peripheries of the first and second source/drain layers, and a gate stack may be formed around the outer periphery of the second semiconductor material layer. The gate stack may be embedded in the recess.

The first layer of semiconductor material may be lightly doped. This may be accomplished, for example, by in-situ doping as the first semiconductor material channel layer is grown, or by driving dopants into the first semiconductor material layer. Of course, the first semiconductor material layer may also be undoped, but with a material appropriately selected (e.g., according to its energy band characteristics) for subsequent formation of well wall portions of the heterojunction or quantum well. Of course, the first semiconductor material layer may form a quantum well structure while being doped.

Source/drain regions may be formed in the first and second source/drain layers. This may be achieved, for example, by doping the first and second source/drain layers. For example, ion implantation, plasma doping, or the like may be performed. According to an advantageous embodiment, the position-maintaining layer may be formed in a recess formed in the outer periphery of the first semiconductor material layer with respect to the outer periphery of the first and second source/drain layers, and then the dopant source layer may be formed on the surface of the first and second source/drain layers, and the dopant in the dopant source layer may be introduced into the first and second source/drain layers by, for example, annealing. The position-retaining layer may prevent dopants in the dopant source layer from directly entering the first semiconductor material layer. However, there may be some dopant that enters the first semiconductor material layer near the ends of the first and second source/drain layers through the first and second source/drain layers.

The present disclosure may be presented in various forms, some examples of which are described below.

Fig. 1 to 12 show schematic diagrams of a flow of manufacturing a semiconductor device according to an embodiment of the present disclosure.

As shown in fig. 1, a substrate 1001 is provided. The substrate 1001 may be a substrate of various forms including, but not limited to, a bulk semiconductor material substrate such as a bulk Si substrate, a semiconductor-on-insulator (SOI) substrate, a compound semiconductor substrate such as a SiGe substrate, and the like. In the following description, a bulk Si substrate is described as an example for convenience of explanation.

According to embodiments of the present disclosure, a heterojunction structure is advantageously formed. To improve the quality of other layers of semiconductor material that are grown later, a buffer layer 1031 may be formed on substrate 1001, for example by epitaxial growth. In this example, the buffer layer 1031 may include Si_1-xGe_x(x is between 0 and 1). The buffer layer 1031 is relaxed at least on top of it.

On the buffer layer 1031, a first semiconductor material layer 1003 and another semiconductor material layer 1005 may be sequentially formed by, for example, epitaxial growth. For example, the first semiconductor material layer 1003 may include Si_1-yGe_y(y is between 0 and 1) and a thickness of about 10-100 nm; the further semiconductor material layer 1005 may comprise Si_1-zGe_z(z is between 0 and 1) and a thickness of about 20-50 nm. Here, the composition of the first semiconductor material channel layer 1003 may be different from the composition of the buffer layer 1031 and the other semiconductor material layer 1005 (y is different from x and z) in order to achieve etch selectivity. The buffer layer 1031 and the another semiconductor material layer 1005 may have the same composition (x ═ z) or different compositions.

Of course, the material selection of each semiconductor layer is not limited thereto. For example, the buffer layer 1031, the first semiconductor material layer 1003 and the other semiconductor material layer 1005 may include one of a group IV semiconductor material or a group III-V compound semiconductor such as Ge, SiGeSn, GeSn, GaAs, InGaAs, InP, A1GaAs, InAlAs, InAs, InGa, InAlGa, GaN, InSb, InGaSb or a combination thereof.

For the first semiconductor material layer 1003, it may be doped to some extent so as to adjust the device threshold (V)_th). Such doping may be obtained, for example, by ion implantation into the first layer of semiconductor material 1003 or by in-situ doping while growing the first layer of semiconductor material 1003. If an n-type device is to be formed, a p-type doping (e.g., at a concentration of about 1E17-2E19 cm) may be formed^-3B or In impurity of (a); whereas if a p-type device is to be formed, an n-type doping (e.g., at a concentration of about 1E17-2E19 cm) may be formed^-3As or P impurities of).

Next, the active region of the device may be defined. This may be done, for example, as follows. Specifically, as shown in fig. 2(a) and 2(b) (fig. 2(a) is a sectional view, and fig. 2(b) is a top view, in which an AA' line shows a position where a section is taken out), a photoresist (not shown) may be formed on the stack of the buffer layer 1031, the first semiconductor material layer 1003, and the other semiconductor material layer 1005 shown in fig. 1, the photoresist may be patterned into a desired shape (in this example, a substantially circular shape) by photolithography (exposure and development), and the other semiconductor material layer 1005, the first semiconductor material layer 1003, and the buffer layer 1031 may be selectively etched, such as Reactive Ion Etching (RIE), in sequence using the patterned photoresist as a mask. The etching proceeds into the buffer layer 1031, but not to the bottom surface of the buffer layer 1031. Then, the upper portions of the etched semiconductor material layer 1005, the etched first semiconductor material layer 1003, and the buffer layer 1031 form a columnar shape (in this example, a columnar shape). The RIE may, for example, be performed in a direction generally perpendicular to the substrate surface such that the pillar is also generally perpendicular to the substrate surface. Thereafter, the photoresist may be removed.

Here, a substantially cylindrical active region is formed, and then a nanowire device may be formed. However, the present disclosure is not limited thereto. For example, the photoresist may be patterned into a rectangle so that a substantially hexahedral active region may be formed, and thus a nanosheet device may be formed.

Then, as shown in fig. 3, the outer periphery of the first semiconductor material layer 1003 may be recessed with respect to the outer periphery of the buffer layer 1031 and the other semiconductor material layer 1005 (in this example, recessed in a lateral direction substantially parallel to the substrate surface). This may be achieved, for example, by further selectively etching the first layer of semiconductor material 1003 relative to the buffer layer 1031 and the further layer of semiconductor material 1005. To accurately control the etch depth, Atomic Layer Etching (ALE) may be used.

In the recess formed by the first semiconductor material layer 1003 with respect to the upper portion of the buffer layer 1031 and the outer circumference of the other semiconductor material layer 1005, the second semiconductor material layer will be formed later. The second layer of semiconductor material together with the previously formed buffer layer 1031, first layer of semiconductor material 1003 and further layer of semiconductor material 1005 will constitute the active region of the device. In order to avoid unnecessary influence on the second semiconductor material layer by the subsequent operation of forming the source/drain regions (doping operation), the source/drain regions may be formed first and then the second semiconductor material layer may be formed.

In addition, in order to avoid that subsequent processing affects the first semiconductor material layer 1003 or leaves unnecessary material in the recess to affect the performance of subsequent processes, a material layer may be filled in the recess to occupy a space in which the recess is maintained (therefore, the material layer may be referred to as a "position maintaining layer"). This may be accomplished, for example, by depositing nitride on the structure shown in fig. 3, and then etching back the deposited nitride, such as RIE. RIE may be performed in a direction substantially perpendicular to the substrate surface and nitride may be left only in the recesses to form the position retaining layer 1007, as shown in fig. 4. In this case, the position retaining layer 1007 may substantially fill the recess.

Next, source/drain regions may be formed in the buffer layer 1031 and the other semiconductor material layer 1005. This may be formed by doping the buffer layer 1031 and the further layer 1005 of semiconductor material. This may be done, for example, as follows.

Specifically, as shown in fig. 5, a dopant source layer 1009 may be formed on the structure shown in fig. 4. For example, the dopant source layer 1009 may include an oxide such as silicon oxide, in which a dopant is contained. For n-type devices, an n-type dopant may be included; for a p-type device, a p-type dopant may be included. Here, the dopant source layer 1009 may be a thin film and thus may be deposited substantially conformally on the surface of the structure shown in fig. 4 by, for example, Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD).

Next, as shown in fig. 6, dopants contained in the dopant source layer 1009 may be brought into the active region by, for example, annealing, thereby forming a doped region therein, as shown by the hatched portion in the figure. More specifically, one of the source/drain regions may be formed in the buffer layer 1031, and the other source/drain region may be formed in the other semiconductor material layer 1005. Thereafter, the dopant source layer 1009 may be removed.

In addition, although the position retaining layer 1007 is present, the dopant may enter the first semiconductor material layer 1003 via the buffer layer 1031 and the other semiconductor material layer 1005, so as to form a certain doping profile at the upper and lower ends of the first semiconductor material layer 1003, as shown by the oval dotted circles in the figure. The doping distribution can reduce the resistance between the source region and the drain region when the device is conducted, so that the performance of the device is improved.

In the above example, the source/drain regions are formed by driving (drive in) dopants from the dopant source layer into the active region, but the present disclosure is not limited thereto. For example, the source/drain regions can be formed by ion implantation, plasma doping (e.g., conformal doping along the surface of the structure in fig. 4), and the like.

In this example, the dopant source layer 1009 includes a portion that extends along a horizontal surface of the buffer layer 1031 such that doped regions formed in the buffer layer 1031 extend beyond the periphery of the active region thereabove. Thus, the source/drain regions formed in the buffer layer 1031 can be easily electrically connected through the doped regions in a subsequent process.

In this example, the buffer layer 1031 and the further semiconductor material layer 1005 are doped with the same conductivity type, resulting in source/drain regions of the same conductivity type. The present disclosure is not so limited. For example, the buffer layer 1031 and the further semiconductor material layer 1005 may be doped with different conductivity types, and thus different conductivity types of source/drain regions are obtained (in which case a tunnel FET may be formed). For example, after forming a dopant source layer of one conductivity type as shown in fig. 5, a masking layer (e.g., oxynitride) may be formed and may be etched back such that its top surface remains at a position between the top surface and the bottom surface of the first semiconductor material layer 1003, thereby masking the dopant source layer formed on the sidewalls of the buffer layer 1031 and exposing the dopant source layer formed on the sidewalls of the other semiconductor material layer 1005. Subsequently, the dopant source layer on the sidewalls of the exposed other semiconductor material layer 1005 may be removed, and a dopant source layer of another conductivity type may be formed on the sidewalls of the other semiconductor material layer 1005.

An isolation layer may be formed around the active region to achieve electrical isolation. For example, as shown in fig. 7, an oxide can be deposited over the structure shown in fig. 6 and etched back to form the isolation layer 1013. The deposited oxide may be subjected to a planarization process such as Chemical Mechanical Polishing (CMP) or sputtering prior to etch back. Here, a top surface of the isolation layer 1013 may be close to an interface between the first semiconductor material layer 1003 and the buffer layer 1031.

The position retaining layer 1007 may be left in place when forming the spacers to avoid that the material of the spacers enters the above-mentioned recess, in which the second semiconductor material layer, the gate stack, is to be accommodated. Thereafter, the position holding layer 1007 may be removed to release the space in the recess. For example, the position retaining layer 1007 (nitride) may be selectively etched with respect to the spacer layer 1013 (oxide) and the buffer layer 1031, the further semiconductor material layer 1005 and the first semiconductor material layer 1003 (SiGe).

A second layer of semiconductor material may then be formed in the recess.

To this end, as shown in fig. 7, a second layer 1059 of semiconductor material may be formed on the resulting structure, for example by deposition or epitaxial growth. The second layer of semiconductor material may have a substantially uniform thickness, for example, about 2-10nm, and may be facetted (finished). Advantageously, the thickness (the dimension in the horizontal direction in the figure) of the second layer 1059 of semiconductor material may be smaller than the smallest dimension of the first layer 1003 of semiconductor material (which at least partly determines the short channel effect and the mobility of the carriers of the device; in the case of nanowires the smallest dimension is the diameter of the nanowires; in the case of nanoplates the smallest dimension is the thickness of the nanoplates). In the case of epitaxial growth, there can be a clear crystal interface between the semiconductor layers. The second layer of semiconductor material 1059 may be unintentionally doped or lightly doped.

The material of second semiconductor material layer 1059 may be selected such that it is favorable for device performance. For example, second semiconductor material layer 1059 may include a semiconductor material useful for enhancing device on-state current and/or reducing device off-state current. For example, for an n-type device, the electron concentration in the second semiconductor material layer 1059 in the device on state may be greater than the electron concentration in the first semiconductor material layer 1003; and for a p-type device, the hole concentration in second semiconductor material layer 1059 in the device on state may be greater than the hole concentration in first semiconductor material layer 1003. In addition, the second semiconductor material layer 1059 may form a heterojunction, or even a quantum well structure, with at least one of the buffer layer 1031, the first semiconductor material layer 1003, and the other semiconductor material layer 1005. Here, due to the stress release of the first semiconductor material layer 1003, the stress in the thin second semiconductor material layer 1059 can be released. Thus, the material selection range of the second semiconductor material layer 1059 can be very wide without causing large crystal defects such as dislocations to occur therein. For example, the second semiconductor material layer 1059 may include one of a group IV semiconductor material or a group III-V compound semiconductor such as SiGe, Ge, SiGeSn, GeSn, GaAs, InGaAs, InP, AlGaAs, InAlAs, InAs, InGa, InAlGa, GaN, InSb, InGaSb, or a combination thereof.

In this example (buffer layer 1031 comprising Si_1-xGe_xThe first semiconductor material layer 1003 includes Si_1-yGe_yThe other semiconductor material layer 1005 comprises Si_1-zGe_z) The second semiconductor material layer 1059 may include Si_1-cGe_c(c is between 0 and 1). An interfacial layer, such as a layer with an abrupt Ge concentration, may be present between the first semiconductor material layer 1003 and the second semiconductor material layer 1059. For an n-type device, c may be less than y, so that tensile stress may be created in second semiconductor material layer 1059 to enhance electron mobility; while for a p-type device, c may be greater than y, so that compressive stress may be generated in the second semiconductor material layer 1059 to enhance hole mobility. c can be close to 1 without causing large dislocation density, which is beneficial for device performance enhancement.

This Si compound_1-cGe_cThe thin layer has the following advantages. First, the thin layer may reduce overlap capacitance between subsequently formed gates and source/drains. Second, it can form quantum wells, confining carriers in the thin layer, to enhance carrier mobility and thus improve device performance. In addition, dopedThe first semiconductor material layer 1003 may also help confine carriers in the thin layer.

Advantageously, the Ge concentration in the second semiconductor material layer 1059 may not be uniform, e.g., smaller at the beginning of growth to reduce defects, and then gradually increased. Then, the Ge concentration in the second semiconductor material layer 1059 may gradually increase from the surface on the side close to the first semiconductor material layer toward the surface on the side far from the first semiconductor material layer. In another embodiment, the Ge concentration in the second semiconductor material layer 1059 may gradually decrease from the surface near the first semiconductor material layer side toward the surface far from the first semiconductor material layer side.

For the portion of the second semiconductor material layer 1059 on the top surface of the other semiconductor material layer 1005, considering that a contact will be subsequently formed over the top surface of the other semiconductor material layer 1005, it may be removed because the low doped or undoped second semiconductor material layer 1059 may increase the contact resistance or may form a high resistance schottky junction with the metal in the contact. For example, as shown in fig. 8, a portion of the second semiconductor material layer 1059 on the top surface of the other semiconductor material layer 1005 may be removed by RIE of the second semiconductor material layer 1059 in the vertical direction. Of course, the portion of the second semiconductor material layer 1059 on the top surface of the isolation layer 1013 may also be removed. In this case, the second semiconductor material layer 1059 may remain on at least a portion of the sidewalls of the other semiconductor material layer 1005.

Alternatively, the portion of the second semiconductor material layer 1059 outside the recess may be completely removed. For example, another position holding layer may be formed in the recess described above. The position-retaining layer may also comprise nitride and may be formed as described above in connection with fig. 4. Next, a portion of the second semiconductor material layer 1059 located inside the recess may be masked with the position-keeping layer, and a portion of the second semiconductor material layer 1059 located outside the recess may be removed. For example, the second layer of semiconductor material 1059 may be RIE performed in a direction substantially perpendicular to the substrate surface, which may be performed to completely remove portions of the second layer of semiconductor material 1059 on the sidewalls of the other layer of semiconductor material 1005. Subsequently, the position retaining layer may be removed.

In this way, the active region of the semiconductor device (the etched buffer layer 1031, in particular, the upper portion thereof, the first semiconductor material layer 1003, the second semiconductor material layer 1059, and the further semiconductor material layer 1005) is defined. In this example, the active region is substantially cylindrical. In this case, a nanowire device may be formed. In the active region, an upper portion of the buffer layer 1031, the first semiconductor material layer 1003 and the other semiconductor material layer 1005 may be substantially aligned in a vertical direction, e.g., center aligned, and an upper portion of the buffer layer 1031 and an outer periphery of the other semiconductor material layer 1005 may be substantially aligned.

Of course, the shape of the active region is not limited thereto, but may be formed in other shapes according to the design layout. For example, in a top view, the active region may be oval, square, rectangular, etc. In the case of a rectangle and orientation, a nanosheet device can be formed.

A gate stack may then be formed in the recess. Specifically, a gate dielectric layer 1015 and a gate conductor layer 1017 may be sequentially deposited on the resulting structure, and the deposited gate conductor layer 1017 (and optionally the gate dielectric layer 1015) may be etched back such that the top surface of the portion thereof outside the recess is not higher than and preferably lower than the top surface of the first semiconductor material layer 1003. For example, the gate dielectric layer 1015 may include a high-K gate dielectric such as HfO₂(ii) a The gate conductor layer 1017 may comprise a metal gate conductor. In addition, a work function adjusting layer may be further formed between the gate dielectric layer 1015 and the gate conductor layer 1017. An interfacial layer, such as an oxide, may also be formed prior to forming the gate dielectric layer 1015.

In this way, the gate stack may be embedded in the recess so as to overlap the entire length of the second layer 1059 of semiconductor material extending between the source/drain regions (corresponding to the gate length).

In addition, depending on the position of the top surface of the isolation layer 1013, there may be some overlap of the gate stack with the source/drain regions formed in the buffer layer 1031 (e.g., in case the top surface of the isolation layer 1013 is lower than the interface between the first semiconductor material layer 1003 and the buffer layer 1031), which may increase the parasitic capacitance between the gate and the source/drain. Therefore, it is preferable that the top surface of the spacer layer 1013 is not lower than the interface between the first semiconductor material layer 1003 and the buffer layer 1031.

Next, the shape of the gate stack may be adjusted to facilitate subsequent interconnect fabrication. For example, as shown in fig. 9, a photoresist 1019 may be formed on the structure shown in fig. 8. The photoresist 1019 is patterned, for example, by photolithography, to cover a portion of the gate stack exposed out of the recess (in this example, the left half portion of the figure may extend in a stripe shape), and to expose the other portion of the gate stack exposed out of the recess.

Then, as shown in fig. 10(a) and 10(b) (fig. 10(a) is a sectional view, and fig. 10(b) is a plan view), selective etching such as RIE may be performed on the gate conductor layer 1017 using the photoresist 1019 as a mask. Thus, the portion of the gate conductor layer 1017 blocked by the photoresist 1019 is retained except for the portion remaining within the recess. Electrical connection to the gate stack may then be made through this portion.

According to another embodiment, the gate dielectric layer 1015 and the isolation layer 1013 may be further selectively etched, such as RIE, to facilitate the subsequent liner formation. After that, the photoresist 1019 may be removed.

Then, as shown in fig. 11, a liner layer 1201 may be formed on the structure shown in fig. 10(a) and 10(b), for example, by deposition. The liner 1201 may comprise nitride and may act as an etch stop layer and a device protection layer. Thereafter, as shown in fig. 12, an interlayer dielectric layer 1021 may be formed on the structure shown in fig. 11. For example, an oxide may be deposited and planarized such as CMP to form the interlayer dielectric layer 1021. In the interlayer dielectric layer 1021, a contact 1023-1 to a source/drain region formed in the buffer layer 1031, a contact 1023-2 to a source/drain region formed in the other semiconductor material layer 1005, and a contact 1023-3 to the gate conductor layer 1017 may be formed. These contacts may be formed by etching holes in the inter-level dielectric layer 1021 and the liner 1201, and filling them with a conductive material such as a metal (e.g., tungsten). A diffusion barrier layer such as TiN may be formed prior to depositing the metal.

It can be seen that the contacts may have different depths. Thus, different etching depths are required when etching the respective contact holes. The presence of liner 1201 helps to enhance the etch control of the contact hole. For example, the etching of the inter-layer dielectric layer 1021 may stop at the underlayer 1201.

Since the gate conductor layer 1017 extends beyond the outer periphery of the active region, its contact 1023-3 can be easily formed. In addition, since the doped region in the buffer layer 1031 extends beyond the active region and no gate conductor layer is present over at least a portion thereof, the contact 1023-1 thereof can be easily formed.

As shown in fig. 12, the semiconductor device according to this embodiment includes a buffer layer 1031, a first semiconductor material layer 1003, and another semiconductor material layer 1005 stacked in a vertical direction, with a second semiconductor material layer 1059 formed around the periphery of the first semiconductor material layer 1003. Source/drain regions are formed in the buffer layer 1031 and the other semiconductor material layer 1005. A gate stack (1015/1017) is formed around the periphery of the second layer of semiconductor material 1059.

In the above embodiments, the active region is formed based on the SiGe material. However, the present disclosure is not limited thereto. The active region may also be formed based on Si material. For example, the buffer layer 1031, the first semiconductor material layer 1003 and the other semiconductor material layer 1005 described above with reference to fig. 1 may be replaced with the first source/drain layer 1031, the first semiconductor material layer 1003 and the second source/drain layer 1005, respectively, of Si material. Each layer may be 10-100nm thick.

In the above embodiments, the desired etch selectivity may be achieved by the Ge concentration in the SiGe material. In this embodiment, the desired etch selectivity may be achieved by the doping concentration. For example, the first source/drain layer 1031 and the second source/drain layer 1005 may be heavily doped, particularly p-doped with B, at a doping concentration of, for example, about 1E19-1E21cm^-3And the first layer of semiconductor material 1003 may be unintentionally doped or lightly doped to adjust the device threshold. The doping can be performed by in-situ doping, ion implantation, gas phase drive-in diffusion, etc.

In addition, in order to suppress diffusion of dopants in the first source/drain layer 1031 and the second source/drain layer 1005, a low temperature epitaxial process, for example, less than 800 ℃.

This may then be done as described above with reference to figures 2 to 12.

In the process of selectively etching the first semiconductor material layer 1003 described above in connection with fig. 3, a TMAH solution may be used.

To enhance the etch selectivity, an outer portion of the first layer of semiconductor material 1003 may be doped n-type. For example, As shown in fig. 13, a dopant source layer 1009' containing n-type dopants such As or P may be formed on the structure shown in fig. 2(a) and 2(b) by deposition such As CVD or ALD. For example, the dopant source layer 1009' may include an oxide having a thickness of about 2-5nm and a dopant concentration of about 0.01% -5%. Such a dopant source layer 1009' is not limited to a separately formed layer, and may be implemented by a doped region formed on sidewalls of the first source/drain layer 1031, the first semiconductor material layer 1003, and the second source/drain layer 1005 by, for example, plasma doping, angled implantation, or the like. Then, as shown in fig. 14, dopants contained in the dopant source layer 1009' (or doped regions on sidewalls of the first source/drain layer 1031, the first semiconductor material layer 1003, and the second source/drain layer 1005) may be driven in to the inner side by, for example, annealing. By controlling the process parameters such as annealing temperature and annealing time, the concentration of the portion of the first semiconductor material layer 1003 required to be removed can be greater than 1E19cm^-3But less than the p-type doping concentration in the first and second source/drain layers 1031, 1005 (to maintain p-type conductivity in the first and second source/drain layers 1031, 1005). In addition, due to the annealing, the B dopant in the first source/drain layer 1031 and the second source/drain layer 1005 may diffuse into the first semiconductor material layer 1003, so that the effective thickness of the first semiconductor material layer 1003 subsequently functioning as a channel region is reduced. Accordingly, in this case, the initial thickness of the first semiconductor material layer 1003 may be large, for example, about 40-150 nm. Subsequently, outer portions of the first semiconductor material layer 1003 relatively heavily n-doped may be removed by selective etching with TMAH solution with respect to the p-doped first and second source/ drain layers 1031, 1005 and the central portion of the first semiconductor material layer 1003 that is not intentionally doped or lightly doped.

In addition, since the first source/drain layer 1031 and the second source/drain layer 1005 are already doped, the process of forming the dopant source layer 1009 described above with reference to fig. 5 may be omitted. However, an annealing process may still be performed to drive a portion of the dopants into the ends of the first layer of semiconductor material 1003, as described above in connection with fig. 6.

The above description with respect to the second layer of semiconductor material 1059 still applies. For example, the second semiconductor material layer 1059 may include SiGe.

In addition, the gate stack formed, such as the gate conductor layer and/or the workfunction adjusting layer therein, may have stress or strain. For example, for a p-type device, the gate stack may have tensile stress to create compressive stress in the channel; while for an n-type device, the gate stack may have compressive stress to create tensile stress in the channel. This structure may generate much greater stress than a planar MOSFET or FinFET since the top of the second source/drain layer 1005 may be moved.

The semiconductor device according to the embodiment of the present disclosure can be applied to various electronic devices. For example, by integrating a plurality of such semiconductor devices and other devices (e.g., other forms of transistors, etc.), an Integrated Circuit (IC) can be formed, and an electronic apparatus can be constructed therefrom. Accordingly, the present disclosure also provides an electronic device including the above semiconductor device. The electronic device may also include components such as a display screen that cooperates with the integrated circuit and a wireless transceiver that cooperates with the integrated circuit. Such electronic devices are for example smart phones, computers, tablets (PCs), artificial intelligence, wearable devices, mobile power supplies etc.

According to an embodiment of the present disclosure, there is also provided a method of manufacturing a system on chip (SoC). The method may include the above-described method of manufacturing a semiconductor device. In particular, a variety of devices may be integrated on a chip, at least some of which are fabricated according to the methods of the present disclosure.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:

a substrate;

a first source/drain layer, a channel layer and a second source/drain layer sequentially stacked on a substrate; and

a gate stack formed around an outer periphery of the channel layer,

wherein the channel layer includes a first semiconductor material layer and a second semiconductor material layer formed around an outer periphery of the first semiconductor material layer,

characterized in that the source/drain regions formed in the first source/drain layer and the second source/drain layer, respectively, at least partially overlap the first semiconductor material layer, the second semiconductor material layer in the stacking direction of the first source/drain layer, the channel layer, and the second source/drain layer, so that the channel region can be formed in both the first semiconductor material layer and the second semiconductor material layer.

2. The semiconductor device of claim 1, wherein the first layer of semiconductor material, the second layer of semiconductor material, and the gate dielectric layer in the gate stack form a quantum well structure.

3. The semiconductor device of claim 1, wherein the second layer of semiconductor material forms a heterojunction with respect to at least one of the first source/drain layer, the second source/drain layer, and the first layer of semiconductor material.

4. The semiconductor device of claim 1, wherein an interfacial layer is present between the first layer of semiconductor material and the second layer of semiconductor material.

5. The semiconductor device according to claim 1, wherein the first semiconductor material layer is aligned with the first and second source/drain layers in the stacking direction with an outer periphery thereof recessed with respect to an outer periphery of the first and second source/drain layers, and the second semiconductor material layer is at least partially formed in the recess formed in the outer periphery of the first semiconductor material layer with respect to the outer periphery of the first and second source/drain layers.

6. The semiconductor device of claim 5, wherein the second layer of semiconductor material is further formed on sidewalls of the second source/drain layer.

7. A semiconductor device as claimed in any one of claims 1 to 6, characterized in that the thickness of the second layer of semiconductor material is 2-10 nm.

8. The semiconductor device according to any one of claims 1 to 6, wherein the thickness of the second layer of semiconductor material is less than the smallest dimension of the first layer of semiconductor material.

9. The semiconductor device according to claim 8,

the first layer of semiconductor material is a nanowire and the smallest dimension is a diameter of the nanowire; or

The first layer of semiconductor material is a nanoplate and the smallest dimension is the thickness of the nanoplate.

10. The semiconductor device of claim 1, wherein the source/drain regions comprise doped regions in the first source/drain layer and the second source/drain layer, the doped regions extending into the first layer of semiconductor material.

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