CN210348479U - Electronic equipment - Google Patents
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- CN210348479U CN210348479U CN201921420452.XU CN201921420452U CN210348479U CN 210348479 U CN210348479 U CN 210348479U CN 201921420452 U CN201921420452 U CN 201921420452U CN 210348479 U CN210348479 U CN 210348479U
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Abstract
The utility model provides an electronic equipment, include: the control chip, the interface female seat and the switch chip, a first pin of the switch chip is connected with an input/input pin of the interface female seat, a second pin of the switch chip is connected with an input/output pin of the control chip, the connection between the first pin and the second pin is in a connected state or a disconnected state, the control pin of the control chip is connected with an enable pin of the switch chip, a detection pin of the control chip is connected with a detection pin of the interface female seat, when the interface female seat is connected with an interface male head with a self-defined function and an interface male head with a standard function, the detection pin can transmit different types of electric signals to the detection pin, the control chip is triggered to output different types of control signals to the enable pin through the control pin, so that the connection between the first pin and the second pin is enabled through the enable pin, and the control chip is prevented from receiving error signals, and further reduce the damage of the electronic equipment of the female seat of interface place.
Description
Technical Field
The utility model belongs to the technical field of equipment control, especially, relate to an electronic equipment.
Background
With the development of hardware technology, the hardware interface has the characteristic of supporting double-sided insertion, for example, the hardware interface of the standard Type-C, the Type-C interface includes a Type-C female socket and a Type-C male head, the pin distribution of the Type-C female socket is shown in fig. 1 and fig. 2, and as can be seen from the pin distribution shown in fig. 1 and fig. 2, the pins of the Type-C female socket and the Type-C male head have symmetry, so that the Type-C interface can support double-sided insertion.
Based on the characteristic that the hardware interface supports double-sided insertion, when the electronic device uses the hardware interface, the pin function of the hardware interface can be customized, so as to transmit signals through the customized hardware interface, but if the interface male head with the standard function (namely, the pin function of the male head is specified by the standard protocol) is inserted into the interface female seat with the customized function (namely, the pin function of the female seat is customized), the interface female seat with the customized function can be damaged. Therefore, if the pin function of the hardware interface in the electronic equipment is self-defined, the electronic equipment needs to be subjected to fool-proof and misplug-proof design:
one design is: the pin function of the hardware interface is explained in the product specification of the electronic equipment, but the user usually does not research the product specification, so that the design is equivalent to no fool-proof and misplug-proof protection for the electronic equipment; the other design is as follows: the structure of female seat of interface and the public head of interface improves, for example, the outer edge of the female seat of interface is provided with the arch, be provided with the recess that matches with this arch on the public head of interface, the public head of interface that has this recess like this just can match completely with the female seat of interface (the pin of public head and the pin laminating of female seat), but if the size of the public head of interface that has standard function is longer, should have the public head of interface of standard function still can match completely with the female seat of interface, lead to the female seat of interface place electronic equipment to receive the error signal, thereby damage the female seat of interface place electronic equipment.
SUMMERY OF THE UTILITY MODEL
In view of this, an object of the present invention is to provide an electronic device for reducing the damage of the electronic device where the female seat of the interface is located. The technical scheme is as follows:
the utility model provides an electronic equipment, electronic equipment includes the female seat of control chip and interface, electronic equipment still includes: a switch chip;
a first pin of the switch chip is connected with an input/output pin of the interface female socket, a second pin of the switch chip is connected with an input/output pin of the control chip, and the connection between the first pin and the second pin is in a connected state or a disconnected state;
and the control pin of the control chip is connected with the enabling pin of the switch chip, and the detection pin of the control chip is connected with the detection pin of the interface female socket.
Preferably, a first part of the input/output pins of the control chip are directly connected with pins with standard functions in the input/output pins of the interface female socket;
the first pin of the switch chip is connected with a pin with a user-defined function in the input/output pin of the interface female socket, the second pin of the switch chip is connected with a second part of pins in the input/output pin of the control chip, and the second part of pins are communicated with the pin with the user-defined function through the switch chip.
Preferably, the switch chip comprises at least one first pin and at least one second pin, and the at least one first pin and the at least one second pin are connected through a component with a closing/opening function;
one pin of the at least one first pin is connected with at least one pin with a customized function, and one pin of the at least one second pin is connected with at least one pin of the second part of pins.
Preferably, the switch chip comprises at least one first switch component;
the first switch component is provided with two pins, one of the two pins is the first pin, the other pin is the second pin, and one of the two pins is multiplexed as the enabling pin.
Preferably, the switch chip comprises at least one second switch component;
the second switch component is provided with three pins, one of the three pins is the first pin, the other pin is the second pin, and the other pin is the enable pin.
Preferably, the detection pin of the interface female socket is a ground pin of the interface female socket, and the detection pin of the control chip is a signal input pin of the control chip.
Preferably, the detection pin of the interface female socket is a ground pin of the interface female socket, and the detection pin of the control chip is a signal input pin of the control chip.
It can be known from the above technical solutions that, a switch chip is added in an electronic device comprising a control chip and an interface female socket, a first pin of the switch chip is connected with an input/output pin of the interface female socket, a second pin of the switch chip is connected with an input/output pin of the control chip, the connection between the first pin and the second pin is in a connected state or a disconnected state, the control pin of the control chip is connected with an enable pin of the switch chip, and a detection pin of the control chip is connected with a detection pin of the interface female socket, so that when the interface female socket is connected with an interface male head with a self-defined function and an interface male head with a standard function, the detection pin of the interface female socket can transmit different types of electrical signals to the detection pin of the control chip, and the control chip is triggered to output different types of control signals to the enable pin through the control pin, in order to enable the connection between first pin and the second pin through enabling the pin, if the female seat of interface is the female seat of an interface that has self-defined function, make the connection between first pin and the second pin be in the connected state when it connects the interface that has self-defined function public head, so that female seat of interface and control chip can be connected, and the female seat of interface that has self-defined function makes the connection between first pin and the second pin be in the disconnected state when connecting the interface that has standard function public head, in order to forbid the female seat of interface and control chip to connect, thereby prevent that control chip from receiving the error signal, and then reduce the damage of the female seat of interface place electronic equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of pin arrangement of an interface socket of a conventional Type-C interface;
FIG. 2 is a schematic diagram of pin distribution of a male connector of a conventional Type-C interface;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a multiplexing ground pin according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a multiplexing power pin according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another electronic device according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a switch chip according to an embodiment of the present invention;
fig. 8 is a schematic diagram of another switch chip provided in an embodiment of the present invention;
fig. 9 is a schematic diagram of another switch chip provided in an embodiment of the present invention;
fig. 10 is a schematic diagram of another switch chip provided in an embodiment of the present invention;
fig. 11 is a schematic diagram of another switch chip according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Please refer to fig. 3, which illustrates a structure of an electronic device according to the present invention, which may include: a control chip 10, an interface female socket 20 and a switch chip 30.
Wherein, the first pin of the switch chip 30 is connected with the input/output pin of the interface female socket 20, the second pin of the switch chip 30 is connected with the input/output pin of the control chip 10, so as to realize the signal transmission between the interface female socket 20 and the control chip 10 by means of the switch chip 30, the signal transmission path between the interface female socket 20 and the control chip 10 needs to be determined according to whether the signal is from the interface female socket 20 to the control chip 10 or from the control chip 10 to the interface female socket 20, which is as follows:
if the signal is from the interface female socket 20 to the control chip 10, the signal transmission path is: a signal is transmitted from an input/output pin of the interface female socket 20 to a first pin of the switch chip 30, and then the signal is output from a second pin of the switch chip 30 to an input/output pin of the control chip 10 through the switch chip 30, and the control chip 10 obtains the signal from its own input/output pin; if the signal is from the control chip 10 to the interface female socket 20, the signal transmission path is: signals are transmitted from the input/output pin of the control chip 10 to the second pin of the switch chip 30, and then the signals are output from the first pin of the switch chip 30 to the input/output pin of the interface female socket 20 through the switch chip 30, and are transmitted to the outside of the electronic device through the input/output pin of the interface female socket 20.
However, whether a signal can pass through the switch chip 30 needs to see the connection state between the first pin and the second pin, in this embodiment, the connection between the first pin and the second pin is in a connection state or a disconnection state, that is, the connection state between the first pin and the second pin is either in a connection state or in a disconnection state, in which a signal can pass through the switch chip 30, and in which a signal cannot pass through the switch chip 30.
Whether the connection state between the first pin and the second pin is the connection state or the disconnection state depends on the type of the interface male plug inserted into the interface female socket 20 and the type of the interface female socket 20, if the interface female socket 20 and the inserted interface male plug are matched, the connection state between the first pin and the second pin is the connection state, otherwise, the connection state between the first pin and the second pin is the disconnection state. For example, if the female socket 20 is a female socket with a user-defined function, and if the male plug is a male plug with a standard function, it indicates that the female socket 20 is not matched with the male plug, and at this time, the connection state between the first pin and the second pin is a disconnection state; if the inserted interface male head is a self-defined interface male head, it indicates that the interface female socket 20 is matched with the inserted interface male head, and at this time, the connection state between the first pin and the second pin is a communication state.
In this embodiment, in coordination with the change of the connection state between the first pin and the second pin, the following connections are required among the control chip 10, the interface female socket 20, and the switch chip 30:
the control pin of the control chip 10 is connected with the enable pin of the switch chip 30, and the detection pin of the control chip 10 is connected with the detection pin of the interface female socket 20, and the using processes of the four pins include: under the condition that the interface female socket 20 is inserted into the interface male connector, the detection pin of the interface female socket 20 detects an electric signal, the electric signal is transmitted to the detection pin of the control chip 10 through the detection pin of the interface female socket 20, and the control chip 10 outputs a control signal to the enabling pin of the switch chip through the control pin under the action of the electric signal so as to enable the connection between the first pin and the second pin of the switch chip 30 through the control signal.
If the interface female socket 20 is inserted into the interface male head matched with the interface female socket, the detection pin of the interface female socket 20 detects an electrical signal for indicating that the control chip 10 can be connected with the interface female socket 20, the control chip 10 outputs a control signal for indicating that the connection state between the first pin and the second pin is a communication state to the enable pin under the action of the electrical signal, and at the moment, the path between the first pin and the second pin is communicated, and the interface female socket 20 is connected with the control chip 10; if the female socket 20 is plugged into the male socket, the detecting pin of the female socket 20 detects an electrical signal for indicating that the control chip 10 is prohibited from being connected to the female socket 20, and the control chip 10 outputs a control signal for indicating that the connection state between the first pin and the second pin is a disconnected state to the enabling pin under the action of the electrical signal, at this time, the path between the first pin and the second pin is disconnected, and the female socket 20 cannot be connected to the control chip 10.
And the detection pin of the control chip 10 may be one of input/output pins of the control chip 10, which may not be connected with the second pin of the switch chip 30; the probing pins of the female socket 20 can be multiplexed, taking the female socket of the Type-C interface shown in fig. 1 as an example, the pins a4/B9/a9/B4 in the female socket of the interface are power pins, and are marked as VBUSThe pins A1/A12/B12/B1 are ground pins, and are marked as GND, and in this embodiment, the power pins or the ground pins can be multiplexed as probe pins. Assuming that the multiplexing ground pin a1 is used as a probe pin, the probe pin is customized as a power pin by connecting a resistor and a power supply (VCC) at the probe pin, and a pin connected to a1 in an interface male plug matched with the interface female socket is also customized as a power pin, so that if the interface female socket 20 is inserted into the interface male plug matched with the interface female socket (i.e. the pins connected to a1 are both customized as the interface male plug of the power pin), the a1 is still the power pin at this time, the a1 outputs a high level such as VCC, and at this time, the control chip 10 outputs a first control signal to an enable pin of the switch chip 30 to control the first pin and the second pin of the switch chip 30 to be in a connected state, so that the input/output pin connected to the first pin in the control chip 10 is connected to the input/output pin of the interface female socket 20; if the interface female socket 20 is inserted into the interface male socket not matched with the interface female socket, that is, the interface male socket whose pin connected with a1 is a standard pin (grounding pin), a1 is grounded, a1 outputs a low level, at this time, the control chip 10 outputs a second control signal to the enable pin of the switch chip 30 to control the first pin and the second pin of the switch chip 30 to be in an off state, and the control chip 10 is disabled from connecting with the second pinOne pin-connected input/output pin is connected to an input/output pin of the interface female socket 20.
Similarly, assuming that the power pin is multiplexed as the probe pin, a circuit manner may be added to the probe pin to enable the probe pin to output different electrical signals when the female socket 20 is inserted into the male socket that is matched or unmatched with the female socket, as shown in fig. 5. The power pin a4 is customized as a ground pin by the circuit shown in fig. 5, and the pin connected with a4 in the same interface male plug matched with the interface female socket is also customized as a ground pin, so that if the interface female socket is inserted into the interface male plug matched with the interface female socket, a4 is still the ground pin at this time, a4 outputs low level, and if the interface female socket is inserted into the interface male plug unmatched with the interface female socket, a4 is connected with the power VCC, and a4 outputs high level at this time. In order to avoid the damage of the multiplexing power supply pin to the detection pin of the control chip 10, a voltage conversion circuit is connected between the detection pin of the control chip 10 and the detection pin of the interface socket 20, so that the high and low levels input to the detection pin of the control chip 10 meet the requirements of the detection pin, and the voltage conversion can be implemented by any current voltage conversion circuit, which is not described again in this embodiment.
The points to be explained here are: the detection pin prohibits the multiplexing of the custom pin in the hardware interface, still takes the female socket of the interface of the Type-C interface as an example, a6 to A8 and B5 to B8 in the female socket of the interface of the Type-C interface are custom pins, the level of the output electrical signal of the custom pins is not definite, the multiplexing of the custom pin is a detection pin, and the condition that the Type of the male header of the interface inserted into the female socket 20 is misjudged exists, so the multiplexing of the custom pin is prohibited as the detection pin in the embodiment.
It can be known from the above technical solutions that, in an electronic device including a control chip 10 and an interface female socket 20, a switch chip 30 is added, a first pin of the switch chip 30 is connected with an input/output pin of the interface female socket 20, a second pin of the switch chip 30 is connected with an input/output pin of the control chip 10, the connection between the first pin and the second pin is in a connected state or a disconnected state, a control pin of the control chip 10 is connected with an enable pin of the switch chip 30, and a detection pin of the control chip 10 is connected with a detection pin of the interface female socket 20, so that when an interface male with a custom function and an interface male with a standard function are connected by the interface female socket 20, the detection pin of the interface female socket 20 can transmit different types of electrical signals to the detection pin of the control chip 10, triggering the control chip 10 to output different types of control signals to the enable pin through the control pin, if the female socket 20 of the interface is a female socket of the interface with the user-defined function, the female socket 20 of the interface with the user-defined function enables the connection between the first pin and the second pin to be in a connected state when the female socket is connected with the male head of the interface with the user-defined function, so that the female socket 20 of the interface can be connected with the control chip 10, and the female socket 20 of the interface with the user-defined function enables the connection between the first pin and the second pin to be in a disconnected state when the female socket 20 of the interface with the standard function is connected with the male head of the interface with the standard function, so that the female socket 20 of the interface is forbidden to be connected with the control chip 10, thereby preventing the control chip 10 from receiving an error signal and further reducing the damage of the electronic equipment where the female socket.
The points to be explained here are: the input/output pins in the female socket 20 include pins with standard functions and pins with customized functions, and normally, the functions of the pins with standard functions are prohibited from being modified by the definition of a communication protocol, and the functions of the pins corresponding to the pins with standard functions on the corresponding male socket of the interface are also standard functions, so that the pins with standard functions are connected together no matter what type of male socket 20 is connected, and the electronic equipment cannot be damaged because the connected male socket of the interface is not matched with the female socket 20 of the interface. However, as for the pins with the customized functions, the customized functions are different according to different product requirements of the electronic device, and therefore, if the pins with the customized functions of the interface female socket 20 are connected to the interface male head that is not matched with the customized pins, the electronic device may be damaged, so that in this embodiment, the switch chip 30 is required to control the connection between the pins with the customized functions in the interface female socket 20 and the input/output pins of the control chip 10, and the pins with the standard functions in the interface female socket 20 can be directly connected to the input/output pins of the control chip 10, as shown in fig. 6.
A first part of pins in the input/output pins of the control chip 10 are directly connected with pins (referred to as standard pins for short) with standard functions in the input/output pins of the interface female socket 20, a first part of pins of the switch chip 30 are connected with pins (referred to as custom pins for short) with custom functions in the input/output pins of the interface female socket 20, a second part of pins of the switch chip 30 are connected with a second part of pins in the input/output pins of the control chip 10, and the second part of pins are communicated with the pins with the custom functions through the switch chip 30, so that the structure of the switch chip 30 can be simplified, and the cost is reduced.
In the present embodiment, an optional structure of the switch chip 30 and the connection based on the optional structure are shown in fig. 7, and the switch chip 30 includes: at least one first pin (marked G1) and at least one second pin (marked G2), the first pin and the second pin are connected through a component (marked G3) with a closing/opening function.
In fig. 7, the number of the first pins and the second pins is the same as the number of the pins with the customized function in the interface socket 20, in fig. 7, the relationship between the first pins and the second pins is a one-to-one relationship, and a switch (a form of a component with a closing/opening function) is connected between the first pins and the second pins with the one-to-one relationship, and each first pin is connected with a pin with the customized function, and each second pin is connected with one input/output pin in the second part of pins, that is, the first pins and the pins with the customized function in the interface socket 20 are in a one-to-one relationship, and the second pins and the respective input/output pins in the second part of the control chip 10 are also in a one-to-one relationship.
The illustration of fig. 7 described above is merely an example, and the number of the first pins and the second pins and the relationship between the first pins and the second pins and other pins may not be limited in practical applications. For example, if the number of the first pins and the second pins is smaller than that of the pins with the customized function in the interface socket 20, one first pin is connected to a plurality of pins with the customized function in the interface socket 20, and one second pin is connected to a plurality of input/output pins in the control chip 10, so as to ensure that each pin with the customized function can be connected to the first pin and each input/output pin in the second part of pins can be connected to the second pin; if the number of the first pins and the second pins is larger than that of the customized pins in the female socket 20, the connection can be performed in at least one of the one-to-many manner and the one-to-one manner. However, in this embodiment, the connection is preferably performed in a one-to-one relationship, and if the number of the first pins and the second pins is not enough to match the number of the pins of the interface socket and the control chip when the connection is performed in the one-to-one relationship, at least two switch chips may be used to satisfy the one-to-one relationship, so that the connection is preferably performed in the one-to-one relationship because when the connection is performed in the one-to-many relationship, other logic control components are required to control the communication between the pins to prevent communication errors, and the connection is performed in the one-to-one relationship, so that the communication between the pins is fixed and accurate, and the structure can be simplified with respect to one-to-many.
Fig. 7 adopts a switch as a component having an on/off function in the switch chip 30, but the form of the component is not limited in this embodiment, and other components capable of implementing the on/off function besides the switch may also be, for example, a diode, a not gate, and the like, as shown in fig. 8, and the connection between the first pin and the second pin is controlled by the component having the on/off function of the not gate.
In the present embodiment, another optional structure of the switch chip 30 is: the switch chip 30 includes at least one first switch assembly having two pins, wherein one of the two pins is a first pin and the other is a second pin, and one of the two pins is multiplexed as an enable pin, and the first switch assembly may be in the form of: at least one of a diode, a relay, and a switch.
As shown in fig. 9, for example, the switch chip 30 includes a plurality of diodes as first switch components, one of the plurality of first switch components is multiplexed into a first pin and an enable pin, and the other is a second pin, the pin with the custom function in the interface female socket 20 and a second part of the pins of the control chip 10 are connected through the two first switch components, the diodes are turned on by a first control signal received by the enable pin when the interface female socket is inserted into the interface male header matched therewith, and the diodes are turned off by a second control signal received by the enable pin when the interface female socket is inserted into the interface male header unmatched therewith.
The switch chip 30 may include the same number of first switch assemblies as the number of pins with customized functions in the female socket 20, so that each first switch assembly is connected to one customized pin. In practical applications, as in the description of fig. 7, the number of the first switch assemblies included in the switch chip 30 is not limited, for example, the number of the first switch assemblies included in the switch chip 30 may be greater than the number of the pins with the customized function in the interface socket 20, and a plurality of first switch assemblies may be connected to one customized function pin, so that in the case that any one of the plurality of first switch assemblies connected to the same pin is damaged, the pin connection control may be implemented by the other first switch assemblies.
In the present embodiment, yet another optional structure of the switch chip 30 is: the switch chip 30 includes at least one second switch assembly having three pins, wherein one of the three pins is a first pin, another one is a second pin, and the other one is an enable pin. The second switching component may be in the form of a transistor or the like.
As shown in fig. 10 and fig. 11 as an example, the switch chip 30 includes a first number of second switch components, the first number is the number of pins with the custom function in the interface socket 20, the second switch components are all NPN transistors, three pins of the NPN transistors are respectively configured as a first pin, a second pin and an enable pin, and the first pin of each second switch component is connected to one pin with the custom function, the second pin is connected to one pin of the second part of pins, and the enable pins of all the NPN transistors are commonly connected to the control pin of the control chip 10. The NPN type triode is conducted through a first control signal received by the enabling pin under the condition that the interface female seat is inserted into the interface male head matched with the interface female seat, and the NPN type triode is cut off through a second control signal received by the enabling pin under the condition that the interface female seat is inserted into the interface male head unmatched with the interface female seat.
Fig. 11 is different from fig. 10 in that the second switch component is a PMOS transistor, and the configuration of three pins of the PMOS transistor can be seen in fig. 11, and the PMOS transistor is controlled to be turned on and off by a control signal received by an enable pin.
In this embodiment, the switch chip 30 may also combine at least two optional structures shown in fig. 7 to fig. 11, and the switch chip 30 may also be used to control the connection between the interface socket 20 and the control chip 10, which will not be described in detail in this embodiment.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
Finally, it should also be noted that, in this document, relational terms such as first and second, and the like may be used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a device includes not only those elements but also elements inherent to the device. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of another like element in the device.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, a plurality of modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (7)
1. An electronic device, the electronic device includes control chip and female seat of interface, its characterized in that, electronic device still includes: a switch chip;
a first pin of the switch chip is connected with an input/output pin of the interface female socket, a second pin of the switch chip is connected with an input/output pin of the control chip, and the connection between the first pin and the second pin is in a connected state or a disconnected state;
and the control pin of the control chip is connected with the enabling pin of the switch chip, and the detection pin of the control chip is connected with the detection pin of the interface female socket.
2. The electronic device of claim 1, wherein a first portion of the input/output pins of the control chip are directly connected to pins with standard functions in the input/output pins of the interface socket;
the first pin of the switch chip is connected with a pin with a user-defined function in the input/output pin of the interface female socket, the second pin of the switch chip is connected with a second part of pins in the input/output pin of the control chip, and the second part of pins are communicated with the pin with the user-defined function through the switch chip.
3. The electronic device of claim 2, wherein the switch chip comprises at least one first pin and at least one second pin, and the at least one first pin and the at least one second pin are connected through a component having a close/open function;
one pin of the at least one first pin is connected with at least one pin with a customized function, and one pin of the at least one second pin is connected with at least one pin of the second part of pins.
4. The electronic device of claim 2, wherein the switch chip comprises at least one first switch component;
the first switch component is provided with two pins, one of the two pins is the first pin, the other pin is the second pin, and one of the two pins is multiplexed as the enabling pin.
5. The electronic device of claim 2, wherein the switch chip comprises at least one second switch component;
the second switch component is provided with three pins, one of the three pins is the first pin, the other pin is the second pin, and the other pin is the enable pin.
6. The electronic device according to claim 1, wherein the probing pin of the interface socket is a ground pin of the interface socket, and the detecting pin of the control chip is a signal input pin of the control chip.
7. The electronic device according to claim 1, wherein the probing pin of the interface socket is a ground pin of the interface socket, and the detecting pin of the control chip is a signal input pin of the control chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201921420452.XU CN210348479U (en) | 2019-08-29 | 2019-08-29 | Electronic equipment |
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| CN201921420452.XU CN210348479U (en) | 2019-08-29 | 2019-08-29 | Electronic equipment |
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| CN210348479U true CN210348479U (en) | 2020-04-17 |
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