CN210073828U

CN210073828U - Semiconductor structure

Info

Publication number: CN210073828U
Application number: CN201920593938.7U
Authority: CN
Inventors: 不公告发明人
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2019-04-26
Filing date: 2019-04-26
Publication date: 2020-02-14
Anticipated expiration: 2029-04-26

Abstract

The embodiment of the utility model provides a relate to wafer packaging technology field, disclose a semiconductor structure. The utility model discloses in, the semiconductor structure includes: the testing device comprises a substrate comprising an electric connection layer and a conducting pad arranged on the substrate, wherein the conducting pad is electrically connected with the electric connection layer, a groove is arranged in the conducting pad, and the groove divides the conducting pad into a first region for testing and a second region for electric connection. The utility model provides a semiconductor structure can improve the yield and the stability of chip.

Description

Semiconductor structure

Technical Field

The embodiment of the utility model provides a relate to wafer packaging technology field, in particular to semiconductor structure.

Background

In order to increase the yield and stability of chips, it is usually necessary to perform a testing (bonding) step on the conductive pads of the chips by using a probe (testprobe) after the chips (die) are manufactured, and the conductive pads are contacted many times. First, the probe for testing applies a proper force on the conductive pad of the chip at a high speed to ensure that the probe touches the conductive pad, and then an electrical test is performed. To ensure that the probe actually touches the conductive pad, the probe makes multiple contacts with the conductive pad, eventually causing destructive damage to the surface of the conductive pad. For example, in the case of memory products, in order to improve the yield of the products, a plurality of spare cells (spare cells) are usually reserved for repair. When the memory is initially completed, the bad or bad circuit units are detected by probe test, laser repair (laser repair) is performed on the bad or bad circuit units to connect the bad or bad circuit units to the reserved spare circuit units, and then probe electrical test is performed. Therefore, the memory is subjected to more than one electrical test of the probe, which causes the conductive pad to be scratched and generate dust.

The inventor finds that at least the following problems exist in the prior art: after the probe electrical test is performed, a bump (bumping) process or a wire bonding (wire bonding) process is performed to form a bump or a wire on the surface of the conductive pad for connecting to other devices on the substrate. The conductive pad scratch and the dust problem caused in the probe electrical test stage can cause the quality of the bump or the wire formed in the subsequent wire bonding or bump process to be poor, and the yield and the stability of the chip are not high.

SUMMERY OF THE UTILITY MODEL

An object of the present invention is to provide a semiconductor structure, which can improve the yield and stability of the chip.

In order to solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the testing device comprises a substrate comprising an electric connection layer and a conducting pad arranged on the substrate, wherein the conducting pad is electrically connected with the electric connection layer, a groove is arranged in the conducting pad, and the groove divides the conducting pad into a first region for testing and a second region for electric connection.

Compared with the prior art, the utility model, the embodiment is owing to be provided with the slot in the conducting pad, the slot will the conducting pad is separated for the first region that is used for the test and is used for the second region of electricity to, in the practical application in-process, the probe can only be surveyed in first region, thereby the probe will fall into the ditch groove bottom in case try to get into the second region, stop motion, promptly, the slot can block the probe gets into the second region, and then guaranteed that the second region that is used for the electricity to connect can not destroyed by the probe, the lug that forms when having avoided follow-up wire bonding or lug technology or the not good problem of wire quality, has improved the yield and the stability of chip.

In addition, a through hole exposing the electric connection layer is arranged in the substrate, the conductive pad comprises a conductive layer positioned on the surface of the substrate and a connecting part positioned in the through hole, and the conductive layer is electrically connected with the electric connection layer through the connecting part.

In addition, the groove is at least partially overlapped with an orthographic projection of the via hole on the substrate. With the arrangement, the groove is directly formed in the process of forming the conductive pad, so that the manufacturing process is simplified, and the cost advantage is achieved.

In addition, the groove penetrates the conductive layer and the connection portion.

In addition, the grooves and the orthographic projections of the through holes on the substrate are arranged at intervals.

In addition, the depth of the groove is smaller than the thickness of the conductive layer in the direction perpendicular to the surface of the substrate.

In addition, in a direction perpendicular to the direction in which the first region points to the second region, the length of the trench is smaller than the length of the conductive layer. With such an arrangement, the electrical connection between the first region and the second region can be ensured, so that both the first region and the second region can be ensured to be electrically connected with the electrical connection layer as long as at least either one of the first region and the second region is electrically connected with the electrical connection layer, thereby ensuring the reliability of the conductive pad.

In addition, the substrate is also provided with a plurality of dielectric layers, and the dielectric layers are arranged among the conductive layers to electrically insulate the conductive layers.

In addition, the projection of the groove on the substrate is rectangular or elliptical.

In addition, the width of the groove in a direction pointing to the second region along the first region ranges from 1 micrometer to 20 micrometers.

In addition, the length of the groove is in a range of 50 micrometers to 80 micrometers in a direction perpendicular to a direction in which the first region points to the second region.

In addition, the depth of the groove ranges from 100 nanometers to 6 micrometers in the direction perpendicular to the surface of the substrate.

Drawings

One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.

Fig. 1 is a top view of a semiconductor structure according to a first embodiment of the present invention;

fig. 2 is a cross-sectional view of a semiconductor structure provided in a first embodiment of the present invention;

fig. 3 is a cross-sectional view of a semiconductor structure provided in a second embodiment of the present invention;

fig. 4 is a cross-sectional view of a semiconductor structure in accordance with yet another embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the following will explain in detail each embodiment of the present invention with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.

The first embodiment of the present invention relates to a semiconductor structure 100, as shown in fig. 1 and 2, including: the testing device includes a substrate 11 having an electrical connection layer 10, a conductive pad 12 disposed on the substrate 11, the conductive pad 12 electrically connected to the electrical connection layer 10, a trench 13 disposed in the conductive pad 12, the trench 13 dividing the conductive pad 12 into a first region 20 for testing and a second region 30 for electrical connection.

Compared with the prior art, the embodiment of the present invention has the advantages that since the groove 13 with the exposed top is disposed in the conductive pad 12 (the conductive pad 12 is exposed at the top), the groove 13 divides the conductive pad 12 into the first region 20 for testing and the second region 30 for electrical connection, so that, in the practical application process, the probe can only detect in the first region 20, and once the probe tries to enter the second region 30, the probe will fall into the bottom of the groove 13 and stop moving, i.e., the groove 13 can block the probe from entering the second region 30, thereby ensuring that the second region 30 for electrical connection is not damaged by the probe, avoiding the conductive pad 12 scratching and dust problem (formed on the surface of the conductive pad 12 in the form of a concave hole (dent) or causing a burr (burring) on the surface of the conductive pad 12) caused by the electrical testing stage of the probe, improving the quality of the bump or the wire formed in the subsequent wire bonding or bump process, the yield and the stability of the chip are improved.

Specifically, the substrate 11 is provided with a via hole 14 exposing the electrical connection layer 10, the conductive pad 12 includes a conductive layer 121 located on the surface of the substrate 11 and a connection portion 122 located in the via hole 14, the conductive layer 121 is electrically connected to the electrical connection layer 10 through the connection portion 122, the conductive pad 12 may be made of a conductive material of an integrated circuit such as copper, aluminum, tungsten, or the like, or an alloy, and the conductive pad 12 may have a square, rectangular, or various optically formable shapes.

It should be noted that the areas of the first region 20 and the second region 30 can accommodate the testing and wire bonding requirements, and the actual size should be considered for the circuit design.

In practical applications, the projection of the trench 13 on the substrate 11 is rectangular or oval, and the width of the trench 13 in the direction pointing to the second region 30 along the first region 20 is in a range from 1 micron to 20 microns, for example, the width of the trench 13 may be 1 micron, 5 microns, 10 microns, 20 microns, etc., since the width of the probe in the prior art is about 8um, while in the present embodiment, the width of the trench 13 is in a range from 1 micron to 20 microns, and the width thereof is greater than the width of the probe, so that the probe can be better blocked from entering the second region 30 for electrical connection.

Further, the length of the trench 13 in a direction perpendicular to the first region 20 and directed to the second region 30 ranges from 50 micrometers to 80 micrometers, for example, the length of the trench 13 may be 50 micrometers, 60 micrometers, 80 micrometers, etc., and by setting the length of the trench 13 to be as long as the length of the conductive pad 12, the probe can be prevented from sliding to the second region 30 from the edge (where the length of the trench is not long enough to completely separate the first region 20 and the second region 30).

In addition, the depth of the trench 13 in the direction perpendicular to the surface of the substrate 11 ranges from 100 nm to 6 μm, for example, the depth of the trench 13 may be 100 nm, 500 nm, 1 μm, 3 μm, 6 μm, etc., and the actual depth should be considered for the circuit design.

In this embodiment, the trench 13 and the through hole 14 at least partially overlap each other in an orthographic projection on the substrate 11, which is advantageous to directly form the trench 13 during the process of forming the conductive pad 12, thereby simplifying the process and providing a cost advantage, and optionally, after the trench 13 is directly formed during the process of forming the conductive pad 12, the size (mainly, the depth) of the trench 13 may be changed by etching (in this way, the conductive pad 12 is made of aluminum, tungsten, and the like, but not copper), mechanical scribing, and the like. Of course, the trench 13 may be formed directly after the formation of the flat conductive pad 12 by etching (in this case, the material of the conductive pad 12 is aluminum, tungsten, or the like), mechanical scribing, or the like.

Further, the trench 13 may penetrate through the conductive layer 121 and the connection portion 122, that is, the conductive pad 12 is separated at the bottom of the trench 13, and the connection portion 122 is divided into two parts and respectively connected to the electrical connection layer 10, so as to ensure that the first region 20 and the second region 30 are electrically connected to the electrical connection layer 10, and at this time, the depth of the trench 13 is larger, so as to better block the probe from entering the second region 30 for electrical connection.

Alternatively, the length of the trench 13 is smaller than the length of the conductive layer 121 in a direction perpendicular to the direction from the first region 20 to the second region 30, so that the electrical connection between the first region 20 and the second region 30 can be ensured, so that as long as at least one of the first region 20 and the second region 30 is electrically connected to the electrical connection layer 10, both the first region 20 and the second region 30 can be electrically connected to the electrical connection layer 10, thereby ensuring the reliability of the conductive pad 12. Of course, the length of the trench 13 may also be equal to the length of the conductive layer 121 in a direction perpendicular to the first region 20 pointing to the second region 30.

It should be noted that a plurality of dielectric layers 15 are further disposed on the substrate 11, the number of the conductive layers 121 is multiple, the dielectric layers 15 are disposed between the conductive layers 121 to electrically insulate the conductive layers 121, and the material of the dielectric layers 15 may be polyimide.

The second embodiment of the present invention relates to a semiconductor structure 200, as shown in fig. 3, the second embodiment is substantially the same as the first embodiment, and the main differences are: in the first embodiment, the trench 13 penetrates the conductive layer 121 and the connection portion 122. In the second embodiment of the present invention, the depth of the trench 13 is smaller than the thickness of the conductive layer 121 in the direction perpendicular to the surface of the substrate 11. In addition, those skilled in the art can understand that the present embodiment can achieve similar technical effects as the first embodiment, and details are not described here.

In other words, in the present embodiment, the trench 13 does not penetrate the conductive layer 121, so that the first region 20 and the second region 30 are ensured to be connected, and at this time, the trench 13 may at least partially coincide with an orthographic projection of the via hole 14 on the substrate 11.

It is understood that the trench 13 may be spaced apart from the orthographic projection of the via 14 on the substrate 11, as shown in fig. 4.

Of course, the trench 13 may penetrate the conductive layer 121 without penetrating the connection portion 122. In this case, the trench 13 may at least partially coincide with an orthographic projection of the via hole 14 on the substrate 11, and the first region 20 and the second region 30 are connected at the connection portion 122 to be electrically connected to the electrical connection layer 10 via the connection portion 122, and at this time, a length of the trench 13 may be less than or equal to a length of the conductive layer 121 in a direction perpendicular to the first region 20 toward the second region 30.

It is understood that when the trench 13 penetrates the conductive layer 121 without penetrating the connection portion 122, the trench 13 and the orthogonal projection of the via hole 14 on the substrate 11 may be disposed at an interval, and at this time, in a direction perpendicular to the direction from the first region 20 to the second region 30, the length of the trench 13 is smaller than the length of the conductive layer 121, so as to ensure the electrical connection between the first region 20 and the second region 30, so that as long as at least any one of the first region 20 and the second region 30 is electrically connected to the electrical connection layer 10, both of the first region 20 and the second region 30 are electrically connected to the electrical connection layer 10, thereby ensuring the reliability of the conductive pad 12.

It will be understood by those skilled in the art that the foregoing embodiments are specific examples of the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in its practical application.

Claims

1. A semiconductor structure, comprising: the testing device comprises a substrate comprising an electric connection layer and a conducting pad arranged on the substrate, wherein the conducting pad is electrically connected with the electric connection layer, a groove is arranged in the conducting pad, and the groove divides the conducting pad into a first region for testing and a second region for electric connection.

2. The semiconductor structure of claim 1, wherein a via hole exposing the electrical connection layer is disposed in the substrate, the conductive pad comprises a conductive layer on a surface of the substrate and a connection portion disposed in the via hole, and the conductive layer is electrically connected to the electrical connection layer through the connection portion.

3. The semiconductor structure of claim 2, wherein the trench at least partially coincides with an orthographic projection of the via on the substrate.

4. The semiconductor structure of claim 3, wherein the trench penetrates the conductive layer and the connection portion.

5. The semiconductor structure of claim 2, wherein the trench and the via are spaced from each other by an orthogonal projection of the trench and the via on the substrate.

6. The semiconductor structure of claim 2, wherein a depth of the trench is less than a thickness of the conductive layer in a direction perpendicular to the substrate surface.

7. The semiconductor structure of claim 2, wherein a length of the trench is less than a length of the conductive layer in a direction perpendicular to the first region pointing to the second region.

8. The semiconductor structure of claim 2, wherein a plurality of dielectric layers are disposed on the substrate, and the dielectric layers are disposed between the plurality of conductive layers to electrically insulate the plurality of conductive layers.

9. The semiconductor structure of claim 1, wherein a projection of the trench on the substrate is rectangular or elliptical.

10. The semiconductor structure of claim 1, wherein a width of the trench in a direction along the first region toward the second region ranges from 1 micron to 20 microns.

11. The semiconductor structure of claim 1, wherein a length of the trench ranges from 50 microns to 80 microns in a direction perpendicular to the direction from the first region to the second region.

12. The semiconductor structure of claim 1, wherein the trench has a depth in a range from 100 nm to 6 μm in a direction perpendicular to the substrate surface.