CN209961325U - A wind vibration detection system for overhead transmission lines - Google Patents

Abstract

The utility model discloses a wind vibration detection system for overhead transmission lines, which comprises an optical transceiver module, a signal acquisition module connected with the optical transceiver module, a data processing module connected with the signal acquisition module, and a remote monitoring module connected in communication with the data processing module. platform. The optical transceiver module includes a circulator connected with the sensing fiber on the overhead transmission line, a photodetector and an erbium-doped fiber amplifier connected with the circulator, an amplifier connected with the photodetector, and an erbium-doped fiber amplifier connected with the circulator. A pulse modulator, and a narrow line width laser connected with the pulse modulator; wherein, the amplifier and the narrow line width laser are both connected with a data processing module. Through the above design, the utility model is sensitive to the wind vibration identification and positioning of the line, and can monitor the running state of the transmission line in real time, take emergency measures in advance, and prevent accidents, thereby improving the stability of the power system, reducing maintenance costs, and improving economy. benefit.

Description

A wind vibration detection system for overhead transmission lines

technical field

The utility model relates to the technical field of power transmission, in particular to a wind vibration detection system for overhead transmission lines.

Background technique

)的原理对现有风振检测方式进行改进。With the continuous development of the power system and the continuous construction of the smart grid, the online monitoring technology of the power system has been widely valued. Transmission lines in complex field environments are vulnerable to various natural disasters and cause safety accidents. The wind-induced vibration of transmission lines is a long-term and cumulative process, and the degree of damage cannot be measured by direct observation, which seriously threatens the normal and safe operation of the line. Implement computer management. However, most of the test data comes from manual inspections, video surveillance, and various electrical sensor measurements. These traditional detection methods have defects such as qualitative observation but not quantitative detection, difficulty in power supply maintenance, and susceptibility to electromagnetic interference. The utility model is based on a phase sensitive optical time domain reflectometry (Phase Sensitive Optical Time Domain Reflectometry,

) to improve the existing wind vibration detection methods.

是一种同时以光纤本身作为感知元件和传输介质的分布式光纤传感技术，当光波在光纤中传输时，会产生如图1所示的后向瑞利散射、布里渊散射和拉曼散射，其中后向瑞利散射光具有和入射光相同的频率，其光强与入射光波长的四次方成反比，光纤上任意一点都是传感单元，当风吹动光缆发生振动时，光纤会发生应力形变，光纤各处折射率发生改变，最终导致该处光的相位发生改变。返回的发生干涉的瑞利后向散射光光强因为相位的改变而发生改变，通过与未发生振动检测到的信号进行分析比较，最终找出光强变化的时间对应振动的确切位置，以此获知沿线各处的应变情况。

It is a distributed optical fiber sensing technology that uses the optical fiber itself as the sensing element and the transmission medium at the same time. When the light wave is transmitted in the optical fiber, it will produce back Rayleigh scattering, Brillouin scattering and Raman as shown in Figure 1. Scattering, in which the backward Rayleigh scattered light has the same frequency as the incident light, and its light intensity is inversely proportional to the fourth power of the wavelength of the incident light. Any point on the fiber is a sensing unit. When the wind blows the fiber optic cable to vibrate, The fiber undergoes stress and deformation, and the refractive index changes everywhere in the fiber, which eventually causes the phase of the light to change. The intensity of the returned interfering Rayleigh backscattered light changes due to the change of phase. By analyzing and comparing with the signal detected without vibration, the exact position of the vibration corresponding to the time of the change in light intensity is finally found out. Know the strain situation along the line.

Utility model content

The purpose of the utility model is to provide an overhead transmission line wind vibration detection system, which mainly solves the problems of unstable wind vibration detection of existing power transmission lines, low stability of the power transmission system due to electromagnetic interference, and difficulty in power supply maintenance.

For achieving the above object, the technical scheme adopted by the present utility model is as follows:

A wind vibration detection system for overhead transmission lines, comprising an optical transceiver module, a signal acquisition module connected with the optical transceiver module, a data processing module connected with the signal acquisition module, and a remote monitoring platform connected in communication with the data processing module; The transceiver module includes a circulator connected to the sensing fiber on the overhead transmission line, a photodetector and an erbium-doped fiber amplifier connected to the circulator, an amplifier connected to the photodetector, and a pulse modulator connected to the erbium-doped fiber amplifier. , and a narrow linewidth laser connected with the pulse modulator; wherein, the amplifier and the narrow linewidth laser are both connected with the signal acquisition module.

Further, the signal acquisition module includes an A/D analog-to-digital conversion module and an FPGA logic control module that are connected to each other; wherein, the FPGA logic control module is connected with the narrow linewidth laser and the data processing module, and the A/D analog-to-digital conversion module is connected. connected to the amplifier.

Further, described data processing module comprises the ARM processor that the model that is connected with FPGA logic control module is S3C2440, and the SDRAM random memory module, FLASH memory module, LCD control module, network communication module, communication interface that all link to each other with ARM processor. module and power module, and a GUI graphic user interface connected with the LCD control module, the SDRAM random storage module and the FLASH storage module; wherein, the network communication module is connected to the remote monitoring platform in communication.

Specifically, the A/D analog-to-digital conversion module includes an analog-to-digital conversion chip U1 whose model is AD9233, and a peripheral control circuit connected to the analog-to-digital conversion chip U1; the peripheral control circuit includes a The capacitor C1 between the VIN+ pin and the VIN- pin, the resistor R1 connected to the VIN+ pin of the chip U1, the amplifier M1 whose negative power supply terminal is connected to the resistor R1, one end is connected to the negative power supply terminal of the amplifier M1 and the other end is connected to The resistor R3 connected to the reverse input terminal u- of the amplifier M1 is connected in series with the reverse input terminal u- of the amplifier M1 and the other end of the resistors R5 and R7 are connected to the ground. A resistor R2 connected to the VIN- pin of the analog-to-digital conversion chip U1, a resistor R4 connected to the positive power supply terminal of the amplifier M1 at one end and the reverse input terminal u+ of the amplifier M1 at the other end, and the same-direction input of the amplifier M1 at one end The resistor R6, whose end u+ is connected and the other end is grounded, is connected to the capacitor C2 between the REFB pin and the REFT pin of the analog-to-digital conversion chip U1, and is connected to the RBIAS pin and the SENSE pin of the analog-to-digital conversion chip U1. Resistor R8, capacitors C3 and C4 connected in parallel with the VREF pin of the analog-to-digital conversion chip U1 and the SENSE pin of the analog-to-digital conversion chip U1 at the other end, and the SENSE pin and PWDN pin of the analog-to-digital conversion chip U1 , SDIO/DCS pin, OEB pin, and DRGND pin are all connected to the terminal J1; among them, one end of the resistors R5 and R7 is also connected to the VIN- pin of the analog-to-digital conversion chip U1, and the analog-to-digital conversion chip U1 The AVDD pin is connected to 1.8V voltage, the DRVDD pin, SCLK/DFS pin, and CSB pin of the analog-to-digital conversion chip U1 are all connected to 3.3V voltage, and the D0-D11 pins of the analog-to-digital conversion chip U1 are controlled by the bus and FPGA logic The I/O interface of the module is connected, and the remaining interfaces of the analog-to-digital conversion chip U1 are connected with the FPGA logic control module.

Specifically, the network communication module includes a single-chip microcomputer-driven network card chip U2 of model DM9000 connected to the ARM processor through a bus, a control circuit connected to the single-chip computer-driven network card chip U2, and a network interface connected to the control circuit and modeled as HR901130A Chip U3; wherein, the control circuit includes a resistor R10 whose one end is connected to the INT pin of the single-chip drive network card chip U2 and the other end is connected to a 3.3V voltage, one end is connected to the CS pin of the single-chip drive network card chip U2, and the other end is connected to 3.3 Resistor R9 with V voltage, one end is connected to the BGRES pin of the single-chip drive network card chip U2 and the other end is grounded resistor R11, after parallel connection one end is connected to the VDD pin of the single-chip drive network card chip U2 and the other end is grounded capacitors C5, C6, C7 and C8, one end of the series is connected to the LED1 pin of the single-chip drive network card chip U2, and the other end is connected to the 3.3V voltage resistor R12 and the light-emitting diode D1. Connect the resistor R13 with 3.3V voltage and the light-emitting diode D2. After the series connection, one end is connected to the X2 pin of the single-chip drive network card chip U2, and the other end is connected to the ground. C9, one end connected in parallel with the TXVDD and RXVDD pins of the single-chip drive network card chip U2 and the other end connected to the TXVDD and RXVDD pins of the single-chip drive network card chip U2 and grounded capacitors C11, C12, C13, connected in parallel with the crystal oscillator after the series Y1. Capacitor C9 at both ends of capacitor C10, after series connection, one end is connected to the TX- pin of the single-chip drive network card chip U2, and the other end is connected to the TX+ pin of the single-chip drive network card chip U2. Resistors R13, R14, one end is connected to the resistors R13, The capacitor C14 between R14 and the other end is grounded. After the series connection, one end is connected to the RX- pin of the single-chip drive network card chip U2, and the other end is connected to the RX+ pin of the single-chip drive network card chip U2. Resistors R15, R16, one end is connected to the resistor The capacitor C15 between R15 and R16 and the other end is grounded, and the inductor L1 whose one end is connected to the Shield pin and GHS_GND pin of the network interface chip U3 and the other end is grounded, and the Shield pin and the GHS_GND pin of the network interface chip U3. The terminal J2 connected to the pin; among them, the TXVDD pin of the single-chip drive network card chip U2 is connected to the CTR and CTT pins of the network interface chip U3, and the TX-, TX+, RX-, RX+ pins of the single-chip drive network card chip U2 are connected to the network The TD-, TD+, RD-, and RD+ pins of the interface chip U3 are respectively connected correspondingly.

Compared with the prior art, the utility model has the following beneficial effects:

(1) The signal acquisition and data processing module of the present utility model adopts the framework of cooperative work of FPGA (EP4CE55) and ARM (S3C2440), wherein the FPGA is combined with the high-speed ADC and its peripheral circuit as a slave, and mainly completes the control of the optical transceiver module. , the acquisition, preprocessing and data transmission of sensing electrical signals; and ARM as the host, with its peripheral circuits, is mainly responsible for the identification and decoding of the data transmitted by the slave, extracting the wind vibration information, and at the same time completing the slave control, human-computer interaction and Network communication and other functions, using the system to be sensitive to the wind vibration identification and positioning of the line, can monitor the operation status of the transmission line in real time, take emergency measures in advance, and prevent accidents, thereby improving the stability of the power system, reducing maintenance costs, and improving economy. benefit.

(2) The utility model uses the characteristic that the transmission of electromagnetic waves in the circulator can only circulate in one direction by setting the circulator, and the Rayleigh scattered light is separated by the circulator and then converted into an electrical signal by the photodetector. The signal is then sampled by AD for data processing, so as to demodulate the wind vibration state and disturbance location along the fiber, making the location more accurate.

(3) The present utility model directly amplifies the optical signal by setting the erbium-doped fiber amplifier, combined with the use of the sensing fiber, without converting the optical signal into an electrical signal, and directly amplifies the optical signal, and , the operating wavelength range of the erbium-doped fiber amplifier is consistent with the minimum loss window of the fiber, the pump power for exciting the erbium-doped fiber is low, only a few tens of mW, the gain is high, the noise is low, the output power is large, and the connection loss is low, because It is an optical fiber amplifier, so it is easier to connect with optical fiber, and the connection loss can be as low as 0.1dB, which can reduce the overall power consumption of the circuit.

(4) The utility model uses a laser with a very narrow linewidth as the light source, because the narrow linewidth laser will make the light injected into the sensing fiber have strong coherence, so the detected light intensity is all within the range of the light pulse width. The coherent superposition of the intensities of the back-scattered Rayleigh light allows the system to detect even fainter vibrational signals.

(5) The present utility model utilizes pulse modulation, based on the pulse modulation scheme of semiconductor optical amplifier (SOA), the SOA realizes the inversion of the junction particle number by applying forward bias voltage, and the incident signal light generates stimulated radiation, so that the signal light is amplified , in which the extinction ratio of the switching SOA can reach more than 40dB, the operation is simple, and the pulse modulation of high speed and high extinction ratio can be realized.

Description of drawings

FIG. 1 is a schematic diagram of a Rayleigh scattering spectrum in an optical fiber in the background art.

FIG. 2 is the overall principle frame of the present invention.

FIG. 3 is a schematic block diagram of the data processing module of the present invention.

FIG. 4 is a schematic circuit diagram of the A/D analog-to-digital conversion module of the present invention.

FIG. 5 is a schematic circuit diagram of the network communication module of the present invention.

FIG. 6 is a schematic diagram of the layout of the experimental device in the embodiment of the present invention.

FIG. 7 is a time-domain waveform diagram of the test result of the suspension point A in the embodiment.

FIG. 8 is a frequency domain waveform diagram of the test result of the suspension point A in the embodiment.

FIG. 9 is a time-domain waveform diagram of the test result of the suspension point C in the embodiment.

FIG. 10 is a frequency domain waveform diagram of the test result of the suspension point C in the embodiment.

FIG. 11 is a graph showing the result of vibration positioning of the optical fiber in the embodiment.

Detailed ways

The present utility model will be further described below in conjunction with the accompanying drawings and examples, and the modes of the present utility model include but are not limited to the following examples.

Example

As shown in FIGS. 2 and 3 , an overhead transmission line wind vibration detection system disclosed by the present utility model includes an optical transceiver module, a signal acquisition module connected with the optical transceiver module, a data processing module connected with the signal acquisition module, and a data processing module connected with the signal acquisition module. The remote monitoring platform connected by the communication of the data processing module.

The optical transceiver module includes a circulator connected with the sensing fiber on the overhead transmission line, a photodetector and an erbium-doped fiber amplifier connected with the circulator, an amplifier connected with the photodetector, and an erbium-doped fiber amplifier connected with the circulator. A pulse modulator, and a narrow line width laser connected with the pulse modulator; wherein, the amplifier and the narrow line width laser are both connected with a data processing module. The signal acquisition module includes an A/D analog-to-digital conversion module and an FPGA logic control module that are connected to each other; wherein, the FPGA logic control module is connected to the narrow linewidth laser and the data processing module, and the A/D analog-to-digital conversion module is connected to the amplifier. . During measurement, a narrow linewidth (within a few kHz) is used as the light source, which becomes pulsed light after being acted by a pulse modulator. The pulsed light is amplified by an erbium-doped fiber amplifier and then coupled to the sensing fiber by a circulator. During measurement, the backward Rayleigh scattered light is separated by a circulator and converted into an electrical signal by a photodetector. The electrical signal is sampled by AD for data processing, thereby demodulating the wind vibration state and disturbance location along the fiber. .

Described data processing module comprises the ARM processor of model S3C2440 that is connected with FPGA logic control module, SDRAM random storage module, FLASH storage module, LCD control module, network communication module, communication interface module and power supply all connected with ARM processor. module, and a GUI graphical user interface connected with the LCD control module, the SDRAM random storage module, and the FLASH storage module; wherein, the network communication module is in communication connection with the remote monitoring platform.

The utility model also integrates and simplifies the connection circuit between AD9233 and FPGA. As shown in FIG. 4 , the A/D analog-to-digital conversion module includes an analog-to-digital conversion chip U1 with a model of AD9233, and an analog-to-digital conversion chip U1 with an analog-to-digital conversion chip U1. The peripheral control circuit connected to each other; the peripheral control circuit includes a capacitor C1 connected between the VIN+ pin and the VIN- pin of the analog-to-digital conversion chip U1, a resistor R1 connected with the VIN+ pin of the chip U1, and the negative power supply terminal and The amplifier M1 connected to the resistor R1, the resistor R3 whose one end is connected to the negative power supply terminal of the amplifier M1 and the other end is connected to the reverse input terminal u- of the amplifier M1. Resistors R5 and R7 with one end connected to ground, one end connected to the positive power supply terminal of the amplifier M1 and the other end connected to the VIN- pin of the analog-to-digital conversion chip U1, one end connected to the positive power supply terminal of the amplifier M1 and the other end connected to the amplifier The resistor R4 connected to the reverse input terminal u+ of M1, the resistor R6 connected to the non-inverting input terminal u+ of the amplifier M1 at one end and grounded at the other end, connected to the capacitor between the REFB pin and the REFT pin of the analog-to-digital conversion chip U1 C2, connected to the resistor R8 between the RBIAS pin and the SENSE pin of the analog-to-digital conversion chip U1, connected in parallel with the VREF pin of the analog-to-digital conversion chip U1 and the SENSE pin of the analog-to-digital conversion chip U1 at the other end Capacitors C3, C4, and the terminal J1 connected to the SENSE pin, PWDN pin, SDIO/DCS pin, OEB pin, and DRGND pin of the analog-to-digital conversion chip U1; among them, one end of the resistors R5 and R7 is connected It is also connected to the VIN- pin of the analog-to-digital conversion chip U1, the AVDD pin of the analog-to-digital conversion chip U1 is connected to 1.8V voltage, and the DRVDD pin, SCLK/DFS pin, and CSB pin of the analog-to-digital conversion chip U1 are connected to 3.3 V voltage, the D0-D11 pins of the analog-to-digital conversion chip U1 are connected to the I/O interface of the FPGA logic control module through the bus, and the remaining interfaces of the analog-to-digital conversion chip U1 are connected to the FPGA logic control module. Among them, the sampling clock of AD9233 is generated by FPGA through phase-locked loop and obtained by frequency division, and then connected to CLK+ and CLK- pins after being converted by differential circuit. The power interface DRVDD can determine the signal level of the AD9233 parallel output data, adjust it to the VCCIO voltage compatible with the corresponding I/O BANK of the FPGA, and then directly connect the AD9233 and the FPGA I/O pins.

Since the S3C2440 does not have an integrated Ethernet MAC controller, the S3C2440 is connected to the DM9000 through an external bus as shown in Figure 5 to realize the network communication function. The network communication module includes a single-chip microcomputer driven network card chip U2 of model DM9000 connected to the ARM processor through a bus, a control circuit connected to the single-chip computer driven network card chip U2, and a network interface chip U3 of model HR901130A connected to the control circuit; Wherein, the control circuit includes a resistor R10 whose one end is connected to the INT pin of the single-chip microcomputer-driven network card chip U2 and the other end is connected to a 3.3V voltage; Resistor R9, one end is connected to the BGRES pin of the single-chip drive network card chip U2 and the other end is grounded resistor R11, after parallel connection one end is connected to the VDD pin of the single-chip drive network card chip U2 and the other end is grounded capacitors C5, C6, C7, C8 , one end of the series is connected to the LED1 pin of the single-chip drive network card chip U2, and the other end is connected to a 3.3V voltage resistor R12 and a light-emitting diode D1, and the other end of the series is connected to the single-chip drive network card chip U2. Voltage resistor R13, light-emitting diode D2, one end is connected in series with the X2 pin of the single-chip drive network card chip U2, and the other end is grounded. The latter end is connected to the TXVDD and RXVDD pins of the single-chip drive network card chip U2, and the other end is connected to the TXVDD and RXVDD pins of the single-chip drive network card chip U2 and grounded capacitors C11, C12, and C13, which are connected in parallel to the crystal oscillator Y1, capacitor The capacitor C9 at both ends of C10 is connected in series with resistors R13 and R14 whose one end is connected to the TX- pin of the single-chip drive network card chip U2 and the other end is connected to the TX+ pin of the single-chip drive network card chip U2. One end is connected between the resistors R13 and R14 And the other end of the capacitor C14 connected to ground is connected in series with resistors R15 and R16 whose one end is connected to the RX- pin of the single-chip drive network card chip U2 and the other end is connected to the RX+ pin of the single-chip drive network card chip U2, and one end is connected to the resistors R15 and R16 The capacitor C15 between and the other end is grounded, and the inductor L1 whose one end is connected to the Shield pin and GHS_GND pin of the network interface chip U3 and the other end is grounded, and the Shield pin and the GHS_GND pin of the network interface chip U3 are connected. Terminal J2; wherein, the TXVDD pin of the single chip microcomputer drives the network card chip U2 to be connected with the CTR and CTT pins of the network interface chip U3, and the single chip drives the TX-, TX+, RX-, RX+ pins of the network card chip U2 and the network interface chip U3 The TD-, TD+, RD-, and RD+ pins are connected respectively. The DM9000 chip is a highly integrated low-power fast Ethernet chip with a general processor interface, an EEPROM interface, and a 4K-dword SRAM cache data area (3K-byte Tx FIFO; 13K-byte Rx FIFO buffer). When the system is powered on, the S3C2440 configures the DM9000 internal network control register (NCR), interrupt register (ISR), etc. through the bus to complete the initialization of the DM9000, and then the DM9000 enters the waiting state for data transmission and reception.

When S3C2440 wants to send data frame to Ethernet, it first packs the data into UDP or IP data packets, and sends it to the data sending buffer of DM9000 byte by byte through 8/16/32-bit bus, and then fills the data length and other information into the corresponding register of DM9000, and then send the enable command, DM9000 will MAC frame the buffered data and data frame information, and send it out; when DM9000 receives the Ethernet data sent from the external network, it will first detect the legality of the data frame If the frame header flag is wrong or there is a CRC check error, the frame data will be discarded, otherwise the data frame will be cached in the internal RAM, and the processor will be notified through the interrupt flag bit. After the processor receives the interrupt, the DM9000 receives the RAM. data are processed.

系统进行振动测量，以此评判系统的测试结果。实验中为了全面分析线路的应变情况，将电缆中的两根光纤(单根长280m)进行了熔接，因此实验时对相同位置的扰动进行了二次测量。As shown in Figure 6, a detection test carried out by the utility model adopts the OPPC-400 cable with a total length of 560m as the experimental object. Points A and B, the length of the cable between the two suspension points is 60m; after the vibration exciter is connected to the cable (the connection point can be moved), the disturbance of different frequencies (0.5-1.5Hz) is applied to simulate the actual wind vibration, using

The system performs vibration measurements to judge the test results of the system. In the experiment, in order to fully analyze the strain of the line, two optical fibers in the cable (single length 280m) were spliced, so the disturbance at the same position was measured twice during the experiment.

Control the exciter to apply a 1Hz disturbance to the position D 220m away from the starting end, and test the cable signal within 40s. When the cable is subjected to external disturbance, there will be many vibration frequencies compared with when no excitation signal is applied, but the The vibration amplitudes of the suspension points (A and B in the figure) and the disturbance position (D in the figure) are the largest, and the frequency peaks of the two are almost the same and much higher than the rest of the positions, indicating that the strain of the suspension point is much higher than that of other cable positions. , which is caused by the intense strain caused by the stress concentration at the suspension point.

Figure 7 shows the time domain waveform of the test result of the suspension point A, and the maximum amplitude of the time domain signal is about ~2.5×105e. Figure 8 shows the frequency domain waveform of the test result of the suspension point A. From the frequency domain waveform It can be seen that a peak of about ∼4.21 × 104 appears at the frequency of 1 Hz, which is consistent with the perturbation frequency applied by the exciter to the cable.

The time domain signal and frequency domain signal at the selected position C are shown in Figures 9 and 10. Compared with the signal of the suspension point A, the time domain signal amplitude at the position C is basically the same as that of the suspension point A. In the frequency domain, there is a large gap between points A and C, and the frequency domain signal strength of point A shows a gradually decreasing trend, while the position C is basically the same.

Figure 11 is the result of the positioning experiment of the optical fiber vibration measurement. According to the test environment and method shown in Figure 6, the waveform shows a symmetrical distribution, and the frequency peak of the disturbance point is the largest. Through observation, it is known that the position D at 220m from the start end is Perturbation application point.

的分布式测量系统对 OPPC电缆的振动及定位完成实时测量。Through the above experimental analysis, it is concluded that when the fiber is subjected to a certain frequency of disturbance, the fiber strain will change at multiple frequencies, and a strong frequency peak will appear near the suspension point and the disturbance point, which is equal to the excitation frequency. , the excitation frequency value can be easily given, and the strength of the disturbance can be identified by analyzing the size of the peak value. To sum up, it is possible to use the

The distributed measurement system completes real-time measurement of the vibration and positioning of the OPPC cable.

)技术监测线路的振动状态与疲劳程度，利用窄线宽(几kHz以内)作为光源，经脉冲调制器作用后变成脉冲光、该脉冲光通过掺铒光纤放大器放大后由环形器耦合到传感光纤中。测量时，后向瑞利散射光经环形器分离后由光电探测器转化为电信号，该电信号再通过 AD采样后进行数据处理，从而解调出光纤沿线各处的风振状态及扰动定位。整个系统功能强大，工作稳定可靠，同时支持进一步扩展和二次开发。实验测试结果表明系统对线路的风振识别及定位敏感，可实时监测输电线路的运行状态，提前采取应急措施、预防事故发生，从而提高电力系统的稳定性，降低维护费用，提升经济效益。因此，具有很高的使用价值和推广价值。The utility model is based on the "FPGA+ARM" distributed optical fiber sensing monitoring system design. The system uses a phase sensitive optical time domain reflectometry (Phase Sensitive Optical Time Domain Reflectometry,

) technology to monitor the vibration state and fatigue degree of the line, using a narrow line width (within a few kHz) as a light source, after being acted by a pulse modulator, it becomes pulsed light, and the pulsed light is amplified by an erbium-doped fiber amplifier and then coupled to the transmission by the circulator. in the sensing fiber. During measurement, the backward Rayleigh scattered light is separated by a circulator and converted into an electrical signal by a photodetector. The electrical signal is sampled by AD for data processing, thereby demodulating the wind vibration state and disturbance location along the fiber. . The whole system has powerful functions, stable and reliable work, and supports further expansion and secondary development. The experimental test results show that the system is sensitive to the wind vibration identification and positioning of the line, and can monitor the operation status of the transmission line in real time, take emergency measures in advance, and prevent accidents, thereby improving the stability of the power system, reducing maintenance costs, and improving economic benefits. Therefore, it has high use value and promotion value.

The above-mentioned embodiment is only one of the preferred embodiments of the present utility model, and should not be used to limit the protection scope of the present utility model, but any changes or embellishments made in the main body design idea and spirit of the present utility model that have no substantial meaning, If the technical problem solved by it is still consistent with the present invention, it should be included in the protection scope of the present invention.

Claims (5)

1. an overhead transmission line wind vibration detection system, is characterized in that, comprises the optical transceiver module, the signal acquisition module that is connected with the optical transceiver module, the data processing module that is connected to the signal acquisition module, and the remote communication connection with the data processing module. monitoring platform; The optical transceiver module includes a circulator connected with the sensing fiber on the overhead transmission line, a photodetector and an erbium-doped fiber amplifier connected with the circulator, an amplifier connected with the photodetector, and an erbium-doped fiber amplifier connected with the circulator. A pulse modulator, and a narrow line width laser connected with the pulse modulator; wherein, the amplifier and the narrow line width laser are both connected with a data processing module. 2. A kind of overhead transmission line wind vibration detection system according to claim 1, is characterized in that, described signal acquisition module comprises mutually connected A/D analog-to-digital conversion module and FPGA logic control module; Wherein, FPGA logic control The module is connected with the narrow linewidth laser and the data processing module, and the A/D analog-to-digital conversion module is connected with the amplifier. 3. a kind of overhead transmission line wind vibration detection system according to claim 2, is characterized in that, described data processing module comprises the ARM processor of model S3C2440 that is connected with FPGA logic control module, and is all connected with ARM processor The SDRAM random storage module, the FLASH storage module, the LCD control module, the network communication module, the communication interface module and the power supply module, and the GUI graphical user interface connected with the LCD control module, the SDRAM random storage module and the FLASH storage module; The communication module communicates with the remote monitoring platform. 4. a kind of overhead transmission line wind vibration detection system according to claim 3, is characterized in that, described A/D analog-to-digital conversion module comprises the analog-to-digital conversion chip U1 of model AD9233, and the analog-to-digital conversion chip U1 The peripheral control circuit connected to each other; the peripheral control circuit includes a capacitor C1 connected between the VIN+ pin and the VIN- pin of the analog-to-digital conversion chip U1, a resistor R1 connected with the VIN+ pin of the chip U1, and the negative power supply terminal and The amplifier M1 connected to the resistor R1, the resistor R3 whose one end is connected to the negative power supply terminal of the amplifier M1 and the other end is connected to the reverse input terminal u- of the amplifier M1. Resistors R5 and R7 with one end connected to the ground, one end connected to the positive power supply terminal of the amplifier M1 and the other end connected to the VIN- pin of the analog-to-digital conversion chip U1, one end connected to the positive power supply terminal of the amplifier M1 and the other end connected to the amplifier The resistor R4 connected to the reverse input terminal u+ of M1, the resistor R6 connected to the non-inverting input terminal u+ of the amplifier M1 at one end and grounded at the other end, connected to the capacitor between the REFB pin and the REFT pin of the analog-to-digital conversion chip U1 C2, connected to the resistor R8 between the RBIAS pin and the SENSE pin of the analog-to-digital conversion chip U1, connected in parallel with the VREF pin of the analog-to-digital conversion chip U1 and the SENSE pin of the analog-to-digital conversion chip U1 at the other end Capacitors C3, C4, and the terminal J1 connected to the SENSE pin, PWDN pin, SDIO/DCS pin, OEB pin, and DRGND pin of the analog-to-digital conversion chip U1; among them, one end of the resistors R5 and R7 is connected It is also connected to the VIN- pin of the analog-to-digital conversion chip U1, the AVDD pin of the analog-to-digital conversion chip U1 is connected to 1.8V voltage, and the DRVDD pin, SCLK/DFS pin, and CSB pin of the analog-to-digital conversion chip U1 are connected to 3.3 V voltage, the D0-D11 pins of the analog-to-digital conversion chip U1 are connected to the I/O interface of the FPGA logic control module through the bus, and the remaining interfaces of the analog-to-digital conversion chip U1 are connected to the FPGA logic control module. 5. A kind of overhead power transmission line wind vibration detection system according to claim 4, is characterized in that, described network communication module comprises the single-chip drive network card chip U2 of model DM9000 that is connected with ARM processor through bus, and the single-chip drive network card chip U2 The control circuit connected to the network card chip U2, and the network interface chip U3 of the model HR901130A connected to the control circuit; wherein, the control circuit includes one end connected to the INT pin of the single-chip drive network card chip U2 and the other end connected to a 3.3V voltage Resistor R10, one end is connected to the CS pin of the single-chip drive network card chip U2 and the other end is connected to the 3.3V resistor R9, one end is connected to the BGRES pin of the single-chip drive network card chip U2 and the other end is grounded. Resistor R11, after parallel connection, one end is connected to the BGRES pin of the single-chip drive network card chip U2. The capacitors C5, C6, C7, and C8 are connected to the VDD pin of the single-chip drive network card chip U2 and the other end is grounded. After the series is connected, one end is connected to the LED1 pin of the single-chip drive network card chip U2, and the other end is connected to a 3.3V resistor R12, which emits light. Diode D1, one end of the serial connection is connected to the LED1 pin of the single-chip drive network card chip U2, and the other end is connected to the 3.3V voltage resistor R13 and light-emitting diode D2, and the other end is connected to the X2 pin of the single-chip drive network card chip U2 and the other end is grounded The crystal oscillator Y1 and capacitor C10 are connected in parallel with the capacitor C9 at both ends of the crystal oscillator Y1 and capacitor C10 in series. After parallel connection, one end is connected to the TXVDD and RXVDD pins of the single-chip drive network card chip U2, and the other end is connected to the TXVDD and RXVDD pins of the single-chip drive network card chip U2. The capacitors C11, C12, and C13 connected to the RXVDD pin and connected to the ground are connected in parallel with the crystal oscillator Y1 and capacitor C9 at both ends of the capacitor C10 after the series connection. The resistors R13 and R14 connected to the TX+ pin of the network card chip U2, one end is connected to the capacitor C14 between the resistors R13 and R14 and the other end is grounded. The resistors R15 and R16 connected to the RX+ pin of the MCU drive network card chip U2, one end is connected between the resistors R15 and R16 and the other end is connected to the grounded capacitor C15, and one end is connected to the Shield pin and the GHS_GND pin of the network interface chip U3 and The other end of the inductor L1 is grounded, and the terminal J2 connected to the Shield pin and the GHS_GND pin of the network interface chip U3; wherein, the TXVDD pin of the single-chip computer drives the network card chip U2 and the network interface chip U3 The CTR and CTT pins are connected , the TX-, TX+, RX-, RX+ pins of the single-chip microcomputer drive network card chip U2 are respectively connected to the TD-, TD+, RD-, RD+ pins of the network interface chip U3.

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