CN209947842U - MOS-HEMT device containing multiple layers of high-K gate insulating layers - Google Patents
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- CN209947842U CN209947842U CN201921934647.6U CN201921934647U CN209947842U CN 209947842 U CN209947842 U CN 209947842U CN 201921934647 U CN201921934647 U CN 201921934647U CN 209947842 U CN209947842 U CN 209947842U
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- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims abstract description 44
- 230000004888 barrier function Effects 0.000 claims abstract description 44
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000000758 substrate Substances 0.000 claims abstract description 15
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 10
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910001928 zirconium oxide Inorganic materials 0.000 claims abstract description 8
- 239000010408 film Substances 0.000 claims description 32
- 239000010409 thin film Substances 0.000 claims description 14
- 229910002704 AlGaN Inorganic materials 0.000 claims description 8
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 8
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 abstract description 20
- 239000002184 metal Substances 0.000 abstract description 20
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 17
- 238000002360 preparation method Methods 0.000 abstract description 16
- 238000009413 insulation Methods 0.000 abstract description 7
- 239000004411 aluminium Substances 0.000 abstract description 6
- 230000006866 deterioration Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 13
- 238000000151 deposition Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 8
- 238000005566 electron beam evaporation Methods 0.000 description 7
- 238000001755 magnetron sputter deposition Methods 0.000 description 7
- 239000002243 precursor Substances 0.000 description 7
- 230000008569 process Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000007641 inkjet printing Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
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Abstract
The utility model provides a MOS-HEMT device that contains multilayer high K gate insulation layer, which comprises a substrate, the substrate surface is formed with the thick buffer layer of 1 ~ 2 mu m, the buffer layer surface is formed with the thick barrier layer of 25 ~ 30nm, the barrier layer surface is formed with the aluminium metal film, the correspondence of barrier layer surface left and right sides aluminium metal film surface is formed with graphical source electrode and drain electrode, be formed with multilayer high K gate insulation layer between the source drain electrode channel, multilayer high K gate insulation layer includes the aluminium oxide layer that is formed by the direct oxidation of the aluminium metal film between the barrier layer surface left and right sides aluminium metal film and superposes the zirconia layer that is formed at aluminium oxide layer surface, aluminium oxide layer surface and the bottom surface parallel and level of source drain electrode, zirconia layer surface is formed with the gate electrode. The multilayer high-K gate insulating layer is formed by overlapping aluminum oxide and zirconium oxide, so that the performance stability of the device can be improved, the leakage current of the device and the deterioration possibility of key characteristics are reduced, and the preparation method is compatible with the preparation process of the conventional HEMT device.
Description
Technical Field
The utility model relates to the field of semiconductor technology, concretely relates to MOS-HEMT device that contains multilayer high K gate insulation layer.
Background
A compound HEMT (High Electron Mobility Transistor) semiconductor device mainly based on GaAs and GaN has the advantages of ultrahigh frequency, High power and the like, and has a wide application prospect in the fields of wireless 5G communication, radar and the like at present. However, the HEMT device of the conventional schottky gate has a serious leakage problem, and is prone to cause deterioration of key performances of the device, such as breakdown voltage, efficiency, gain and the like. In order to effectively suppress the gate current, at present, a metal-oxide-semiconductor (MOS) structure is introduced into the gate of the conventional compound HEMT structure to form a MOS-HEMT device, which is an effective solution. However, the inventors of the present invention have found through research that the existing manufacturing process for forming a metal-oxide-semiconductor (MOS) device by introducing a MOS structure into a MOS-HEMT device is complicated, and therefore how to effectively manufacture a high-K gate insulating layer becomes the focus of the technology.
SUMMERY OF THE UTILITY MODEL
To effectively restrain compound HEMT device grid current among the prior art, at present there is the MOS-HEMT device of formation through introducing metal-oxide-semiconductor (MOS) structure, but this MOS structure forms MOS-HEMT device and can lead to the comparatively complicated technical problem of device preparation flow, the utility model provides a MOS-HEMT device that contains multilayer high K gate insulation layer.
In order to solve the technical problem, the utility model discloses a following technical scheme:
a MOS-HEMT device comprising a plurality of high-K gate insulating layers includes a substrate, a buffer layer with a thickness of 1-2 μm is formed on the surface of the substrate, a barrier layer with a thickness of 25-30 nm is formed on the surface of the buffer layer, an aluminum metal film is formed on the surface of the barrier layer, a patterned source electrode is formed on the surface of the aluminum metal film on the left side of the surface of the barrier layer, a patterned drain electrode is formed on the surface of the aluminum metal film on the right side of the surface of the barrier layer, a plurality of high-K gate insulating layers are formed between channels of the source electrode and the drain electrode, the multilayer high-K gate insulating layer comprises an aluminum oxide layer generated by directly oxidizing aluminum metal films between the aluminum metal films on the left side and the right side of the surface of the barrier layer and a zirconia layer superposed on the surface of the aluminum oxide layer, the surface of the alumina layer is flush with the bottom surface of the source drain electrode, and a gate electrode is formed on the surface of the zirconia layer.
Further, the substrate is made of Si, SiC or sapphire.
Further, the buffer layer is made of GaAs, and the barrier layer is made of AlGaAs.
Furthermore, the buffer layer is made of GaN, and the barrier layer is made of AlGaN.
Further, the thickness of the aluminum metal thin film is 2 nm.
Further, the thickness of the zirconia layer is 2-5 nm.
The utility model also provides an aforementioned MOS-HEMT device preparation method that contains multilayer high K grid insulating layer, the method includes following step:
s1, sequentially laminating a buffer layer single crystal film with the thickness of 1-2 mu m and a barrier layer single crystal film with the thickness of 25-30 nm on the surface of the substrate by utilizing MOCVD;
s2, obtaining the graphical buffer layer and barrier layer films by photoetching the buffer layer single crystal film and the barrier layer single crystal film;
s3, depositing a layer of aluminum metal film with the thickness of 2nm on the surface of the barrier layer film through magnetron sputtering or electron beam evaporation;
s4, respectively depositing multiple layers of metal on the left and right side surfaces of the aluminum metal film through magnetron sputtering or electron beam evaporation, and obtaining patterned source electrodes and drain electrodes through a photoetching process;
s5, directly depositing a zirconium oxide precursor on the surface of the aluminum metal film between the source electrode channel and the drain electrode channel through an ink-jet printing technology, decomposing and oxidizing the zirconium oxide precursor through heating and deep ultraviolet irradiation methods to form a zirconium oxide insulating layer with the thickness of 2-5 nm, and oxidizing the aluminum metal film at the lower layer by the zirconium oxide precursor under the condition of deep ultraviolet irradiation to finally form a multilayer high-K gate insulating layer formed by overlapping an aluminum oxide layer and a zirconium oxide layer;
and S6, depositing multiple layers of metal on the surface of the zirconia layer through magnetron sputtering or electron beam evaporation, and obtaining the patterned gate electrode through a photoetching process.
Further, in step S1, the buffer layer is made of GaAs, and the barrier layer is made of AlGaAs; or the buffer layer is made of GaN, and the barrier layer is made of AlGaN.
Further, in the step S4, the multilayer metal deposited on the left and right side surfaces of the aluminum metal film is Ni/Au/Ge/Ni/Au, and the thicknesses of the metal layers are 20nm/100nm/26nm/26nm/100nm in sequence.
Further, in step S6, the metal stack structure of the gate electrode is Ni/Au, Ni/Ti/Au, or Ti/Au.
Compared with the prior art, the utility model provides a MOS-HEMT device that contains multilayer high K gate insulation layer and preparation method thereof has following technical advantage:
1. in the MOS-HEMT device structure containing the multilayer high-K gate insulating layers, the multilayer high-K gate insulating layers are formed by overlapping two oxides of alumina layers and zirconia layers, so that a mixed oxide with a higher K value can be formed, and meanwhile, the mixed oxide also has lower interface state defects;
2. the negative influence of the introduction of the gate dielectric on transconductance can be reduced by increasing the K value, and the method has obvious advantages in the aspect of equal-scale reduction of devices;
3. on the premise of being compatible with the existing HEMT device preparation process, the MOS-HEMT device preparation method can successfully realize the preparation of the MOS-HEMT device only by additionally adding the aluminum metal film deposition in the step S3 and the oxidation process in the step S4, and compared with the existing MOS structure forming MOS-HEMT device, the MOS-HEMT device preparation process is simplified;
4. on the premise that the cost is hardly increased, the leakage current of the MOS-HEMT device can be reduced, the performance stability of the device is improved, and the possibility of deterioration of key characteristics of the device is reduced.
Drawings
Fig. 1 is a schematic structural diagram of a MOS-HEMT device including a plurality of layers of high-K gate insulating layers according to the present invention.
Fig. 2a to 2f are schematic cross-sectional structure diagrams of each flow stage in the preparation method of the MOS-HEMT device having the multilayer high-K gate insulating layer according to the present invention.
In the figure, 1, a substrate; 2. a buffer layer; 3. a barrier layer; 4. an aluminum metal thin film; 5. a source electrode; 6. A drain electrode; 7. a plurality of high-K gate insulating layers; 70. a zirconia precursor; 8. and a gate electrode.
Detailed Description
In order to make the technical means, creation features, achievement purposes and functions of the present invention easy to understand and understand, the present invention is further explained by combining with the specific drawings.
In the description of the present invention, it is to be understood that the terms "longitudinal", "radial", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are merely for convenience of description and to simplify the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present invention. In the description of the present invention, "a plurality" means two or more unless otherwise specified.
Referring to fig. 1, the present invention provides a MOS-HEMT device including a substrate 1, wherein a buffer layer 2 with a thickness of 1-2 μm is formed on a surface of the substrate 1, a barrier layer 3 with a thickness of 25-30 nm is formed on a surface of the buffer layer 2, an aluminum metal thin film 4 is formed on a surface of the barrier layer 3, a patterned source electrode 5 is formed on a left side aluminum metal thin film 4 on the surface of the barrier layer 3, a patterned drain electrode 6 is formed on a right side aluminum metal thin film 4 on the surface of the barrier layer 3, a multi-layer high K gate insulating layer 7 is formed between channels of the source electrode 5 and the drain electrode 6, the multi-layer high K gate insulating layer 7 includes an aluminum oxide layer directly oxidized by the aluminum metal thin film 4 between the aluminum metal thin films 4 on left and right sides of the surface of the barrier layer 3 and a zirconium oxide layer superposed on the surface of the aluminum oxide layer, that is, the multilayer high-K gate insulating layer 7 is formed by stacking alumina and zirconia, the surface of the alumina layer is flush with the bottom surfaces of the source electrode 5 and the drain electrode 6, and the surface of the zirconia layer is formed with the gate electrode 8. So far, in the utility model discloses an among the MOS-HEMT device, be located some aluminium metal thin film 4 between source electrode 5 and drain electrode 6 and oxidized into aluminium oxide and with source drain electrode bottom surface parallel and level, another part aluminium metal thin film 4 then is located the below of source electrode 5 and drain electrode 6 respectively.
In a specific embodiment, the substrate 1 is made of Si, SiC, or sapphire.
In a specific embodiment, the buffer layer 2 is made of GaAs, and the barrier layer 3 is made of AlGaAs, that is, when the buffer layer 2 is made of GaAs, the corresponding barrier layer 3 is made of AlGaAs.
In a specific embodiment, the buffer layer 2 is made of GaN, and the barrier layer 3 is made of AlGaN, that is, when the buffer layer 2 is made of GaN, the corresponding barrier layer 3 is made of AlGaN.
In a specific embodiment, the thickness of the aluminum metal thin film 4 is 2nm, so that on one hand, the contact between the source and drain electrodes and AlGaN or AlGaAs is not affected, and on the other hand, a foundation can be laid for the subsequent generation of aluminum oxide as an insulating layer.
In a specific embodiment, the thickness of the zirconia layer is 2-5 nm, so that the thinner zirconia can improve the capacitance and reduce the driving voltage, and meanwhile, the lower aluminum film can be oxidized under DUV irradiation.
The utility model also provides an aforementioned MOS-HEMT device preparation method that contains multilayer high K grid insulating layer, the method includes following step:
s1, as shown in figure 2a, sequentially laminating a buffer layer 2 single crystal film with the thickness of 1-2 microns and a barrier layer 3 single crystal film with the thickness of 25-30 nm on the surface of a substrate 1 by utilizing MOCVD (metal organic chemical vapor deposition), wherein the substrate 1 can be specifically realized by selecting the existing materials such as Si, SiC or sapphire; among them, the MOCVD (Metal Organic Chemical Vapor Deposition) is a prior art well known to those skilled in the art;
s2, obtaining the graphical buffer layer and barrier layer films by photoetching the buffer layer 2 single crystal film and the barrier layer 3 single crystal film; wherein the photolithography process is a prior art in the manufacturing process of semiconductor devices;
s3, as shown in the figure 2b, depositing a layer of aluminum metal film 4 with the thickness of 2nm on the surface of the barrier layer 3 film through magnetron sputtering or electron beam evaporation; magnetron sputtering or electron beam evaporation is one of the prior art of physical vapor deposition;
s4, as shown in FIG. 2c, depositing a plurality of layers of metal on the left and right surfaces of the aluminum metal film 4 by magnetron sputtering or electron beam evaporation, and obtaining a patterned source electrode 5 and a patterned drain electrode 6 by a photoetching process;
s5, as shown in fig. 2d, in order to obtain a multilayer high-K gate insulating layer 7, a zirconia precursor 70 is deposited directly on the surface of the aluminum metal thin film 4 between the source electrode 5 and the drain electrode 6 channel by the existing inkjet printing technique; as shown in fig. 2e, decomposing and oxidizing the zirconia precursor 70 by heating and Deep Ultraviolet (DUV) irradiation to form a 2-5 nm thick zirconia insulating layer, and oxidizing the lower aluminum metal thin film 4 by the zirconia precursor 70 under the deep ultraviolet irradiation to finally form a multilayer high-K gate insulating layer 7 formed by stacking and mixing an aluminum oxide layer and a zirconia layer, i.e. the multilayer high-K gate insulating layer 7 is formed by stacking and mixing aluminum oxide and zirconia;
s6, as shown in fig. 2f, depositing multiple layers of metal on the surface of the zirconia layer by magnetron sputtering or electron beam evaporation, and obtaining the patterned gate electrode 8 by photolithography process.
As a specific example, in step S1, the buffer layer 2 is made of GaAs, and the barrier layer 3 is made of AlGaAs; alternatively, the buffer layer 2 is made of GaN, and the barrier layer 3 is made of AlGaN. Namely: the buffer layer 2 is made of GaAs, the barrier layer 3 is made of AlGaAs, the buffer layer 2 is made of GaN, the barrier layer 3 is made of AlGaN, and the buffer layer 2 and the barrier layer 3 made of two materials can be provided to form the MOS-HEMT device structure.
As a specific example, in step S4, the multilayer metal deposited on the left and right side surfaces of the aluminum metal thin film 4 on the surface of the barrier layer 3 is Ni/Au/Ge/Ni/Au, and the metal layer thickness is 20nm/100nm/26nm/26nm/100nm in this order, so that the source electrode 5 and the drain electrode 6 having a multilayer metal laminated structure can be obtained.
As a specific example, in step S6, the metal laminated structure of the gate electrode 8 is Ni/Au, Ni/Ti/Au, or Ti/Au, so that the gate electrode 8 with the metal laminated structure can be obtained.
Compared with the prior art, the utility model provides a MOS-HEMT device that contains multilayer high K gate insulation layer and preparation method thereof has following technical advantage:
1. in the MOS-HEMT device structure containing the multilayer high-K gate insulating layers, the multilayer high-K gate insulating layers are formed by overlapping two oxides of alumina layers and zirconia layers, so that a mixed oxide with a higher K value can be formed, and meanwhile, the mixed oxide also has lower interface state defects;
2. the negative influence of the introduction of the gate dielectric on transconductance can be reduced by increasing the K value, and the method has obvious advantages in the aspect of equal-scale reduction of devices;
3. on the premise of being compatible with the existing HEMT device preparation process, the MOS-HEMT device preparation method can successfully realize the preparation of the MOS-HEMT device only by additionally adding the aluminum metal film deposition in the step S3 and the oxidation process in the step S4, and compared with the existing MOS structure forming MOS-HEMT device, the MOS-HEMT device preparation process is simplified;
4. on the premise that the cost is hardly increased, the leakage current of the MOS-HEMT device can be reduced, the performance stability of the device is improved, and the possibility of deterioration of key characteristics of the device is reduced.
Finally, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the present invention can be modified or replaced by other means without departing from the spirit and scope of the present invention, which should be construed as limited only by the appended claims.
Claims (6)
1. A MOS-HEMT device containing a plurality of layers of high-K gate insulating layers is characterized by comprising a substrate, wherein a buffer layer with the thickness of 1-2 mu m is formed on the surface of the substrate, a barrier layer with the thickness of 25-30 nm is formed on the surface of the buffer layer, an aluminum metal film is formed on the surface of the barrier layer, a patterned source electrode is formed on the surface of the aluminum film on the left side of the surface of the barrier layer, a patterned drain electrode is formed on the surface of the aluminum film on the right side of the surface of the barrier layer, a plurality of layers of high-K gate insulating layers are formed between channels of the source electrode and the drain electrode, each high-K gate insulating layer comprises an aluminum oxide layer generated by directly oxidizing the aluminum metal film between the aluminum films on the left side and the right side of the surface of the barrier layer and a zirconium oxide layer superposed on the surface of the aluminum oxide layer, and a gate electrode is formed on the surface of the zirconia layer.
2. The MOS-HEMT device with multiple high-K gate insulating layers according to claim 1, wherein the substrate is made of Si, SiC or sapphire.
3. The MOS-HEMT device of claim 1, wherein the buffer layer is made of GaAs and the barrier layer is made of AlGaAs.
4. The MOS-HEMT device with multiple high-K gate insulating layers according to claim 1, wherein the buffer layer is made of GaN and the barrier layer is made of AlGaN.
5. The MOS-HEMT device with multiple high-K gate insulator layers according to claim 1, wherein said aluminum metal thin film has a thickness of 2 nm.
6. The MOS-HEMT device containing multiple high-K gate insulating layers according to claim 1, wherein the thickness of the zirconia layer is 2 to 5 nm.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110707149A (en) * | 2019-11-11 | 2020-01-17 | 中证博芯（重庆）半导体有限公司 | MOS-HEMT device containing multiple layers of high-K gate insulating layers and preparation method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110707149A (en) * | 2019-11-11 | 2020-01-17 | 中证博芯（重庆）半导体有限公司 | MOS-HEMT device containing multiple layers of high-K gate insulating layers and preparation method thereof |
| CN110707149B (en) * | 2019-11-11 | 2024-09-10 | 重庆慧太博科技有限公司 | A MOS-HEMT device containing multiple layers of high-K gate insulation layers and a method for preparing the same |
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Effective date of registration: 20200120 Address after: 401573 No. 500 Jiahe Avenue, Caojie Street, Information Security Industry City, Hechuan District, Chongqing Patentee after: Zhonghe Boxin (Chongqing) Semiconductor Co., Ltd. Address before: 401573 No. 500 Jiahe Avenue, Caojie Street, Hechuan District, Chongqing Patentee before: Zhong Zheng Bo Xin (Chongqing) Semiconductor Co., Ltd. |