CN209896068U - Semiconductor gate electronically controlled quantum dots - Google Patents

Abstract

A semiconductor gate electronically controlled quantum dot, comprising: a substrate (101); a silicon dioxide layer (102), which is formed on the substrate (101), and an ion implantation region (102) is formed on the silicon dioxide layer (102). 200) and a large quantum dot electrode (400), an ohmic contact electrode (300) is prepared in the ion implantation region (200), and a small quantum dot electrode (500) is prepared on the silicon dioxide layer (102), wherein the large quantum dot electrode is (400) is connected to the small quantum dot electrode (500); the insulating layer (600), which is formed on the silicon dioxide layer (102), only covers the quantum dot area, wherein the quantum dot area includes the small quantum dot electrode (500) , the inner region of the quantum dot large electrode (400) and the inner region of the ion implantation region (200). The semiconductor gate electronically controlled quantum dot only retains the aluminum oxide insulating layer in the quantum dot region, which solves the problem of background current that occurs in hole-type quantum dots of traditional silicon semiconductor materials.

Description

Semiconductor gate electronically controlled quantum dots

technical field

The utility model relates to the field of quantum technology, in particular to a semiconductor gate electronically controlled quantum dot.

Background technique

In recent years, in order to realize the preparation of qubits for quantum computing, solid-state semiconductor quantum dots have attracted extensive attention of scientists due to their unique properties. The silicon-based-metal-oxide-semiconductor (Si-MOS) structure, due to its preparation process similar to that of traditional integrated circuit chips, and the scalability of the quantum dot structure on it on a two-dimensional plane, has become the research on quantum dot system. popular.

However, among the two doping methods of silicon-based semiconductor materials, the research on quantum dots prepared on an N-type silicon MOS substrate with electrons as carriers has attracted more attention. For the P-type silicon MOS substrate of hole carriers, after annealing at a high temperature of about 400 degrees Celsius, a two-dimensional bound electron layer will be generated at the interface between the silicon dioxide and the insulating layer of aluminum oxide, so that the surface of the substrate will have a two-dimensional bound electron layer. Two-dimensional hole carriers are excited at the silicon-silicon dioxide interface. In the traditional gate electronically enhanced quantum dot structure, since the aluminum oxide layer used for insulation almost covers the entire surface of the device, the two-dimensional hole carriers are correspondingly distributed at the interface of the entire surface of the device. A large, unregulated background current is generated, rendering the quantum dots inoperable.

Utility model content

(1) Technical problems to be solved

In view of the existing technical problems, the utility model proposes a semiconductor gate electronically controlled quantum dot, which is used to obtain a high-quality semiconductor quantum dot system.

(2) Technical solutions

The utility model provides a semiconductor gate electronically controlled quantum dot, comprising:

The substrate 101; the silicon dioxide layer 102, which is formed on the substrate 101, the silicon dioxide layer 102 is formed with an ion implantation region 200 and a large quantum dot electrode 400, and the ion implantation region 200 is prepared with an ohmic contact electrode 300. The small quantum dot electrodes 500 are prepared on the silicon layer 102, wherein the large quantum dot electrodes 400 are connected to the small quantum dot electrodes 500, the ion implantation region 200 is implanted with boron, and the depth of ion implantation is the interface between the silicon dioxide layer 102 and the substrate 101 The insulating layer 600, which is formed on the silicon dioxide layer 102, only covers the quantum dot area, and the quantum dot area includes the small quantum dot electrode 500, the inner area of the large quantum dot electrode 400 and the ions The inner region of region 200 is implanted.

Optionally, the thickness of the insulating layer 600 is 10˜50 nm.

Optionally, the thickness of the silicon dioxide layer 102 is 5˜50 nm.

Optionally, the small quantum dot electrode 500 is a two-layer metal of titanium (Ti) with a thickness of 2-10 nm and gold (Au) with a thickness of 25-50 nm, or titanium (Ti) with a thickness of 2-10 nm and a thickness of 2-10 nm. Two-layer metal of palladium (Pd) at 25-50 nm.

Optionally, the insulating layer 600 is an aluminum oxide layer.

Optionally, the large quantum dot electrode 400 is a two-layer metal of titanium (Ti) with a thickness of 5-10 nm and gold (Ti) with a thickness of 30-70 nm, or titanium (Ti) with a thickness of 5-10 nm and a thickness of 30-70 nm. Two-layer metal of palladium (Pd) of 30-70 nm.

Optionally, the ohmic contact electrode 300 is a two-layer metal of titanium (Ti) with a thickness of 2-5 nm and aluminum (Al) with a thickness of 35-100 nm.

(3) Beneficial effects

The utility model proposes a semiconductor gate electronically controlled quantum dot, and the beneficial effects are as follows:

1. Most of the aluminum oxide insulating layer is etched away, and only the aluminum oxide insulating layer in the quantum dot area of the semiconductor gate electronically controlled quantum dot is retained, which solves the background current problem in the hole-type quantum dots of traditional silicon semiconductor materials.

2. The semiconductor gate electronically controlled quantum dots can be fully electronically controlled by the gate structure of the traditional depletion-type quantum dots.

3. The semiconductor gate electronically controlled quantum dot opens up a new idea for the preparation of hole spin qubits.

Description of drawings

FIG. 1 schematically shows a schematic cross-sectional structure diagram of a semiconductor gate electronically controlled quantum dot according to an embodiment of the present invention.

FIG. 2 schematically shows a flow chart of a method for preparing a semiconductor gate electronically controlled quantum dot according to an embodiment of the present invention.

FIG. 3 schematically shows a schematic diagram of a metal mark on an intrinsic silicon substrate according to an embodiment of the present invention.

FIG. 4 schematically shows a schematic diagram of an ion implantation region on an intrinsic silicon substrate according to an embodiment of the present invention.

FIG. 5 schematically shows a schematic diagram of an ohmic contact electrode structure prepared on an intrinsic silicon substrate according to an embodiment of the present invention.

FIG. 6 schematically shows a schematic diagram of a large electrode structure of peripheral quantum dots prepared on an intrinsic silicon substrate according to an embodiment of the present invention.

FIG. 7 schematically shows a schematic diagram of a quantum dot small electrode structure prepared on an intrinsic silicon substrate according to an embodiment of the present invention.

FIG. 8 schematically shows the enlarged structural schematic diagram of the internal quantum dot small electrode in FIG. 7 according to the embodiment of the present invention.

FIG. 9 schematically shows a schematic diagram of the aluminum oxide in the remaining quantum dot area after etching on the intrinsic silicon substrate according to the embodiment of the present invention.

FIG. 10 schematically shows the conduction curve of the semiconductor gate electronically controlled quantum dot device according to the embodiment of the present invention.

FIG. 11 schematically shows the Coulomb oscillation curve of the semiconductor gate electronically controlled quantum dot device according to the embodiment of the present invention.

FIG. 12 schematically shows a three-dimensional honeycomb diagram of Coulomb oscillation of the semiconductor gate electronically controlled quantum dot device according to the embodiment of the present invention.

[reference number]

101-Substrate 102-Silicon dioxide

103 - Two-dimensional hole gas 104 - Metal label

200-Ion implantation regions (201, 202, 203, 204)

300-ohm contact electrodes (301, 302, 303, 304)

400-Quantum dot large electrode (401, 402, 403, 404, 405, 406)

500-Quantum dot small electrodes (501, 502, 503, 504, 505, 506)

600-Insulation

701-First Quantum Dot 702-Second Quantum Dot

Detailed ways

In order to make the purpose, technical solutions and advantages of the present utility model more clearly understood, the present utility model will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In order to avoid the influence of two-dimensional hole carriers in traditional structure-enhanced quantum dots, the present invention designs a new quantum dot structure, and uses wet etching to remove most of the aluminum oxide insulating layer, leaving only quantum dots. The aluminum oxide insulating layer in the dot area, after annealing, the area covered with aluminum oxide has two-dimensional hole carriers, and then the gate structure of the traditional depletion-type quantum dot is used for electronic control adjustment, and then the full electric power can be obtained. Controlled gate hole quantum dot devices. This idea cleverly takes advantage of the fact that after high temperature annealing, the interface between alumina and silica can bind electrons so that two-dimensional hole carriers can be induced at the interface between silicon and silica. Specifically, the bound electron layer is formed by annealing the interface between the silicon dioxide layer of the p-type silicon semiconductor material and the aluminum oxide insulating layer to obtain a high-quality semiconductor quantum dot system, which provides a new quantum dot system for quantum computing research based on semiconductor quantum dots. point system.

An embodiment of the present utility model proposes a semiconductor hole-type gate electronically controlled quantum dot, as shown in FIG. 1 , including:

The substrate 101 , in an embodiment of the present invention, uses intrinsic silicon as the substrate 101 .

A silicon dioxide layer 102 is formed on the substrate 101 . An ion implantation region 200 and a large quantum dot electrode 400 are formed on the silicon dioxide layer 102, an ohmic contact electrode 300 is prepared in the ion implantation region 200, and a small quantum dot electrode 500 is prepared on the silicon dioxide layer 102, wherein the large quantum dot electrode is 400 is connected to the small quantum dot electrode 500 . In an embodiment of the present invention, the thickness of the silicon dioxide layer 102 is 5˜50 nm, preferably 20 nm. The ohmic contact electrode 300 is a two-layer metal of titanium (Ti) with a thickness of 2-5 nm and aluminum (Al) with a thickness of 35-100 nm. The quantum small electrode 500 is a two-layer metal of titanium (Ti) with a thickness of 2-10 nm and gold (Au) with a thickness of 25-50 nm, or titanium (Ti) with a thickness of 2-10 nm and palladium with a thickness of 25-50 nm (Pd) two-layer metal. The quantum dot large electrode 400 is a two-layer metal of titanium (Ti) with a thickness of 5-10 nm and gold (Au) with a thickness of 30-70 nm, or titanium (Ti) with a thickness of 5-10 nm and a thickness of 30-70 nm. Two-layer metal of palladium (Pd).

The insulating layer 600 , which is formed on the silicon dioxide layer 102 , covers only the quantum dot region, which includes the quantum dot small electrode 500 , the inner region of the quantum dot large electrode 400 and the inner region of the ion implantation region 200 . In an embodiment of the present invention, the insulating layer 600 is an aluminum oxide layer with a thickness of 10-50 nm, preferably a thickness of 20 nm.

The embodiment of the present utility model provides a preparation method of a semiconductor hole-type gate electronically controlled quantum dot device, by designing a novel semiconductor quantum dot on an intrinsic silicon MOS substrate. The substrate used in the method is a non-doped intrinsic silicon MOS substrate, which is no different from a common intrinsic silicon substrate. Its preparation process is shown in Figure 2, including:

S0 , metal markings 104 are formed on the silicon dioxide layer 102 .

In one embodiment of the present invention, optical exposure and electron beam coating are used to obtain peripherally positioned large metal marks 104 on the substrate (including the substrate 101 and the silicon dioxide layer 102 ), and then the marks are used as overlay alignment , as shown in FIG. 3 , wherein the thickness of the silicon dioxide layer 102 is 5-50 nm, preferably 20 nm. .

S1, prepare an ion implantation region 200 on the silicon dioxide layer 102, and perform ion implantation and annealing.

In an embodiment of the present invention, a hole-type ion implantation region 200 is prepared on the silicon dioxide layer 102 by using a photolithography mask technology and an ion implantation technology. As shown in FIG. 4 , in this embodiment, four Ion implantation regions 201 , 202 , 203 and 204 . Then, ion implantation is performed, and then annealing is performed by high temperature annealing technology. The implanted ions are boron (B), the implantation meter is 10 ¹⁵ cm ^-2 , and the depth of ion implantation is that the interface between the silicon dioxide layer 102 and the substrate 101 faces the substrate 101 The direction is 1-10 nm, the annealing condition is that the degree of vacuum is less than 10 ^-3 Pa, the annealing temperature is 950-1050° C., and the time is 5-15 minutes.

S2, the ohmic contact electrode 300 is prepared in the ion implantation region 200, and the large quantum dot electrode 400 is prepared.

In an embodiment of the present invention, the ohmic contact electrodes 300 are prepared by using ultraviolet lithography, electron beam evaporation coating, wet shallow etching and metal stripping techniques. As shown in FIG. 5 , four ohmic contact electrodes 301 are prepared in this embodiment. , 302, 303 and 304, a total of 4 contact windows are exposed on this ion implantation region 200, and the wet shallow etching technique is used to etch the silicon dioxide 102 on the surface of the substrate in the 4 contact windows by BOE, Then immediately use electron beam evaporation coating technology to deposit two layers of titanium (Ti) with a thickness of 2 to 5 nm and aluminum (Al) with a thickness of 35 to 100 nm, and then use acetone to soak to complete the metal stripping, forming a metal covering the four contact windows. The ohmic contact electrodes 301, 302, 303 and 304 of the silicon MOS substrate, in which the metal Ti is used as an adhesion layer. Among them, the photoresist used is AZ5214E, the baking temperature is 95°C, the baking time is 90 seconds, and the etching solution is BOE, which is no different from the traditional BOE. The etching is carried out at room temperature and the time is 15 seconds.

The outer quantum dot large electrode 400 is prepared by using ultraviolet lithography and electron beam evaporation coating, as shown in FIG. 6 . On the basis of the above preparation, UV optical overlay exposure is used to expose the required window of the peripheral quantum dot large electrode 400, and electron beam evaporation coating is used to deposit titanium (Ti) with a thickness of 5-10 nm and a thickness of 30-70 nm successively. Two-layer metal of gold (Au), or two-layer metal of titanium (Ti) with a thickness of 5-10nm and palladium (Pd) with a thickness of 30-70nm, and then immersed in acetone to complete the metal stripping to form a large quantum dot electrode 400 , 6 large quantum dot electrodes (401, 402, 403, 404, 405, 406) are prepared in this example, corresponding to the small quantum dot electrodes prepared subsequently.

S3 , preparing small quantum dot electrodes 500 on the silicon dioxide layer 102 , wherein the large quantum dot electrodes 400 are connected to the small quantum dot electrodes 500 .

In an embodiment of the present utility model, first, electron beam exposure (10nm-500nm scale) is performed using electron beam exposure technology, and 10μm*10μm metal marks prepared by photolithography are used for alignment during overlay exposure. . Then, carry out pattern development, and then carry out electron beam evaporation coating. The coating metal selects a two-layer metal of titanium (Ti) with a thickness of 2-10 nm and gold (Au) with a thickness of 25-50 nm or titanium with a thickness of 2-10 nm. (Ti) and a two-layer metal of palladium (Pd) with a thickness of 25 to 50 nm; nanoscale quantum dot electrodes 500 (501, 502, 503, 504, 505, 506) with quantum regions formed after metal stripping are completed by soaking in acetone, As shown in FIG. 7 , its enlarged schematic diagram is shown in FIG. 8 . The 6 quantum dot small electrodes (501, 502, 503, 504, 505, 506) on the nanoscale are respectively connected with the 6 quantum dot large electrodes (401, 402, 403, 404, 405, 406) in the peripheral quantum dot large electrodes. one end is connected. The small quantum dot electrodes 500 are used to adjust the potential of the quantum dots, and the large quantum dot electrodes 400 are used to connect the small electrodes to the large scale for experimental wiring measurements. Among them, the electron beam exposure glue is double-layer PMMA950A ₂ glue, the glue temperature is 180°C, and the time is 5 minutes and 10 minutes respectively.

S4, an insulating layer 600 is prepared on the silicon dioxide layer 102, wherein the insulating layer 600 only covers the quantum dot region.

In an embodiment of the present invention, an aluminum oxide layer is first grown on the silicon dioxide layer 102 by using atomic layer deposition (ALD) technology as the insulating layer 600 , wherein the thickness of the insulating layer 600 is 10-50 nm, preferably 20 nm. , as shown in Figure 9.

Then, using ultraviolet optical overlay exposure, the aluminum oxide in the quantum region of the semiconductor hole-type gate electronically controlled quantum dot is exposed, and then the remaining part of the aluminum oxide is etched cleanly by using the wet shallow etching technology to make the aluminum oxide The layer only covers the quantum dot region, which includes the small quantum dot electrode 500 , the inner region of the quantum dot large electrode 400 , and the inner region of the ion implantation region 200 .

S5, annealing the device after step S4 to obtain two-dimensional hole gas in the quantum dot region.

In an embodiment of the present utility model, using the high temperature reducing gas protection annealing technology, under the protection of 95% to 85% nitrogen and 55 to 15% hydrogen at 0.05 to 0.2 MPa, annealing at a temperature of 380 ° C to 430 ° C for 10 ~ For 30 minutes, two-dimensional hole gas is formed.

Among them, the photoresist used is AZ5214E, the baking temperature is 95°C, the baking time is 90 seconds, the etching solution is TRANSETCH-N, the etching is performed in an oil bath at 120°C, and the etching time is 10 seconds.

In order to further verify the performance of the semiconductor hole-type gate electronically controlled quantum dots prepared by the preparation method of the semiconductor hole-type gate electronically controlled quantum dots proposed by the present invention, a series of tests on the semiconductor quantum chips were carried out. Through the test, a new quantum dot material and structural system are provided for quantum computing research based on semiconductor quantum dots.

As shown in FIG. 6 and FIG. 7 , taking the first quantum dot 701 as an example, the bound charges formed after the annealing of the insulating layer 600 are used to excite two-dimensional hole gas below to form a conductive channel. Conduction strips with different hole carrier densities can be obtained by changing the magnitude of the voltage applied to the quantum dot small electrode 501 (metal gate). First, the small quantum dot electrodes 503 , 504 and 505 are grounded to avoid interference to the first quantum dot 701 . An AC excitation voltage of about 20uV is applied to the ohmic contact electrode 303 (source electrode) of the first quantum dot 701, and the ohmic contact electrode 302 (drain electrode) is connected to the transport signal of the measurement channel in the lock-in amplifier SR830, as shown in Figure 10 As shown, by scanning the DC voltage applied on the quantum dot small electrode 501 (metal gate), it can be seen that when the voltage value is about 1V, the ohmic contact electrode 302 (drain electrode) begins to have current, and with the voltage on the metal gate Gradually decrease, the on-current increases.

For the second quantum dot 702, by adjusting the three electrodes L (505), M (504) and R (503) in the small quantum dot electrode, the size of the second quantum dot 702 can be changed, when the size of the quantum dot becomes smaller. , the holes in the quantum dots can be discharged one by one. Under the condition that the voltages of electrodes L and R remain unchanged, by scanning the change of the voltage value applied to the quantum dot electrode M, a series of quantum dots as shown in FIG. 11 can be obtained from the ohmic contact electrode 301 (source electrode) through the quantum Coulomb peak oscillation process of point transport into the ohmic contact electrode 304 (drain electrode). Under the condition that the voltage of the electrode M remains unchanged, the changes of the voltage values applied to the electrodes L and R of the quantum dot electrodes are simultaneously scanned, and the three-dimensional Coulomb oscillation honeycomb diagram as shown in FIG. 12 can be obtained.

The so-called Coulomb peak oscillation is the quantum tunneling process. In the macroscopic classical world, an object cannot pass through a potential barrier higher than itself, but in the microscopic quantum mechanics, electron or hole carriers are in the potential well. Both inside and outside are probabilistically distributed, electrons or holes can tunnel through a potential barrier of a certain height and width, and different potential barrier heights and widths can indicate different tunneling probabilities of electrons or holes, and can also indicate that they are in Probability distribution inside the potential well and outside the potential well.

The experimental data shown in FIG. 10 , FIG. 11 and FIG. 12 show that the silicon-based hole-type gate electronically controlled quantum dots designed and prepared by the present invention can work well and have excellent sample performance. Therefore, the number of holes in the quantum dots can be precisely controlled one by one, and when the holes in the quantum dots are discharged to the last hole, by applying a magnetic field parallel to the two-dimensional hole gas layer, the spins are turned up and down The two hole states of , respectively encode the 0 and 1 of the qubit, forming a hole-type qubit. It can be manipulated with qubits using electrical pulses and microwaves. In addition, using another quantum dot as a detector for detection as described above is equivalent to preparing a hole-spin qubit chip device with a detector. The utility model lays a solid foundation for subsequent quantum bit preparation and manipulation and quantum computing research.

In summary, the present utility model proposes a semiconductor hole-type gate electronically controlled quantum dot and a preparation method thereof. By etching away most of the alumina insulating layer, only the quantum dot region of the semiconductor gate electronically controlled quantum dot is retained. The aluminum oxide insulating layer solves the background current problem in the hole-type quantum dots of traditional silicon semiconductor materials. The semiconductor hole-type gate electronically controlled quantum dot can be electrically controlled and regulated by the gate structure of the traditional depletion-type quantum dot, so that the quantum dot device can be fully electronically controlled. This preparation method opens up a new idea for the preparation of hole spin qubits.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention, and are not intended to limit the present invention. In the utility model, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims (7)

1. An electrically controlled quantum dot for a semiconductor gate, comprising:

a substrate (101);

the silicon dioxide layer (102) is formed on the substrate (101), an ion implantation area (200) and a quantum dot large electrode (400) are formed on the silicon dioxide layer (102), an ohmic contact electrode (300) is prepared in the ion implantation area (200), a quantum dot small electrode (500) is prepared on the silicon dioxide layer (102), the quantum dot large electrode (400) is connected with the quantum dot small electrode (500), boron is implanted into the ion implantation area (200), and the depth of ion implantation is 1-10 nm towards the direction of the substrate (101) at the interface of the silicon dioxide layer (102) and the substrate (101);

an insulating layer (600) formed on the silicon dioxide layer (102) covering only a quantum dot region, wherein the quantum dot region includes an inner region of the quantum dot small electrode (500), the quantum dot large electrode (400), and an inner region of the ion implantation region (200).

2. The semiconductor gate electrically controlled quantum dot according to claim 1, wherein the thickness of the insulating layer (600) is 10-50 nm.

3. The semiconductor gate electrically controlled quantum dot according to claim 1, wherein the thickness of the silicon dioxide layer (102) is 5-50 nm.

4. The semiconductor gate electrically controlled quantum dot according to claim 1, wherein the quantum dot small electrode (500) is a two-layer metal of titanium with a thickness of 2-10 nm and gold with a thickness of 25-50 nm, or a two-layer metal of titanium with a thickness of 2-10 nm and palladium with a thickness of 25-50 nm.

5. A semiconductor gate electrically controlled quantum dot according to claim 1, wherein the insulating layer (600) is aluminum oxide.

6. The semiconductor gate electrically controlled quantum dot according to claim 1, wherein the quantum dot large electrode (400) is a two-layer metal of titanium with a thickness of 5-10 nm and gold with a thickness of 30-70 nm, or a two-layer metal of titanium with a thickness of 5-10 nm and palladium with a thickness of 30-70 nm.

7. The semiconductor gate electrically controlled quantum dot according to claim 1, wherein the ohmic contact electrode (300) is a two-layer metal of titanium with a thickness of 2-5 nm and aluminum with a thickness of 35-100 nm.

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