CN209803776U

CN209803776U - NVDIMM controller and NVDIMM

Info

Publication number: CN209803776U
Application number: CN201822267330.3U
Authority: CN
Inventors: 周小锋; 江喜平
Original assignee: Xian Unilc Semiconductors Co Ltd
Current assignee: Xi'an Ziguang Guoxin Semiconductor Co ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2019-12-17
Anticipated expiration: 2028-12-29

Abstract

The utility model provides a NVDIMM controller (100) and NVDIMM (200). The NVDIMM (200) includes DRAM (201), NAND flash (202), and an NVDIMM controller that controls the NVDIMM and includes a DDR controller (101), a NAND flash controller (102), the DDR controller employing and enabling DBI. The NVDIMM controller further includes: a data backup module (103) that encodes the N bits DQ and 1 bit DBI read from the DRAM by the DDR controller into N bits EDQ and sends N bits EDQ to the NAND flash controller; and a data recovery module (104) which decodes the N bits EDQ read from the NAND flash by the NAND flash controller into N bits DQ and 1 bit DBI and sends the N bits DQ and 1 bit DBI to the DDR controller, wherein the data backup module is connected with the DDR controller and the NAND flash controller, and the data recovery module is connected with the DDR controller and the NAND flash controller.

Description

NVDIMM controller and NVDIMM

Technical Field

The utility model relates to a non-volatile memory field, more specifically relate to a NVDIMM controller and NVDIMM of low-power consumption.

Background

NVDIMM is a non-volatile memory that includes DRAM, NAND Flash (NAND Flash), and NVDIMM controller. When the mainboard/CPU is abnormal or the power is down, the NVDIMM controller is informed through an interrupt or a message, and the NVDIMM controller can back up the data in the DRAM to the NAND flash memory. When the main board/CPU is powered on again later, the main board/CPU informs the NVDIMM controller to restore the data backed up in the NAND flash memory to the DRAM, and charges the super capacitor. The NVDIMM is powered by the super capacitor during data backup, but the super capacitor has limited power supply capacity and has larger attenuation along with the service time and the working temperature. For NVDIMMs, power consumption for data backup and data backup/restore time are two important performance indicators, which determine the capacity and reliability of the super capacitor and the cost of the product. The increase of data backup power consumption inevitably needs to improve the capacity of the super capacitor, and the increase of the capacity of the super capacitor can bring about the increase of cost and the reduction of reliability; data backup/restore time determines power consumption and user experience during data backup. Therefore, the fast backup and recovery of the NVDIMM data with low power consumption can obviously improve the competitiveness of products.

In order to reduce interface power consumption, a Data Bus Inversion (DBI) mechanism is introduced into DDR 4. For the NVDIMM controller of JEDEC specification (JESD245A/B), operation of DDRx and NAND flash memory interface is required both at data backup and recovery. DDR4 uses 1.2V interface voltage and POD (pseudo Open Drain) technology, combined with DBI, can reduce the power consumption of 25-40% interface. Although the existing NVDIMM product adopts the DBI mechanism on the DDR (DDR4) side to significantly reduce the DRAM operation power consumption, the data to be backed up needs to be written into the NAND flash memory together with the DBI indication when backing up the data, so that the DRAM can get the correct data when the DBI indication signal is given to the recovery data. Backing up the DBI may bring additional storage overhead to NVDIMM to back up data while increasing the power consumption of the backup. Taking 16GB NVDIMM DDR4x8 as an example, backing up DBI requires an increase in storage space of 2GB, which will lengthen 1/8 backup and restore times and will also increase backup power consumption by about 1/8.

Chinese patent publication CN108255428A discloses a data processing method, apparatus and electronic device. The data processing method comprises the following steps: receiving a data transmission request, wherein the data transmission request indicates that data stored by the NVDIMM is transmitted to the block device, and the data transmission request carries an identifier of a data block; determining storage position information of target data in the NVDIMM according to the data transmission request, wherein the target data are to-be-transmitted data corresponding to the data transmission request; the target data indicated by the storage location information in the NVDIMM is directly transferred to the block device in byte access. However, the method reduces the data transmission time by using the NVDIMM level on the mainboard/CPU, the data required to be stored in the NVDIMM has certain characteristics, and the design point of the NVDIMM is not considered, so that the method does not have the universal low-power-consumption fast data backup and recovery characteristic of the NVDIMM.

SUMMERY OF THE UTILITY MODEL

For an NVDIMM controller using a DBI mechanism, the power consumption of a DDR interface can be obviously reduced, but the storage of DBI information increases the storage space and the power consumption of a NAND flash memory interface during data backup, and simultaneously increases the data backup and recovery time. Therefore, the object of the present invention is to solve the following problems:

(1) Reducing data backup power consumption of the NVDIMM by using the NVDIMM controller;

(2) Data backup and recovery time of the NVDIMM is reduced with the NVDIMM controller.

The utility model discloses an above-mentioned technical problem is solved to following aspect.

according to a first aspect of the present invention, there is provided an NVDIMM controller comprising a DDR controller and a NAND flash memory controller, the NVDIMM controller being configured to control an NVDIMM, the NVDIMM comprising a DRAM and a NAND flash memory, the DDR controller being connected to the DRAM, the NAND flash memory controller being connected to the NAND flash memory, wherein the DDR controller employs and enables a DBI, characterized in that,

The NVDIMM controller further comprises:

A data backup module encoding the N bits DQ and 1 bit DBI read from the DRAM by the DDR controller into N bits EDQ and sending N bits EDQ to the NAND flash memory controller; and

A data recovery module to decode the N bits EDQ read from the NAND flash by the NAND flash controller into N bits DQ and 1 bit DBI and send the N bits DQ and 1 bit DBI to the DDR controller,

The data backup module is connected with the DDR controller and the NAND flash memory controller, and the data recovery module is connected with the DDR controller and the NAND flash memory controller.

according to a preferred embodiment of the first aspect of the present invention, wherein the data backup module encodes the N bits EDQ to be the same as the N bits DQ when the N bits DQ contain N/2 "1 s", and maps the N bits DQ index to N-1 bits of N bits EDQ and writes 1 bits DBI to the remaining 1 bits of N bits EDQ when the number of "1 s" of the N bits DQ is not N/2, wherein the number of bits of "1 s" of N bits EDQ is not N/2.

According to a preferred embodiment of the first aspect of the present invention, wherein the data recovery module decodes the N bits EDQ into the same N bits DQ when N/2 "1" s are contained in the N bits EDQ, and inversely maps the N bits EDQ into N bits DQ and 1 bits DBI when the number of "1" s in the N bits EDQ is not N/2.

according to a preferred embodiment of the first aspect of the present invention, wherein the DRAM is DDR 4.

According to a preferred embodiment of the first aspect of the present invention, wherein the DDR4 is DDR4 × 8 or DDR4 × 16.

According to a preferred embodiment of the first aspect of the present invention, wherein, when the DDR4 is DDR4 × 8, the EDQ is 8 bits EDQ, the data backup module encodes the 8 bits DQ into the same 8 bits EDQ when there are 4 "1" s in 8 bits EDQ, and maps the 8 bits DQ index to 7 bits in 8 bits EDQ and writes 1 bit DBI into the remaining 1 bits in 8 bits EDQ when there are 5-8 "1 s in 8 bits EDQ, wherein the number of bits of" 1 "in 8 bits EDQ is not 4.

According to a preferred embodiment of the first aspect of the present invention, wherein the data recovery module makes the DQ identical to the EDQ when 4 "1" s are contained in 8 bits EDQ, and demaps the 8 bits EDQ to 8 bits DQ and 1 bit DBI when not 4 "1" s are contained in 8 bits EDQ.

According to a second aspect of the present invention, there is provided an NVDIMM comprising the NVDIMM controller of the first aspect.

The utility model discloses a NVDIMM controller is to the DDR that has used the DBI mechanism, wherein 1) NVDIMM controller's data backup module is encoded N bit DQ and 1 bit DBI that the DDR controller read from DRAM into N bit EDQ, and sends N bit EDQ to NAND flash memory controller; and 2) the data recovery module of the NVDIMM controller decodes the N bits EDQ read from the NAND flash by the NAND flash controller into the N bits DQ and the 1 bit DBI and sends the N bits DQ and the 1 bit DBI to the DDR controller. The NVDIMM adopting the NVDIMM controller can reduce power consumption and reduce data backup and recovery time.

Drawings

The invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is to be understood that these drawings are for illustrative purposes only and are not necessarily drawn to scale. In the drawings:

Fig. 1 is a system block diagram of an NVDIMM controller according to one embodiment of the present invention.

Fig. 2 is a schematic diagram of an NVDIMM in accordance with an embodiment of the present invention.

Detailed Description

according to the utility model discloses, NVDIMM controller realizes that nonvolatile function is mainly accomplished by DDR controller, NAND flash memory controller and data backup/recovery module triplex, and these triplex are realized using FPGA or ASIC. The DDR controller is used for controlling the DRAM, and the NAND flash memory controller is used for controlling the NAND flash memory. The utility model discloses to the DDR who has used the DBI function, wherein data backup/restore the module to DQ and the two codec processing of DBI in order to realize interface low-power consumption, improved data backup/restore speed simultaneously. The DDR described hereinafter refers to DDR4, but it should be understood that the invention is not limited to DDR4, and that the invention is equally applicable to other existing and future DDR versions that support DBI.

Fig. 1 is a system block diagram of an NVDIMM controller according to one embodiment of the present invention. Taking DDR4x8 as an example, the interface signals associated with a DDR controller are 8 bits DQ and 1 bit DBI, and the interface signals associated with a NAND flash controller are encoded DQ (edq).

The operation of the NVDIMM controller will be described in detail below.

The DDR controller reads data from DRAM, due to the action of DBI, the number of '1' in DQ and DBI indication has 9 possibilities, as shown in Table 1, DBI is '0' indicating that there is a flip in DQ data, otherwise, DQ is not flipped.

table 1: DQ and DBI values and relationships

As can be seen from table 1, when DBI is 1, the data actually stored in the DRAM is the same as DQ read by the DDR controller; when DBI is 0, the data actually stored in the DRAM is opposite to the DQ read by the DDR controller.

According to the characteristics of the DQ, there are only 4/5/6/7/8 '1's in the 8-bit data. The utility model discloses a NVDIMM controller is based on this kind of characteristics, creatively encodes DQ and DBI the two jointly, generates 8 bit EDQ, as shown in Table 2, and data backup module represents 8 bit DQ and 1 bit DBI with 8 bits EDQ through the coding, and EDQ writes into NAND flash memory through NAND flash memory controller, accomplishes the data backup.

TABLE 2 DQ, DBI and EDQ coding relationship Table

For the case of 5/6/7/8 '1's in DQ, to distinguish from the case of 4 '1's in DQ, when DBI is 1, no 3-bit '1' is contained in 7-bit EDQ representing an index map of 93 possible DQ values; when DBI is 0, no 4-bit '1' is contained in the 7-bit EDQ representing the index map of 93 possible DQ values.

For example, in one embodiment, when DBI is 1, EDQ [7] ═ DBI, EDQ [6:0] represents an indexed mapping of 93 possible DQ values, where 3 bits '1' are not contained in EDQ [6:0 ]; when DBI is equal to 0, EDQ [7] ═ DBI, EDQ [6:0] represents an indexed mapping of 93 possible DQ values, with EDQ [6:0] not containing a 4-bit '1'.

The above embodiment places the DBI information high at EDQ, but it is understood that the DBI information can be placed anywhere in EDQ.

When the NVDIMM controller restores the data, the NAND flash controller first reads EDQ data from the NAND flash that was written at the time of the backup. And then the data recovery module decodes the read EDQ data to obtain DQ and DBI, and sends the decoded DQ and DBI to the DDR controller, wherein the decoding process is the reverse process of Table 2, if EDQ has 4 bits of '1', the decoding is not needed, otherwise, 8 bits of EDQ are reversely mapped to 8 bits of DQ and 1 bit of DBI. And finally, the DDR controller pulls down/pulls up a DBI signal of an interface of the DDR controller according to the DBI, the DQ is sent to the DRAM, and the DRAM determines whether to flip the DQ according to the value of the DBI, so that data recovery is completed.

the example of DDR4x8 has been described above, but it should be understood that the present invention is equally applicable to DDR4x 16. Fig. 2 is a schematic diagram of an NVDIMM in accordance with an embodiment of the present invention. As shown in fig. 2, the NVDIMM controller 100 includes a DDR controller 101, a NAND flash controller 102, a data backup module 103 and a data restore module 104. The NVDIMM controller controls NVDIMM200 including DRAM 201 and NAND flash memory 202, and the data backup/restore module implements data backup and data restore. The DDR controller is connected with the DRAM, the NAND flash memory controller is connected with the NAND flash memory, the data backup module is connected with the DDR controller and the NAND flash memory controller, and the data recovery module is connected with the DDR controller and the NAND flash memory controller.

It is understood that these embodiments are for illustrative purposes only and that many variations may be made by those skilled in the art, while the scope of the invention is defined by the claims.

Claims

1. an NVDIMM controller comprising a DDR controller and a NAND flash memory controller, the NVDIMM controller for controlling an NVDIMM, the NVDIMM comprising DRAM and NAND flash memory, the DDR controller coupled to the DRAM, the NAND flash memory controller coupled to the NAND flash memory, wherein the DDR controller employs and enables DBI,

The NVDIMM controller further comprises:

2. the NVDIMM controller of claim 1, wherein the data backup module to encode the N bits EDQ to be the same as the N bits DQ if the N bits DQ contain N/2 "1 s, and to map the N bits DQ index to N-1 bits of N bits EDQ and to write 1 bits DBI to the remaining 1 bit of N bits EDQ if the number of" 1 s "of the N bits DQ is not N/2, wherein the number of bits of" 1 s "of N bits EDQ is not N/2.

3. the NVDIMM controller of claim 1 or 2, wherein the data recovery module decodes the N bits EDQ to the same N bits DQ when N/2 "1 s" are contained in the N bits EDQ and demaps the N bits EDQ to N bits DQ and 1 bit DBI when the number of "1 s" in the N bits EDQ is not N/2.

4. the NVDIMM controller of claim 1, wherein the DRAM is DDR 4.

5. The NVDIMM controller of claim 4, wherein the DDR4 is DDR4x8 or DDR4x 16.

6. The NVDIMM controller of claim 5, wherein when the DDR4 is DDR4x8, the EDQ is 8 bits EDQ, the data backup module encodes the 8 bits DQ to be the same 8 bits EDQ when 4 "1 s" are contained in 8 bits EDQ, and maps an 8 bits DQ index to 7 bits in 8 bits EDQ and writes a 1 bit DBI to the remaining 1 bit in 8 bits EDQ when 5-8 "1 s" are contained in 8 bits EDQ, wherein the number of bits of "1 s" in 8 bits EDQ is not 4.

7. The NVDIMM controller of claim 6, wherein the data recovery module makes the DQ the same as the EDQ when 4 "1 s" are contained in 8 bits EDQ and demaps the 8 bits EDQ into 8 bits DQ and 1 bit DBI when non-4 "1 s" are contained in 8 bits EDQ.

8. An NVDIMM comprising the NVDIMM controller of any one of claims 1-7.