CN209388803U - Chip resistor - Google Patents

Abstract

The utility model provides a chip resistor, include: the resistor comprises a ceramic substrate and two resistor layers arranged on two surfaces of the ceramic substrate, wherein the two resistor layers are connected in series through side guide pieces on the side wall of the ceramic substrate, and the resistor is suitable for thick-film high-resistance products. This application has series resistance and sets up in wafer chip's two relative surfaces, increases the elastic beneficial effect of resistance design.

Description

Chip resistor

technical field

The present invention relates to a chip resistor, in particular to a chip resistor in the form of series double-sided.

Background technique

Chip resistor (R-Chip) is a passive component whose main function is to reduce voltage and limit current. The known resistance chip adopts the ceramic substrate of aluminum oxide crystallization, prints the metal thick film conductor, and coats the glass uranium protection chip on the outer layer. Chip resistors are suitable for 3C products because of their small size and high power.

Utility model content

The present invention provides a chip resistor, which has series resistors arranged on two opposite surfaces of the chip to increase the flexibility of resistor design.

The present invention provides a chip resistor, which has series resistors arranged on two opposite surfaces of the chip, and is suitable for thick-film high-resistance chip resistors, and can be applied to frequency dividers (dividers), frequency mixers (hybrids), X- X-ray equipment, low signal detection circuit (low signal detection circuit), amplification circuit (amplification circuit), high impedance quartz amplifier (high impedance quartz amplifier) or other test equipment.

According to the above, a chip resistor includes: a body, the body has a first surface opposite to a second surface and a plurality of sidewalls between the first surface and the second surface; a first Terminal electrodes and a second terminal electrode are separately disposed on the first surface; a first resistance layer is disposed on the first surface, and the first resistance layer has a long curved shape and a first resistance with two ends pattern, wherein, any one of the terminals of the first resistance pattern is connected to the first terminal electrode, and the other terminal is connected to the second terminal electrode; a first protection layer covers the first resistance layer; a first conductive pad It is arranged on the body to electrically connect a circuit board to the outside; a second conductive pad and a third conductive pad are separately arranged on the second surface; a second resistance layer is arranged on the second surface, The second resistive layer has a second resistive pattern that is curved and has two ends, wherein any end of the second resistive pattern is connected to the second conductive pad, and the other end is connected to the third conductive pad. pad; a second protection layer covers the second resistance layer; and a first side lead is disposed on one of the sidewalls, the first side lead is electrically connected to the second terminal electrode and the second conductive pad .

In one embodiment, the chip resistor further includes: a second side lead is disposed on one of the sidewalls, wherein the first conductive pad is disposed on the second surface, and the second side lead is structurally connected to The first terminal electrode is connected to the first conductive pad, and the second side conductor is electrically connected to the first terminal electrode and the first conductive pad.

In one embodiment, the first side guide and the second side guide are disposed on the same or different side walls.

In one embodiment, the second protection layer covers the second conductive pad, covers or exposes a portion of the second surface between the second conductive pad and the third conductive pad, and exposes the third conductive pad.

In one embodiment, the chip resistor further includes: a fourth conductive pad disposed on the second surface, the fourth conductive pad is structurally connected to the third conductive pad exposed by the second protection layer and electrically connected to the first conductive pad. Three conductive pads.

In one embodiment, the second protection layer is interposed between the fourth conductive pad and the first side guide to electrically insulate the fourth conductive pad from the first side guide.

In one embodiment, the chip resistor further includes: a third protective layer covering the first side lead.

In one embodiment, an impedance range of the chip resistor is 1G˜2G ohms.

In one embodiment, the first resistance layer and the second resistance layer are in a series relationship.

In one embodiment, the body is a ceramic substrate.

Description of drawings

FIG. 1 is a top perspective schematic diagram of a first embodiment of a chip resistor of the present application;

FIG. 2 is a schematic bottom view of the first embodiment of the chip resistor of the present application;

FIG. 3 is a top perspective schematic diagram of the partial structure of the first embodiment of the chip resistor of the present application;

Fig. 4 is a schematic bottom perspective schematic diagram of partial structure development of the first embodiment of the chip resistor of the present application;

FIG. 5 is a perspective view from the bottom of the second embodiment of the chip resistor of the present application;

FIG. 6 is a perspective view from the bottom of the third embodiment of the chip resistor of the present application;

FIG. 7 is a bottom perspective schematic diagram of a fourth embodiment of a chip resistor of the present application.

Figure number:

Chip resistors 2, 4, 6, 8

Ontology 10

first surface 12

second surface 14

side wall 16

Terminal electrodes 22, 24

The first resistive layer 21

First protective layer 29

Second resistance layer 41

first conductive pad 42

Second conductive pad 44

The third conductive pad 46

Fourth conductive pad 48

Second protective layer 49

Side guides 62, 64

third protective layer 69

Detailed ways

FIG. 1 and FIG. 2 are respectively top and bottom stereoscopic diagrams of the first embodiment of the chip resistor of the present application. FIG. 3 and FIG. 4 are respectively a top view and a bottom perspective schematic diagram of the partial structure development of the first embodiment of the chip resistor of the present application. Referring to FIGS. 1 to 4 , the chip resistor 2 has a quadrilateral shape, including a body 10 , a first surface 12 and a second surface 14 , and four sidewalls 16 connecting the first surface 12 and the second surface 14 . In the first embodiment, the terminal electrode 22 , the terminal electrode 24 , the first resistive layer 21 and the first protection layer 29 are disposed on the first surface 12 . Secondly, the first resistance layer 21 has a first resistance pattern with a long curved shape and two ends, wherein the two ends are structurally adjacent to the terminal electrode 22 and the terminal electrode 24 respectively arranged apart from each other, and are electrically connected to the terminal electrodes respectively. 22 and terminal electrode 24. Furthermore, the first protection layer 29 covers the entire first resistive layer 21 , so the terminal electrodes 22 , the terminal electrodes 24 and part of the first surface 12 are exposed. Then, on the side wall 16, a side guide 62 and a side guide 64 are provided at intervals, wherein the terminal electrode 22 and the side guide 62 are structurally adjacent and electrically connected, and the terminal electrode 24 and the side guide 64 are structurally Adjacent and electrically connected, but the application is not limited to this aspect.

1 to 4, the second surface 14 is provided with a first conductive pad 42, a second conductive pad 44, a third conductive pad 46 and a second resistance layer 41, wherein the first conductive pad 42 and the side guide 62 Structurally adjacent and electrically connected, the second conductive pad 44 and the side guide 64 (first side guide) are structurally adjacent and electrically connected. Secondly, the second resistive layer 41 has a second resistive pattern with a long curved shape and two ends, wherein the two ends are respectively structurally adjacent to the second conductive pad 44 and the third conductive pad 46 that are spaced apart, and respectively The ground electrically connects the second conductive pad 44 and the third conductive pad 46 . Furthermore, the second protective layer 49 covers the entire second resistive layer 41, the second conductive pad 44 and the second surface 14 of the part between the second conductive pad 44 and the third conductive pad 46, therefore, the first The conductive pad 42 and the third conductive pad 46 are not covered by the second protection layer 49 . Next, the fourth conductive pad 48 is disposed on the third conductive pad 46 and overlaps part of the second protection layer 49 , wherein the fourth conductive pad 48 and the third conductive pad 46 are structurally overlapped and electrically connected. In addition, the side guide 64 can be covered with a third protection layer 69 , wherein the third protection layer 69 extends to the second protection layer 49 , and the third protection layer 69 electrically isolates the side guide 64 and the fourth conductive pad 48 . Alternatively, the length of the fourth conductive pad 48 can be reduced to ensure electrical isolation from the side guide 64 .

With reference to FIGS. 1 to 4, in one embodiment, in terms of a current path, the current enters from the terminal electrode 22 and passes through the first resistance layer 21, the terminal electrode 24, the side guide 64, and the second conductive pad in sequence. 44 . The second resistance layer 41 reaches the third conductive pad 46 . Therefore, the first resistor layer 21 and the second resistor layer 41 are in a series relationship. Moreover, the first conductive pad 42 and the fourth conductive pad 48 can be respectively used as conductive pads, so as to communicate with an external circuit board (not shown in the figure). Therefore, through the electrical connection between the first conductive pad 42, the side guide 62 and the terminal electrode 22, and the electrical connection between the fourth conductive pad 48 and the third conductive pad 46, the current can enter from the first conductive pad 42 and pass through the above-mentioned After the current path, it is transmitted to the outside by the fourth conductive pad 48 .

According to the above, one of the structural features of the chip resistor is that two relatively large surfaces of the main body are respectively provided with a resistance layer, and the two resistance layers form a series relationship through the terminal electrodes, side guides and conductive pads. Therefore, the chip resistor of the present application can be applied to a thick-film high-resistance chip resistor, and the extended resistance range can reach 1G˜2G ohms. Secondly, at least one of the four side walls between the relatively larger two surfaces can be provided with at least one side guide, and the side guide bridges and electrically connects the resistive layers on the two surfaces. Furthermore, one of the relatively larger two surfaces of the main body of the chip resistor 2 can be provided with a conductive pad as a welding pad, so as to be fixed to the external circuit board and electrically connected to the external circuit board, wherein the conductive pad is electrically connected by a side lead terminal electrodes on the other surface. It can be understood that the patterns, sizes, and positions of the terminal electrodes, resistive layers, side guides, and conductive pads that can perform the above functions can be changed according to needs, and are not limited to those shown in FIGS. 1 to 4 . Secondly, the conductive pad used as the welding pad must be electrically insulated from the side conductors forming the resistance series, so as to prevent the current from directly taking the shortest path without flowing through the resistance layer. Therefore, the electrical insulation between the conductive pad and the side conductor can be prevented through the protection layer or by adjusting the size of the conductive pad.

Also, there are many kinds of materials and ways of forming structures that can perform the above functions. For example, the body of the chip resistor can use a ceramic substrate; the terminal electrodes, resistor layers and conductive pads on the two surfaces can be printed with the same or different conductive pastes and then sintered and solidified; the side guides can be vapor-deposited conductive materials formed on the side wall; and the protective layer is made of an insulating material such as epoxy resin or glass resin.

FIG. 5 is a perspective schematic bottom view of a second embodiment of a chip resistor of the present application. Please refer to FIG. 2 and FIG. 5 at the same time. The difference between the chip resistor 4 and the chip resistor 2 of the first embodiment is only that the chip resistor 4 omits the fourth conductive pad 48 of the chip resistor 2, so on the second surface 14, the first The second protection layer 49 exposes the first conductive pad 42 and the third conductive pad 46 . Therefore, the third conductive pad 46 is also used for fixing and electrically connecting with an external circuit board (not shown in the figure).

FIG. 6 is a perspective schematic bottom view of a third embodiment of a chip resistor of the present application. Please refer to FIG. 2 and FIG. 6 at the same time. The difference between the chip resistor 6 and the chip resistor 2 of the first embodiment is only that the chip resistor 6 omits the fourth conductive pad 48 and the size of the second protective layer 49 of the chip resistor 2. . The second protective layer 49 of the chip resistor 6 is relatively small, thus exposing part of the second surface 14 .

FIG. 7 is a bottom perspective schematic diagram of a fourth embodiment of a chip resistor of the present application. Please refer to FIG. 2 and FIG. 7 at the same time. The difference between the chip resistor 8 and the chip resistor 2 of the first embodiment is only that the side leads of the chip resistor 8 are respectively arranged on different side walls and the chip resistor 6 omits the chip resistor 2. The fourth conductive pad 48. As shown in Figure 7, the side lead 64 of the chip resistor 8 is on one side wall, and the side lead (not drawn) electrically connected to the first conductive pad 42 is arranged on a side different from the side where the side lead 64 is located. on the other side of the wall.

Although the present invention has been disclosed above by the embodiments, it is not intended to limit the present invention. Relevant persons in the technical field to which the utility model belongs can make various changes and modifications without departing from the spirit and scope of the utility model. Therefore, the protection scope of the present utility model should be defined by the scope of the patent application.

Claims (10)

1. A chip resistor, characterized in that, comprising: a body having opposite first and second surfaces and a plurality of sidewalls between the first and second surfaces; a first terminal electrode and a second terminal electrode are separately arranged on the first surface; A first resistive layer is disposed on the first surface, the first resistive layer has a first resistive pattern with a long curved shape and two ends, wherein any end of the first resistive pattern is connected to the first end electrode, and the other terminal is connected to the second terminal electrode; a first protection layer covering the first resistance layer; A first conductive pad is arranged on the body for electrically connecting an external circuit board; A second conductive pad and a third conductive pad are separately arranged on the second surface; A second resistive layer is disposed on the second surface, the second resistive layer has a second resistive pattern with a long curved shape and two terminals, wherein any terminal of the second resistive pattern is connected to the second conductive pad, and the other terminal is connected to the third conductive pad; a second protective layer covering the second resistive layer; and A first side lead is disposed on one of the side walls, and the first side lead is electrically connected to the second terminal electrode and the second conductive pad. 2. The chip resistor as claimed in claim 1, further comprising: a second side guide disposed on one of the side walls, wherein the first conductive pad is disposed on the second surface, The second side guide is structurally connected to the first terminal electrode and the first conductive pad, and the second side guide is electrically connected to the first terminal electrode and the first conductive pad. 3. The chip resistor according to claim 2, wherein the first side guide and the second side guide are disposed on the same or different sidewalls. 4. The chip resistor according to claim 1, wherein the second protective layer covers the second conductive pad, covers or exposes a part of the second conductive pad between the second conductive pad and the third conductive pad. surface, and expose the third conductive pad. 5. The chip resistor according to claim 1, further comprising: a fourth conductive pad disposed on the second surface, the fourth conductive pad structurally connected to the exposed by the second protective layer The third conductive pad is electrically connected to the third conductive pad. 6. The chip resistor according to claim 5, wherein the second protection layer is interposed between the fourth conductive pad and the first side lead to electrically insulate the fourth conductive pad from the first side guide. 7. The chip resistor as claimed in claim 1, further comprising: a third protection layer covering the first side lead. 8 . The chip resistor according to claim 1 , wherein an impedance range of the chip resistor is 1G˜2G ohms. 9. The chip resistor as claimed in claim 1, wherein the first resistor layer and the second resistor layer are in a series relationship. 10. The chip resistor as claimed in claim 1, wherein the body is a ceramic substrate.