CN209119081U - Semiconductor devices and pad structure - Google Patents
Semiconductor devices and pad structure Download PDFInfo
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- CN209119081U CN209119081U CN201821858974.3U CN201821858974U CN209119081U CN 209119081 U CN209119081 U CN 209119081U CN 201821858974 U CN201821858974 U CN 201821858974U CN 209119081 U CN209119081 U CN 209119081U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000012360 testing method Methods 0.000 claims abstract description 109
- 229910000679 solder Inorganic materials 0.000 claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000010410 layer Substances 0.000 claims description 80
- 239000000463 material Substances 0.000 claims description 24
- 239000011241 protective layer Substances 0.000 claims description 12
- 238000005476 soldering Methods 0.000 claims description 11
- 240000007594 Oryza sativa Species 0.000 claims 1
- 235000007164 Oryza sativa Nutrition 0.000 claims 1
- 230000005611 electricity Effects 0.000 claims 1
- 235000009566 rice Nutrition 0.000 claims 1
- 239000000523 sample Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 11
- 238000002360 preparation method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 7
- 239000011810 insulating material Substances 0.000 description 6
- 238000003466 welding Methods 0.000 description 6
- 238000013461 design Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012774 insulation material Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 210000002421 cell wall Anatomy 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Present disclose provides a kind of pad structure and semiconductor devices, belong to technical field of semiconductors.The pad structure includes substrate, the first dielectric layer, groove, solder pad and testing weld pad, wherein the first dielectric layer is set in the substrate；Groove is set to the surface of first dielectric layer far from the substrate；Solder pad and testing weld pad one are set to the surface of first dielectric layer far from the substrate, another is set to the slot bottom of the groove.The pad structure and semiconductor devices can be improved the yield and stability of semiconductor devices.
Description
Technical field
This disclosure relates to technical field of semiconductors more particularly to a kind of semiconductor devices and pad structure.
Background technique
With the development of semiconductor technology, semiconductor devices in production and life using more and more extensive.Semiconductor
Device, such as chip etc. are frequently utilized that pad is realized and external connection.However, pad often connects with external connection line
Unstable situation is connect, the yield and stability of semiconductor devices are reduced.
Above- mentioned information disclosed in the background technology part are only used for reinforcing the understanding to the background of the disclosure, therefore it can
To include the information not constituted to the prior art known to persons of ordinary skill in the art.
Utility model content
The disclosure is designed to provide a kind of semiconductor devices and pad structure, and then solves pad to a certain extent
Unstable problem is connect with aerial lug.
To solve the above problems, the disclosure adopts the following technical scheme that
According to the first aspect of the disclosure, a kind of pad structure is provided, comprising:
Substrate；
First dielectric layer is set in the substrate；
Groove, set on the surface of first dielectric layer far from the substrate；
Solder pad and testing weld pad, one is set to the surface of first dielectric layer far from the substrate, another
Set on the slot bottom of the groove.
In a kind of exemplary embodiment of the disclosure, the solder pad is set to first dielectric layer far from described
The surface of substrate；The testing weld pad is set to the slot bottom of the groove.
In a kind of exemplary embodiment of the disclosure, the depth of the groove is 100 nanometers~1 micron.
In a kind of exemplary embodiment of the disclosure, the substrate includes wiring layer, and the wiring layer includes:
Wiring is tested, is connect with the testing weld pad.
In a kind of exemplary embodiment of the disclosure, the test wiring is exposed by the groove, and the test is welded
Disk connects the surface of the test wiring exposure.
In a kind of exemplary embodiment of the disclosure, the wiring layer further include:
Soldering wiring, the soldering wiring are connect with the solder pad.
In a kind of exemplary embodiment of the disclosure, the soldering wiring is by passing through leading for first dielectric layer
Electric column is connect with the solder pad.
In a kind of exemplary embodiment of the disclosure, the testing weld pad and the solder pad are mutually isolated.
In a kind of exemplary embodiment of the disclosure, connected between the testing weld pad and the solder pad by conductive
The connection of binding structure.
In a kind of exemplary embodiment of the disclosure, base described in surface distance of the testing weld pad far from the substrate
The distance at bottom is 100 nanometers smaller than the distance of substrate described in surface distance of the solder pad far from the substrate~1 micron.
In a kind of exemplary embodiment of the disclosure, the testing weld pad and the solder pad are identical material.
In a kind of exemplary embodiment of the disclosure, the testing weld pad is identical with the solder pad thickness.
In a kind of exemplary embodiment of the disclosure, the pad structure further include:
Protective layer, set on the side of first dielectric layer far from the substrate, and expose the testing weld pad and
The solder pad.
In terms of according to the third of the disclosure, a kind of semiconductor devices is provided, which includes above-mentioned pad
Structure.
The pad structure and semiconductor devices that the disclosure provides, solder pad and testing weld pad are separated from each other, therefore, even if
Testing weld pad is damaged when contacting with test probe, will not be impacted to solder pad, so that solder pad can
Effectively to connect with conductive connecting, yield and stability so that semiconductor devices are improved.
Detailed description of the invention
Its example embodiment is described in detail by referring to accompanying drawing, the above and other feature and advantage of the disclosure will become
It is more obvious.
Fig. 1 is the structural schematic diagram of pad in the prior art.
Fig. 2 is the structural schematic diagram of pad structure in an embodiment of the present disclosure.
Fig. 3 is the using renderings of pad structure in an embodiment of the present disclosure.
Fig. 4 is the structural schematic diagram of pad structure in an embodiment of the present disclosure.
Fig. 5 is the preparation method flow chart of pad structure in an embodiment of the present disclosure.
Fig. 6 is the schematic diagram of the groove region in an embodiment of the present disclosure on the first dielectric layer of exposure.
Fig. 7 is the schematic diagram for forming groove in an embodiment of the present disclosure on the first dielectric layer.
Fig. 8 is the preparation method flow chart of testing weld pad and solder pad in an embodiment of the present disclosure.
Fig. 9 is the schematic diagram that a conductive film layer is formed in an embodiment of the present disclosure.
Figure 10 is the schematic diagram for forming photoetching compound protective layer in an embodiment of the present disclosure on conductive film layer.
Figure 11 is the schematic diagram that testing weld pad and solder pad are formed in an embodiment of the present disclosure.
Figure 12 is the schematic diagram for forming photoetching compound protective layer in an embodiment of the present disclosure on conductive film layer.
Specific embodiment
Example embodiment is described more fully with reference to the drawings.However, example embodiment can be real in a variety of forms
It applies, and is not understood as limited to example set forth herein；On the contrary, these embodiments are provided so that the disclosure will more comprehensively and
Completely, and by the design of example embodiment comprehensively it is communicated to those skilled in the art.Described feature, structure or characteristic
It can be incorporated in any suitable manner in one or more embodiments.In the following description, many details are provided
Embodiment of the disclosure is fully understood to provide.
In the figure for clarity, may be exaggerated the thickness of region and layer.Identical appended drawing reference indicates identical in figure
Or similar structure, thus the detailed description that them will be omitted.
When certain structure is at other structures "upper", it is possible to refer to that certain structural integrity is formed in other structures, or refer to certain
Structure is " direct " to be arranged in other structures, or refers to that certain structure is arranged in other structures by the way that another structure is " indirect ".Term
"one", " one ", " described " to indicate there are one or more elements/component part/etc.；Term " comprising " and " having " is used
To indicate the open meaning being included and refer to that the element/component part/in addition to listing also may be present separately other than waiting
Outer element/component part/etc..Term " first " and " second " etc. are only used as label, are not the quantity limits to its object
System.
In the related technology, as shown in Figure 1, pad 001 on semiconductor devices, often both as testing weld pad so as to survey
Needle contact is soundd out, and is used to connect with conductive connecting 002 as solder pad.However, in semiconducter device testing, test
Probe is contacted with pad 001 is easy to cause pad to damage 004, such as generates and scratch or generate micronic dust.These pads damage 004
It is easy to cause to be not connected firmly between pad 001 and conductive connecting 002 and lean on, conductive connecting 002 (i.e. routing) is easy to fall off, drop
The low yield and stability of semiconductor devices.
A kind of pad structure is provided in disclosure embodiment, as shown in Fig. 2, the pad structure may include substrate 1,
One dielectric layer 4, groove 5, solder pad 3 and testing weld pad 2, wherein
First dielectric layer 4 is set in substrate 1；Groove 5 is set to the first surface of the dielectric layer 4 far from substrate 1；Welding weldering
One in disk 3 and testing weld pad 2 is set to the first surface of the dielectric layer 4 far from substrate 1, another is set to the slot bottom of groove 5.
The pad structure that the disclosure provides, solder pad 3 for connect with conductive connecting 002, testing weld pad 2 for
Test probe contact.Solder pad 3 and testing weld pad 2 are separated from each other, therefore, even if testing weld pad 2 connects with test probe 003
It is damaged, solder pad 3 will not be impacted when touching, allow solder pad 3 effective with conductive connecting 002
Connection, improves the yield and stability of semiconductor devices.
Each component of the pad structure provided with reference to the accompanying drawing disclosure embodiment is described in detail:
As shown in Fig. 2, substrate 1 may include the second dielectric layer 12 and wiring layer 11, wiring layer 11 can be set to second
Between dielectric layer 12 and the first dielectric layer 4.
The material of second dielectric layer 12 can be selected and be determined according to the design requirement of semiconductor devices, Ke Yiwei
Organic insulating material, or inorganic insulating material, or the mixing material for organic insulating material and inorganic insulating material.
For example, in one embodiment, the material of the second dielectric layer 12 can be one in silica, silicon nitride and amorphous silicon
Kind is a variety of.It is understood that the second dielectric layer 12 can be one layer of insulation material layer, or different exhausted of multilayer
Edge material layer forms.
As shown in Fig. 2, wiring layer 11 may include test wiring 111, test wiring 111 can be connect with testing weld pad 2,
Test for integrated circuit.
In an illustrative embodiments, test wiring 111 is spaced with testing weld pad 2 by the first dielectric layer 4, and the two
Between pass through conductive column realize connection.The conductive column in the preparation, can first form a via hole on groove 5, and the via hole is sudden and violent
Dew test wiring 111；Then when forming testing weld pad 2, the material for being used to form testing weld pad 2 can be filled in the via hole
Form conductive column.The conductive column not only may be implemented testing weld pad 2 and test the connection of wiring 111, but also may be implemented to survey
The support of test weld disk 2.
In another exemplary embodiment, as shown in Fig. 2, wiring 111 is tested in the exposure of groove 5, and testing weld pad 2 connects
Test the surface of the exposure of wiring 111.It is contacted in this way, groove 5 may be implemented with the direct of wiring 111 is tested.
As shown in figure 4, wiring layer 11 can also include soldering wiring 112, soldering wiring 112 can connect with solder pad 3
It connects, is connect for semiconductor devices with external circuit.Orthographic projection of the solder pad 3 on wiring layer 11 can be with soldering wiring
112 is least partially overlapped, and can pass through the conductive column across the first dielectric layer 4 between solder pad 3 and soldering wiring 112
31 connections.
The conductive column 31 in the preparation, first can form a via hole in the first dielectric layer 4, via hole exposure welding is matched
Line 112；Then when forming solder pad 3, the material for being used to form solder pad 3, which can be filled in the via hole, forms conduction
Column 31.The connection of solder pad 3 Yu soldering wiring 112 not only may be implemented in the conductive column 31, but also may be implemented to weld welding
The support of disk 2 effectively improves the support of solder pad 3 when the bonding of conductive connecting 002 or conductive connecting 002 are welded
Power improves the yield of encapsulating products.
The material of first dielectric layer 4 can be selected and be determined according to the design requirement of semiconductor devices, Ke Yiwei
Organic insulating material, or inorganic insulating material.For example, in one embodiment, the material of the first dielectric layer 4
It can be one of silica, silicon nitride and amorphous silicon or a variety of.It is understood that the first dielectric layer 4 can be one
Layer insulation material layer, or the different insulation material layer of multilayer is laminated.
The depth of groove 5 can be determined according to the design requirement or structure of semiconductor devices.Groove 5 can run through
Or not through the first dielectric layer 4.
In an illustrative embodiments, the depth of groove 5 can be 100 nanometers~1 micron.In this way, the side of the groove 5
Effective blocking to test probe 003 may be implemented in wall.It is understood that testing weld pad 2 and solder pad 3 are connected by conductive
The connection of binding structure, then the conduction connecting structure can cover the side wall of groove 5 between testing weld pad 2 and solder pad 3
Part, at this point, testing weld pad 2 and solder pad 3 are stepped on the whole；The conduction connecting structure may be implemented to test probe
003 blocking scratches into the region of solder pad 3 to prevent test probe 003 when test, reduces the damage of solder pad 3.
In an illustrative embodiments, as shown in Fig. 2, solder pad 3 can be set to the first dielectric layer 4 far from substrate
1 surface；Testing weld pad 2 can be set to the slot bottom of groove 5.In this way, compared to testing weld pad 2, the surface distance of solder pad 3
Substrate 1 is farther, i.e. the surface that protrudes from testing weld pad 2 of solder pad 3.As shown in figure 3, when test probe 003 is moved to groove 5
Edge when, by the blocking of the cell wall that will receive groove 5 or the device being attached on cell wall, so that test probe 003
It can be moved in groove 5.In this way, can further decrease test probe 003 is strayed into welding weldering in 2 surface offsets of testing weld pad
A possibility that disk 3, reduces the damage of solder pad 3, guarantees the structural integrity of solder pad 3.In an illustrative embodiments
In, the distance of surface distance substrate 1 of the testing weld pad 2 far from substrate 1, the surface distance substrate than solder pad 3 far from substrate 1
1 distance is 100 nanometers small~and 1 micron.
In another exemplary embodiment, solder pad 3 can be set to the slot bottom of groove 5；Testing weld pad 2 can be set to
First surface of the dielectric layer 4 far from substrate 1.
The shape of testing weld pad 2 can for rectangular, rectangle, circle, ellipse, regular hexagon or other can pass through structure
The shape of figure technique preparation is contacted with other devices not being constituted negative effect and can satisfy with the effective of test probe 003
Subject to.The size (surface size and thickness) of testing weld pad 2 can be determined according to the design requirement of semiconductor devices, with energy
Enough test probes 003 that effectively accommodates are completed subject to test.The disclosure does not do special limit to shape, the size etc. of testing weld pad 2
It is fixed.
The material of testing weld pad 2 is conductive material, can be metal material, metal oxide materials or other materials.
It is understood that testing weld pad 2 can be made of layer of conductive material, can also by the different conductive material stacking of multilayer and
At.For example, the material of testing weld pad 2 can be one of copper, aluminium, tungsten, titanium, gold, silver or the alloy of above-mentioned material.
Shape, size and the material of solder pad 3 can be identical as testing weld pad 2, can not also be identical, and the disclosure is to this
Special restriction is not done.
In an illustrative embodiments, testing weld pad 2 and solder pad 3 can use identical material, in this way, test
Pad 2 and solder pad 3 are convenient for preparing in same technique.Especially, if testing weld pad 2 and solder pad 3 are connected using conductive
The connection of binding structure, and three uses identical material, then testing weld pad 2, solder pad 3 and conduction connecting structure are convenient for while being made
It is standby to come out.
In an illustrative embodiments, testing weld pad 2 and 3 thickness of solder pad can be identical, so, it is ensured that weldering
Connect the surface that pad 3 protrudes from testing weld pad 2.When especially testing weld pad 2 is identical with 3 material of solder pad, the two can lead to
Same conductive film layer preparation is crossed, convenient for simplifying the preparation process of pad structure.
As shown in Fig. 2, the pad structure can also include protective layer 7, which be can be set in the first dielectric layer
4 sides far from substrate 1, the opening which forms expose testing weld pad 2 and solder pad 3, and protective layer 7
Upper surface protrudes from the upper surface of testing weld pad 2 and solder pad 3.Protective layer 7 can be made of one layer of protection materials, can also be with
It is laminated by the different protection materials of multilayer.For example, which can be polyimides.
The disclosure additionally provides a kind of preparation method of pad structure, as shown in figure 5, the preparation method packet of the pad structure
It includes:
Step S110 provides a substrate 1；
Step S120 forms the first dielectric layer 4 in substrate 1；
Step S130 forms groove 5 in the first dielectric layer 4；
Step S140 forms solder pad 3 and testing weld pad 2, and one in solder pad 3 and testing weld pad 2 is set to the
One surface of the dielectric layer 4 far from substrate 1, another is set to the slot bottom of groove 5.
Wherein, in the step s 120, the can be formed in substrate 1 by the methods of chemical vapor deposition, atomic layer deposition
One dielectric layer 4.
In step S130, groove 5 can be formed by masking process-photoetching process method.For example, in an example
In property embodiment, masking process-photoetching process may include:
Step S210 forms photoresist layer 61 far from the surface of substrate 1 in the first dielectric layer 4；
Step S220 is exposed by corresponding mask plate, and the pattern of mask plate is transferred to photoresist layer 61, is such as schemed
Shown in 6；
Step S230, by development, so that photoresist layer 61 exposes the region of groove 5 to be opened up；
Step S240 forms groove 5 by etching；
Step S250 removes photoresist layer 61, forms structure shown in Fig. 7.
In an illustrative embodiments, solder pad 3 is different with 2 material of testing weld pad or thickness is different, then in step
In rapid S140, then solder pad 3 and testing weld pad 2 can be respectively formed.
In another exemplary embodiment, solder pad 3 is identical with 2 material of testing weld pad and thickness is identical, then can be with
It is formed simultaneously solder pad 3 and testing weld pad 2.Solder pad can be formed by the methods of physical vapour deposition (PVD), plating, vapor deposition
3 and testing weld pad 2.For example, as shown in figure 8, solder pad 3 and testing weld pad 2 can be formed by the following method:
Step S310 forms a conductive film layer, and the slot bottom and the first dielectric layer 4 that conductive film layer covers groove 5 are far from base
The surface at bottom 1, as shown in Figure 9；
Step S320 forms a photoresist layer far from the surface of substrate 1 in conductive film layer 62；
Step S330 is exposed on photoresist layer by masking process, and the pattern of mask plate is transferred to photoresist layer
On；
Step S340, development, so that photoresist layer forms the pattern of the pattern and solder pad 3 with testing weld pad 2
Photoetching compound protective layer 63, as shown in Figure 10；
Step S350, by etching, removal is not photo-etched the conductive film layer 62 of the protection of compound protective layer 63, and etching off is except sudden and violent at once
The conductive film layer 62 of dew；
Step S360 removes photoetching compound protective layer 63, obtains remaining conductive film layer 62, i.e. testing weld pad 2 and welding weldering
Disk 3, as shown in figure 11.
It is understood that if connected between solder pad 3 and testing weld pad 2 by conduction connecting structure, and it is conductive
The material of connection structure is identical as solder pad 3 and testing weld pad 2, then the conduction connecting structure can also with solder pad 3 and
Testing weld pad 2 is prepared simultaneously.In the preparation, as shown in Fig. 9~Figure 11, in step S330, it can choose mask plate appropriate,
So that the pattern of the conduction connecting structure between testing weld pad 2 and solder pad 3 and testing weld pad 2 and solder pad 3 together by
It is transferred on photoresist layer.In this way, being formed by photoetching compound protective layer 63 with testing weld pad 2, welding weldering in step S340
The pattern of disk 3 and conduction connecting structure.In step S360, remaining conductive film layer 62 includes testing weld pad 2, solder pad 3
And conduction connecting structure.
If be isolated between solder pad 3 and testing weld pad 2, suitable mask plate can be selected in step S330,
So that the pattern of photoetching compound protective layer 63 is as shown in figure 12 in step S340, expose between solder pad 3 and testing weld pad 2
Area of isolation.
It should be noted that although describing each step of method in the disclosure in the accompanying drawings with particular order,
This does not require that or implies must execute these steps in this particular order, or have to carry out step shown in whole
Just it is able to achieve desired result.Additional or alternative, it is convenient to omit multiple steps are merged into a step and held by certain steps
Row, and/or a step is decomposed into execution of multiple steps etc., it is regarded as a part of this disclosure.
The disclosure also provides a kind of semiconductor devices, including any one is welded described in above-mentioned pad structure embodiment
Dish structure.The semiconductor devices can be memory, processor or other semiconductor devices.
In the embodiment of pad structure and above-mentioned pad structure that the semiconductor devices of disclosure embodiment uses
Pad structure is identical, and therefore, beneficial effect having the same, details are not described herein.
It should be appreciated that the disclosure is not limited in its application to the detailed construction and arrangement of the component of this specification proposition
Mode.The disclosure can have other embodiments, and can realize and execute in many ways.Aforesaid deformation form and
Modification is fallen within the scope of this disclosure.It should be appreciated that this disclosure and the disclosure of restriction extend in text
And/or it is mentioned in attached drawing or all alternative combinations of two or more apparent independent features.It is all these different
Combination constitutes multiple alternative aspects of the disclosure.Embodiment described in this specification illustrates to become known for realizing the disclosure
Best mode, and those skilled in the art will be enable using the disclosure.
Claims (14)
1. a kind of pad structure characterized by comprising
Substrate；
First dielectric layer is set in the substrate；
Groove, set on the surface of first dielectric layer far from the substrate；
Solder pad and testing weld pad, one is set to the surface of first dielectric layer far from the substrate, another is set to
The slot bottom of the groove.
2. pad structure according to claim 1, which is characterized in that the solder pad is set to first dielectric layer
Surface far from the substrate；The testing weld pad is set to the slot bottom of the groove.
3. pad structure according to claim 1, which is characterized in that the depth of the groove is 100 nanometers~1 micron.
4. pad structure according to claim 2, which is characterized in that the substrate includes wiring layer, the wiring layer packet
It includes:
Wiring is tested, is connect with the testing weld pad.
5. pad structure according to claim 4, which is characterized in that the test wiring is exposed by the groove, and institute
State the surface that testing weld pad connects the test wiring exposure.
6. pad structure according to claim 4, which is characterized in that the wiring layer further include:
Soldering wiring, the soldering wiring are connect with the solder pad.
7. pad structure according to claim 6, which is characterized in that the soldering wiring is situated between by passing through first electricity
The conductive column of matter layer is connect with the solder pad.
8. pad structure according to claim 1, which is characterized in that the testing weld pad and the solder pad mutually every
From.
9. pad structure according to claim 1, which is characterized in that lead between the testing weld pad and the solder pad
Cross conduction connecting structure connection.
10. pad structure according to claim 1, which is characterized in that surface of the testing weld pad far from the substrate
Distance apart from the substrate is smaller by 100 than the distance of substrate described in surface distance of the solder pad far from the substrate to receive
Rice~1 micron.
11. pad structure according to claim 1, which is characterized in that the testing weld pad and the solder pad are phase
Same material.
12. pad structure according to claim 1, which is characterized in that the testing weld pad and the solder pad thickness
It is identical.
13. pad structure according to claim 1, which is characterized in that the pad structure further include:
Protective layer set on the side of first dielectric layer far from the substrate, and exposes the testing weld pad and described
Solder pad.
14. a kind of semiconductor devices, which is characterized in that including the described in any item pad structures of claim 1~13.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821858974.3U CN209119081U (en) | 2018-11-12 | 2018-11-12 | Semiconductor devices and pad structure |
| PCT/CN2019/117394 WO2020098623A1 (en) | 2018-11-12 | 2019-11-12 | Semiconductor device, pad structure and fabrication method thereof |
| US17/231,906 US20210233822A1 (en) | 2018-11-12 | 2021-04-15 | Semiconductor device, pad structure and fabrication method thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111180407A (en) * | 2018-11-12 | 2020-05-19 | 长鑫存储技术有限公司 | Semiconductor device, bonding pad structure and preparation method thereof |
| WO2020098623A1 (en) * | 2018-11-12 | 2020-05-22 | Changxin Memory Technologies, Inc. | Semiconductor device, pad structure and fabrication method thereof |
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2018
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111180407A (en) * | 2018-11-12 | 2020-05-19 | 长鑫存储技术有限公司 | Semiconductor device, bonding pad structure and preparation method thereof |
| WO2020098623A1 (en) * | 2018-11-12 | 2020-05-22 | Changxin Memory Technologies, Inc. | Semiconductor device, pad structure and fabrication method thereof |
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