CN209105035U - DC-DC step-down isolation circuit - Google Patents

Abstract

The utility model relates to a DC-DC step-down isolation circuit, comprising a PWM signal generation circuit, a single-capacitor half-bridge step-down isolation conversion circuit, a full-bridge rectifier circuit and a voltage-stabilized output circuit, wherein an input end of the PWM signal generation circuit is connected to The voltage source is connected, the output end of the PWM signal generating circuit is connected with the input end of the full-bridge rectifier circuit through the single-capacitor half-bridge step-down isolation conversion circuit, and the output end of the full-bridge rectifier circuit is connected with the input end of the voltage-stabilizing output circuit, The output end of the regulated output circuit is the output end of the isolation circuit. The utility model forms two PWM signals with opposite signals through dual-channel inverters, the circuit structure is simple, and the power supply adopts a conversion circuit of single-capacitor half-bridge topology, which has high working efficiency.

Description

A DC-DC step-down isolation circuit

technical field

The utility model relates to the technical field of power supplies, in particular to a DC-DC step-down isolation circuit.

Background technique

DC-DC (Direct Current-Direct Current, DC-DC) step-down isolation circuit converts the input high DC voltage (such as 12V) into an isolated and stable low DC voltage (such as 5V) output, the traditional DC-DC drop The voltage isolation circuit uses a switching power supply controller to control the driving pulse width of the power switch, requires an external power switch device to realize a half-bridge topology circuit, and requires an isolated output feedback circuit to achieve a stable output voltage, the number of components is large, higher cost.

Utility model content

The purpose of the utility model is to provide a DC-DC step-down isolation circuit with simple structure, stable voltage output and high working efficiency.

To achieve the above object, the utility model adopts the following technical solutions:

A DC-DC step-down isolation circuit includes a PWM signal generation circuit, a single-capacitor half-bridge step-down isolation conversion circuit, a full-bridge rectifier circuit and a voltage-stabilized output circuit, wherein an input end of the PWM signal generation circuit is connected to a voltage source, The output end of the PWM signal generating circuit is connected with the input end of the full-bridge rectifier circuit through the single-capacitor half-bridge step-down isolation conversion circuit, and the output end of the full-bridge rectifier circuit is connected with the input end of the voltage-stabilizing output circuit. The output end of the output circuit is the output end of the isolation circuit.

As a further improvement of the above technical solution:

The PWM signal generating circuit includes an LDO chip U1, a dual-channel inverter U2, a filter capacitor C1, a filter capacitor C2 and a resistor R1. The input end of the LDO chip U1 is connected to a voltage source, and its output end is connected to the filter capacitor C1. The power supply terminal of the dual-channel inverter U2 is connected. The first input terminal of the dual-channel inverter U2 is connected to its first output terminal through the resistor R1, and the first input terminal is grounded through the capacitor C6. The dual-channel inverter U2 The second input terminal of the inverter U2 is connected to its first output terminal, the first output terminal and the second output terminal of the dual-channel inverter U2 are connected to the input terminal of the single-capacitor half-bridge step-down isolation conversion circuit, and the filter The capacitor C2 is connected in parallel with the filter capacitor C1.

The single-capacitor half-bridge step-down isolation conversion circuit is composed of a control chip U4, a transformer T1 and a peripheral circuit. The power supply end of the control chip U4 is connected to the power supply, and the power supply end is grounded through the capacitor C3. The control chip U4 The output end of the transformer T1 is connected to the input end of the transformer T1, and the output end of the transformer T1 is connected to the input end of the full-bridge rectifier circuit.

The full-bridge rectifier circuit includes rectifier diodes D1, D2, D3, and D4, an energy storage filter capacitor C5, and the transformer T1 includes secondary windings n2 and n3. The same name terminal is connected in parallel with the anode of the rectifier diode D1 and the cathode of the rectifier diode D3. The synonym terminal of the secondary winding n2 is connected in parallel with the synonym terminal of the secondary winding n3 and then connected to the anode of the rectifier diode D2 and the cathode of the rectifier diode D4. The cathode of the rectifier diode D1 and the cathode of the rectifier diode D2 are connected in parallel as the output positive terminal of the rectifier circuit, the anodes of the rectifier diodes D3 and D4 are connected in parallel as the output isolation ground of the rectifier circuit, and the energy storage filter capacitor C5 is connected in parallel after rectification. The output positive terminal is connected to both ends of the isolated ground.

The voltage regulator output circuit includes an LDO chip U3, feedback resistors R3, R4, a filter capacitor C7 and a filter capacitor C8; the input end of the LDO chip U3 is connected to the positive output terminal of the full-bridge rectifier circuit, and the output end of the LDO chip U3 The voltage dividing resistor R3 is connected to its ground terminal, the ground terminal is grounded through the resistor R4, the capacitor C8 is connected in parallel with both ends of the resistor R4, one end of the capacitor C7 is connected to the output terminal of the LDO chip U3, and the other end of the capacitor C7 is connected. ground.

The model of the LDO chip U1 is NCP1117ST33T3G; the model of the dual-channel inverter U2 is NLV27WZ14DFT2G.

The model of the control chip U4 is DRV8872DDARQ1.

The model of the LDO chip U3 is LD1117DTTR.

It can be seen from the above technical solutions that the DC-DC step-down isolation circuit of the present invention has a simple circuit topology, and adopts a dual-channel inverter and an R and C configuration to output a high-frequency PWM signal to control the switch of the full-bridge converter. The circuit structure is simple and easy to implement. The utility model adopts the circuit topology of single-capacitor half-bridge type, and the output power is relatively large, so that the circuit topology has higher working efficiency.

Description of drawings

Figure 1 is a circuit diagram of the present utility model.

Detailed ways

Below in conjunction with accompanying drawing, the utility model is further described:

As shown in FIG. 1 , the DC-DC step-down isolation circuit of this embodiment includes a PWM signal generation circuit, a single-capacitor half-bridge step-down isolation conversion circuit, a full-bridge rectifier circuit, and a voltage-stabilized output circuit. The input of the PWM signal generation circuit The terminal is connected to the voltage source, the output terminal of the PWM signal generating circuit is connected to the input terminal of the full-bridge rectifier circuit through the single-capacitor half-bridge step-down isolation conversion circuit, and the output terminal of the full-bridge rectifier circuit is connected to the input terminal of the voltage-stabilizing output circuit. The output end of the regulated output circuit is the output end of the isolation circuit.

The 12V DC power supply goes through the PWM signal generation circuit, the half-bridge step-down isolation conversion circuit, the full-bridge rectifier circuit, and the voltage regulator circuit to output a stable 5V isolation voltage.

The PWM signal generating circuit includes LDO chip U1 with model NCP1117ST33T3G, dual-channel inverter U2 with model NLV27WZ14DFT2G, filter capacitor C1, filter capacitor C2 and resistor R1. The input end of LDO chip U1 is connected to the voltage source, and its output end is The filter capacitor C1 is connected to the power supply terminal of the dual-channel inverter U2, the first input terminal of the dual-channel inverter U2 is connected to its first output terminal through the resistor R1, and the first input terminal is grounded through the capacitor C6. The second input terminal of the inverter U2 is connected to its first output terminal, so that the second output terminal of the dual-channel inverter U2 outputs a square wave with an opposite waveform to the first output terminal. The first output end and the second output end of the dual-channel inverter U2 are connected to the input end of the single-capacitor half-bridge step-down isolation conversion circuit, and the filter capacitor C2 is connected in parallel with the filter capacitor C1. One end of the input 12V voltage is connected to the input end of the LDO chip U1. The LDO chip U1 outputs a stable 3.3V voltage through the filter capacitor C1. The filter capacitor C1 outputs a stable 3.3V voltage. Through the configuration of different parameters of the resistor R1 and the capacitor C6, the first output terminal of the dual-channel inverter U2 outputs square waves of different frequencies. The 6-pin of the dual-channel inverter U2 is connected to the 3-pin of U2.

The single-capacitor half-bridge step-down isolation conversion circuit is composed of a control chip U4, a transformer T1 and peripheral circuits with a model of DRV8872DDARQ1. The power supply end of the control chip U4 is connected to the power supply, and the power supply end is grounded through the capacitor C3, and the output of the control chip U4 is The terminal is connected to the input terminal of the transformer T1, and the output terminal of the transformer T1 is connected to the input terminal of the full-bridge rectifier circuit. Short-circuit pins 2 and 3 on the primary side of transformer T1 to increase the turns ratio of the primary side of the transformer, short-circuit pins 5 and 7 on the secondary side of transformer T1, and short-circuit pins 6 and 8 on the secondary side of the transformer to reduce the turns ratio of the secondary side of the transformer.

The full-bridge rectifier circuit includes rectifier diodes D1, D2, D3, D4, energy storage filter capacitor C5, and the transformer T1 includes secondary windings n2 and n3. The same-named terminal of the secondary winding n2 is connected in parallel with the same-named terminal of the secondary winding n3 and then connected to the rectifier. The anode of the diode D1 and the cathode of the rectifier diode D3 are connected, the synonym end of the secondary winding n2 is connected in parallel with the synonym end of the secondary winding n3, and then connected to the anode of the rectifier diode D2 and the cathode of the rectifier diode D4, and the cathode of the rectifier diode D1 Parallel with the cathode of the rectifier diode D2 is the output positive terminal of the rectifier circuit, the anodes of the rectifier diodes D3 and D4 are connected in parallel to the output isolation ground of the rectifier circuit, and the energy storage filter capacitor C5 is connected in parallel between the output positive terminal and the isolation ground after rectification. .

The voltage-stabilizing output circuit includes LDO chip U3 with model LD1117DTTR, feedback resistors R3, R4, filter capacitor C7 and filter capacitor C8; the input end of LDO chip U3 is connected to the output positive end of the full-bridge rectifier circuit, and the output end of LDO chip U3 is divided into The piezoresistor R3 is connected to its ground terminal, the ground terminal is grounded through the resistor R4, the capacitor C8 is connected in parallel with both ends of the resistor R4, one end of the capacitor C7 is connected to the output terminal of the LDO chip U3, and the other end of the capacitor C7 is grounded.

The utility model forms two PWM signals with opposite signals through dual-channel inverters, the circuit structure is simple, and the power supply adopts a conversion circuit of single-capacitor half-bridge topology, which has high working efficiency.

The above-mentioned embodiments are only to describe the preferred embodiments of the present invention, and do not limit the scope of the present invention. On the premise of not departing from the design spirit of the present invention, those of ordinary skill in the art can understand the technical solutions of the present invention. Various modifications and improvements made shall fall within the protection scope determined by the claims of the present utility model.

Claims (8)

1. a kind of DC-DC is depressured isolation circuit, it is characterised in that: including pwm signal occur circuit, the decompression of single capacitor half-bridge every From translation circuit, full bridge rectifier and voltage-stabilizing output circuit, the input terminal of circuit occurs for the pwm signal and voltage source connects It connects, the output end of circuit occurs for pwm signal through the input terminal of single capacitor half-bridge decompression isolated variable circuit and full bridge rectifier The input terminal of connection, the output end of the full bridge rectifier and voltage-stabilizing output circuit connects, the voltage-stabilizing output circuit it is defeated Outlet is the output end of isolation circuit.

2. DC-DC according to claim 1 is depressured isolation circuit, it is characterised in that: the pwm signal occurs circuit and includes LDO chip U1, binary channels phase inverter U2, filter capacitor C1, filter capacitor C2 and resistance R1, the input terminal of the LDO chip U1 It is connect with voltage source, output end is connect through filter capacitor C1 with the feeder ear of binary channels phase inverter U2, the binary channels reverse phase The first input end of device U2 is connect through resistance R1 with its first output end, and the first input end and is grounded through capacitor C6, described The second input terminal of binary channels phase inverter U2 is connect with its first output end, the first output end and second of binary channels phase inverter U2 Output end is connect with the input terminal of single capacitor half-bridge decompression isolated variable circuit, and the filter capacitor C2 and filter capacitor C1 are simultaneously Connection.

3. DC-DC according to claim 1 is depressured isolation circuit, it is characterised in that: the single capacitor half-bridge decompression isolation Translation circuit is made of control chip U4, transformer T1 and peripheral circuit, it is described control chip U4 feeder ear connect to power supply, And the feeder ear and be grounded through capacitor C3, the output end of the control chip U4 is connect with the input terminal of transformer T1, transformer The output end of T1 and the input terminal of full bridge rectifier connect.

4. DC-DC according to claim 3 is depressured isolation circuit, it is characterised in that: the full bridge rectifier includes whole Diode D1, D2, D3, D4 are flowed, energy storage filter capacitor C5, the transformer T1 include vice-side winding n2, n3, the vice-side winding Connect after the Same Name of Ends of n2 is in parallel with the Same Name of Ends of vice-side winding n3 with the cathode of the anode of rectifier diode D1, rectifier diode D3 It connects, the different name end and vice-side winding n3 different name end of vice-side winding n2 and anode, the rectifier diode of Lian Houyu rectifier diode D2 The cathode of D4 connects, and the output for rectification circuit in parallel with the cathode of rectifier diode D2 of the cathode of the rectifier diode D1 is just Extremely, the anode parallel connection of rectifier diode D3, D4 be rectification circuit output isolator, the energy storage filter capacitor C5 is connected in parallel on Output cathode end and the both ends isolator connect after rectification.

5. DC-DC according to claim 1 is depressured isolation circuit, it is characterised in that: the voltage-stabilizing output circuit includes LDO Chip U3, feedback resistance R3, R4, filter capacitor C7 and filter capacitor C8；The input termination full-bridge rectification electricity of the LDO chip U3 The output end at road output cathode end, the LDO chip U3 is connect through divider resistance R3 with its ground terminal, which passes through resistance R4 ground connection, the capacitor C8 are connected in parallel on the both ends of resistance R4, and one end of the capacitor C7 is connect with the output end of LDO chip U3, The other end of capacitor C7 is grounded.

6. DC-DC according to claim 2 is depressured isolation circuit, it is characterised in that: the model of the LDO chip U1 NCP1117ST33T3G；The model NLV27WZ14DFT2G of binary channels phase inverter U2.

7. DC-DC according to claim 3 is depressured isolation circuit, it is characterised in that: the model of control chip U4 DRV8872DDARQ1。

8. DC-DC according to claim 5 is depressured isolation circuit, it is characterised in that: the model of the LDO chip U3 LD1117DTTR。