CN209045554U - Semiconductor structure and memory construction - Google Patents
Semiconductor structure and memory construction Download PDFInfo
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Abstract
Description
技术领域technical field
本实用新型属于集成电路制造技术领域，特别是涉及一种半导体结构及存储器结构。The utility model belongs to the technical field of integrated circuit manufacturing, in particular to a semiconductor structure and a memory structure.
背景技术Background technique
随着工艺的发展，半导体器件的集成度越来越高，半导体器件的尺寸也越来越小，制程工艺越来越复杂，成本也越来越高。同时，在半导体器件的制备过程中，若特征形状与目标值有误差(即特征形状不能够精确对准)，则会对半导体器件的性能将产生明显不利的影响。譬如，在现有的存储器结构的制备工艺中，整个工艺流程步骤较多，成本较高，且在形成位线接触孔时，现有的光刻曝光工艺很难实现精确对准，从而使得制备得到的存储器结构的可靠性及稳定性较低。With the development of technology, the integration degree of semiconductor devices is getting higher and higher, the size of semiconductor devices is getting smaller and smaller, the process technology is getting more and more complicated, and the cost is getting higher and higher. Meanwhile, during the fabrication of the semiconductor device, if there is an error between the feature shape and the target value (ie, the feature shape cannot be accurately aligned), the performance of the semiconductor device will be significantly adversely affected. For example, in the existing manufacturing process of the memory structure, the entire process has many steps and high cost, and when forming the bit line contact hole, the existing photolithography exposure process is difficult to achieve precise alignment, which makes the preparation process difficult. The resulting memory structure has low reliability and stability.
实用新型内容Utility model content
鉴于以上所述现有技术的缺点，本实用新型的目的在于提供一种半导体结构及存储器结构，用于解决现有技术中存储器结构的制备工艺流程步骤较多、成本较高、位线接触孔难以实现精确对准，使得得到的存储器结构的可靠性及稳定性较差等问题。In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor structure and a memory structure, which are used to solve the problems in the prior art that the preparation process of the memory structure has many steps, high cost, and bit line contact holes. It is difficult to achieve precise alignment, resulting in problems such as poor reliability and stability of the resulting memory structure.
为实现上述目的及其他相关目的，本实用新型提供一种半导体结构，所述半导体结构包括：In order to achieve the above purpose and other related purposes, the present invention provides a semiconductor structure, the semiconductor structure includes:
半导体基底；semiconductor substrate;
垫层结构，位于所述半导体基底的表面；a pad structure, located on the surface of the semiconductor substrate;
浅沟槽隔离结构，位于所述半导体基底及所述垫层结构内，以于所述半导体基底内隔离出若干个间隔排布的有源区；a shallow trench isolation structure located in the semiconductor substrate and the pad structure to isolate a plurality of spaced active regions in the semiconductor substrate;
硬掩膜层，位于所述垫层结构的表面；a hard mask layer, located on the surface of the pad structure;
底部抗反射涂层，位于所述硬掩膜层的表面；a bottom anti-reflective coating on the surface of the hard mask layer;
填充层，位于所述底部抗反射涂层内，所述填充层定义出需要形成的位线接触的位置及形状；及a fill layer within the bottom anti-reflective coating, the fill layer defining the location and shape of the bit line contacts to be formed; and
侧墙结构，位于所述底部抗反射涂层内，且位于所述填充层的外侧，所述侧墙结构定义出需要形成的埋入式栅极字线的位置及形状；其中，A spacer structure is located in the bottom anti-reflection coating and outside the filling layer, and the spacer structure defines the position and shape of the buried gate word line to be formed; wherein,
于相同的刻蚀条件下，所述填充层的去除速率小于所述底部抗反射层的去除速率及所述侧墙结构的去除速率。Under the same etching conditions, the removal rate of the filling layer is lower than the removal rate of the bottom anti-reflection layer and the removal rate of the spacer structure.
作为本实用新型的一种优选方案，所述有源区内还形成有深阱区域。As a preferred solution of the present invention, a deep well region is also formed in the active region.
作为本实用新型的一种优选方案，所述垫层结构包括：As a preferred solution of the present utility model, the cushion structure includes:
垫氧化层，位于所述半导体基底的表面；a pad oxide layer, located on the surface of the semiconductor substrate;
垫氮化层，位于所述垫氧化层的表面。A pad nitride layer is located on the surface of the pad oxide layer.
作为本实用新型的一种优选方案，所述硬掩膜层包括：As a preferred solution of the present invention, the hard mask layer includes:
第一硬掩膜层，位于所述垫层结构的表面；及a first hard mask layer on the surface of the pad structure; and
第二硬掩膜层，位于所述第一硬掩膜层的表面。The second hard mask layer is located on the surface of the first hard mask layer.
本实用新型还提供一种存储器结构，所述存储器结构包括：The utility model also provides a memory structure, the memory structure includes:
半导体基底，所述半导体基底内形成有浅沟槽隔离结构，所述浅沟槽隔离结构在所述半导体基底内隔离出若干个间隔排布的有源区；a semiconductor substrate, wherein a shallow trench isolation structure is formed in the semiconductor substrate, and the shallow trench isolation structure isolates a plurality of spaced active regions in the semiconductor substrate;
若干个间隔排布的埋入式栅极字线，位于所述有源区内，且所述埋入式栅极字线的上表面低于所述半导体基底的上表面；a plurality of buried gate word lines arranged at intervals are located in the active region, and the upper surface of the buried gate word lines is lower than the upper surface of the semiconductor substrate;
位线接触，位于所述半导体基底上；及bit line contacts on the semiconductor substrate; and
介质层，位于所述埋入式栅极字线的表面，且填满所述位线接触之间的间隙。The dielectric layer is located on the surface of the buried gate word line and fills the gap between the bit line contacts.
作为本实用新型的一种优选方案，所述有源区内还形成有深阱区域。As a preferred solution of the present invention, a deep well region is also formed in the active region.
作为本实用新型的一种优选方案，所述存储器结构还包括垫层结构，所述垫层结构位于所述埋入式栅极字线及所述位线接触之间的所述半导体基底的表面。As a preferred solution of the present invention, the memory structure further includes a pad layer structure, and the pad layer structure is located on the surface of the semiconductor substrate between the buried gate word line and the bit line contact .
作为本实用新型的一种优选方案，所述垫层结构包括：As a preferred solution of the present utility model, the cushion structure includes:
垫氧化层，位于所述半导体基底的表面；及a pad oxide layer on the surface of the semiconductor substrate; and
垫氮化层，位于所述垫氧化层的表面。A pad nitride layer is located on the surface of the pad oxide layer.
作为本实用新型的一种优选方案，所述位线接触的底部陷入于所述半导体基底内。As a preferred solution of the present invention, the bottom of the bit line contact is recessed into the semiconductor substrate.
作为本实用新型的一种优选方案，所述埋入式栅极字线包括：As a preferred solution of the present invention, the buried gate word line includes:
栅极导电层，位于所述有源区内，所述栅极导电层的上表面低于所述半导体基底的上表面；及a gate conductive layer, located in the active region, the upper surface of the gate conductive layer is lower than the upper surface of the semiconductor substrate; and
栅极氧化层，位于所述有源区内，且位于所述栅极导电层与所述半导体基底之间。A gate oxide layer is located in the active region and between the gate conductive layer and the semiconductor substrate.
如上所述，本实用新型的半导体结构及存储器结构，具有以下有益效果：As mentioned above, the semiconductor structure and the memory structure of the present invention have the following beneficial effects:
本实用新型的半导体结构，在形成侧墙结构及填充层时即定义出埋入式栅极字线及位线接触的位置及形状，在基于所述半导体结构制备埋入式栅极字线及位线接触时，不需要额外的光刻工艺来定义位线接触孔，从而可以避免光刻曝光偏移，确保位线接触的精确对准；同时，半导体结构的制备方法简单，工艺步骤简洁，节约材料成本和工艺成本；In the semiconductor structure of the present invention, when the sidewall structure and the filling layer are formed, the position and shape of the contact of the buried gate word line and the bit line are defined. When the bit line is in contact, no additional photolithography process is required to define the bit line contact hole, so that the photolithography exposure offset can be avoided, and the precise alignment of the bit line contact can be ensured; at the same time, the preparation method of the semiconductor structure is simple, and the process steps are concise, Save material cost and process cost;
本实用新型的存储器结构，通过形成侧墙结构及填充层分别定义出埋入式栅极字线及位线接触的位置及形状，在形成位线接触孔时不需要额外的光刻工艺来定义位线接触孔，从而可以避免光刻曝光偏移，确保位线接触的精确对准；同时，存储器结构的制备方法简单，工艺步骤简洁，节约材料成本和工艺成本。In the memory structure of the present invention, the position and shape of the buried gate word line and the contact of the bit line are respectively defined by forming the sidewall structure and the filling layer, and no additional photolithography process is required to define the contact hole when the bit line is formed. The bit line contact hole can avoid photolithography exposure offset and ensure the precise alignment of the bit line contact; at the same time, the preparation method of the memory structure is simple, the process steps are concise, and the material cost and process cost are saved.
附图说明Description of drawings
图1显示为本实用新型实施例一中提供的半导体结构的制备方法的流程图。FIG. 1 shows a flow chart of a method for fabricating a semiconductor structure provided in Embodiment 1 of the present invention.
图2至图8显示为本实用新型实施例一中提供的半导体结构的制备方法中步骤1)所得结构的结构示意图；其中，图5为于半导体基底内形成浅沟槽隔离结构后所得结构的俯视结构示意图，图6为沿图5中AA方向的截面结构示意图。2 to 8 are schematic structural diagrams of the structure obtained in step 1) of the method for fabricating the semiconductor structure provided in the first embodiment of the present invention; wherein, FIG. 5 is the structure obtained after forming the shallow trench isolation structure in the semiconductor substrate. A schematic top view of the structure, FIG. 6 is a schematic cross-sectional structure along the AA direction in FIG. 5 .
图9显示为本实用新型实施例一中提供的存半导体结构的制备方法中步骤2)所得结构的俯视结构示意图。FIG. 9 is a schematic top view of the structure obtained in step 2) of the method for preparing a semiconductor structure provided in Embodiment 1 of the present invention.
图10显示为沿图9中AA方向的截面结构示意图。FIG. 10 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 9 .
图11显示为本实用新型实施例一中提供的半导体结构的制备方法中步骤3)所得结构的截面结构示意图。FIG. 11 is a schematic cross-sectional structure diagram of the structure obtained in step 3) of the method for fabricating the semiconductor structure provided in the first embodiment of the present invention.
图12显示为本实用新型实施例一中提供的半导体结构的制备方法中步骤4)所得结构的俯视结构示意图。FIG. 12 is a schematic top view of the structure obtained in step 4) of the method for fabricating the semiconductor structure provided in the first embodiment of the present invention.
图13显示为沿图12中AA方向的截面结构示意图。FIG. 13 is a schematic view of the cross-sectional structure along the AA direction in FIG. 12 .
图14显示为本实用新型实施例一中提供的半导体结构的制备方法中步骤5)所得结构的示意图。14 is a schematic diagram of the structure obtained in step 5) of the method for preparing the semiconductor structure provided in the first embodiment of the present invention.
图15为沿图14中AA方向的截面结构示意图。FIG. 15 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 14 .
图16显示为本实用新型实施例三中提供的存储器结构的制备方法的流程图。FIG. 16 shows a flowchart of a method for fabricating a memory structure provided in Embodiment 3 of the present invention.
图17至图23显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤1)所得结构的结构示意图；其中，图19为于半导体基底内形成浅沟槽隔离结构后所得结构的俯视结构示意图，图20为沿图19中AA方向的截面结构示意图。17 to 23 are schematic structural diagrams of the structure obtained in step 1) of the method for fabricating the memory structure provided in the third embodiment of the present invention; wherein, FIG. 19 is the structure obtained after forming the shallow trench isolation structure in the semiconductor substrate. A schematic top view of the structure, FIG. 20 is a schematic cross-sectional structure along the AA direction in FIG. 19 .
图24显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤2)所得结构的俯视结构示意图。FIG. 24 is a schematic top view of the structure obtained in step 2) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图25显示为沿图24中AA方向的截面结构示意图。FIG. 25 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 24 .
图26显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤3)所得结构的截面结构示意图。FIG. 26 is a schematic cross-sectional structure diagram of the structure obtained in step 3) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图27显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤4)所得结构的俯视结构示意图。27 is a schematic top-view structural diagram of the structure obtained in step 4) of the method for preparing a memory structure provided in Embodiment 3 of the present invention.
图28显示为沿图27中AA方向的截面结构示意图。FIG. 28 is a schematic view of the cross-sectional structure along the AA direction in FIG. 27 .
图29显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤5)所得结构的俯视示意图。FIG. 29 is a schematic top view of the structure obtained in step 5) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图30为沿图29中AA方向的截面结构示意图。FIG. 30 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 29 .
图31显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤6)所得结构的截面结构示意图。31 is a schematic cross-sectional structure diagram of the structure obtained in step 6) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图32至图33显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤7)所得结构的截面结构示意图。32 to 33 are schematic cross-sectional structural diagrams of the structure obtained in step 7) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图34至图36显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤8)所得结构的截面结构示意图。34 to 36 are schematic cross-sectional structural diagrams of the structure obtained in step 8) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图37显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤9)所得结构的俯视示意图。37 is a schematic top view of the structure obtained in step 9) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图38为沿图37中AA方向的截面结构示意图。FIG. 38 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 37 .
图39至图41显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤10)所得结构的截面结构示意图。39 to 41 are schematic cross-sectional structural diagrams of the structure obtained in step 10) of the method for fabricating the memory structure provided in Embodiment 3 of the present invention.
图42显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤11)所得结构的截面结构示意图。42 is a schematic cross-sectional structure diagram of the structure obtained in step 11) of the method for fabricating a memory structure provided in Embodiment 3 of the present invention.
图43显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤12)所得结构的俯视示意图。FIG. 43 is a schematic top view of the structure obtained in step 12) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图44为沿图43中AA方向的截面结构示意图。FIG. 44 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 43 .
图45显示为本实用新型实施例三中提供的存储器结构的制备方法中步骤13)所得结构的俯视示意图。45 is a schematic top view of the structure obtained in step 13) of the method for fabricating the memory structure provided in the third embodiment of the present invention.
图46为沿图44中AA方向的截面结构示意图。FIG. 46 is a schematic diagram of a cross-sectional structure along the AA direction in FIG. 44 .
元件标号说明Component label description
10 半导体基底10 Semiconductor substrate
11 垫层结构11 Cushion structure
111 垫氧化层111 Pad oxide
112 垫氮化层112 Pad nitride layer
12 浅沟槽隔离结构12 Shallow Trench Isolation Structure
13 有源区13 Active area
131 深阱区域131 Deep well region
14 硬掩膜层14 Hard mask layer
141 第一硬掩膜层141 first hard mask layer
142 第二硬掩膜层142 Second hard mask layer
15 底部抗反射层15 Bottom anti-reflection layer
151 第二开口图形151 Second opening pattern
16 光刻胶层16 photoresist layer
161 第一开口图形161 The first opening pattern
162 位线接触区域162-bit line contact area
163 埋入式栅极字线区域163 Buried gate word line area
17 侧墙结构17 Side wall structure
18 填充层18 Filler layers
19 图形沟道19 Graphic channel
20 埋入式栅极字线沟槽20 Buried Gate Wordline Trench
21 埋入式栅极字线21 Buried gate word line
211 栅极氧化层211 Gate Oxide
212 栅极导电层212 gate conductive layer
22 介质层22 dielectric layer
23 位线接触孔23-bit line contact hole
24 位线接触24-bit line contact
具体实施方式Detailed ways
以下通过特定的具体实例说明本实用新型的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本实用新型的其他优点与功效。本实用新型还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本实用新型的精神下进行各种修饰或改变。The embodiments of the present invention are described below through specific specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图1至图46。需要说明的是，本实施例中所提供的图示仅以示意方式说明本实用新型的基本构想，虽图示中仅显示与本实用新型中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可为一种随意的改变，且其组件布局形态也可能更为复杂。See Figures 1 through 46. It should be noted that the diagrams provided in this embodiment are only to illustrate the basic concept of the present invention in a schematic way, although the diagrams only show the components related to the present invention rather than the number of components in the actual implementation, In the drawing of shape and size, the shape, quantity and proportion of each component can be arbitrarily changed in actual implementation, and the component layout shape may also be more complicated.
实施例一Example 1
如图1所示，本实用新型提供一种半导体结构的制备方法，所述半导体结构的制备方法包括以下步骤：As shown in FIG. 1 , the present invention provides a method for preparing a semiconductor structure, and the method for preparing a semiconductor structure includes the following steps:
1)提供一半导体基底，于所述半导体基底的表面形成垫层结构；并于所述半导体基底及所述垫层结构内形成浅沟槽隔离结构，所述浅沟槽隔离结构于所述半导体基底内隔离出若干个间隔排布的有源区；1) A semiconductor substrate is provided, a pad layer structure is formed on the surface of the semiconductor substrate; and a shallow trench isolation structure is formed in the semiconductor substrate and the pad layer structure, and the shallow trench isolation structure is formed on the semiconductor substrate A number of spaced active regions are isolated in the substrate;
2)于垫层结构的表面依次形成硬掩膜层、底部抗反射层及光刻胶层，其中，所述硬掩膜层、所述底部抗反射层及所述光刻胶层由下至上依次叠置，且所述光刻胶层中形成有第一开口图形，所述第一开口图形暴露出需要形成位线接触的位线接触区域及需要形成埋入式栅极字线的埋入式栅极字线区域；2) forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the pad structure in turn, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer are from bottom to top are stacked in sequence, and a first opening pattern is formed in the photoresist layer, and the first opening pattern exposes a bit line contact area that needs to form a bit line contact and a buried gate word line that needs to be formed. type gate word line area;
3)依据所述光刻胶层刻蚀所述底部抗反射层，将所述第一开口图形转移至所述底部抗反射层内，以于所述底部抗反射层内形成第二开口图形；3) etching the bottom anti-reflection layer according to the photoresist layer, and transferring the first opening pattern into the bottom anti-reflection layer, so as to form a second opening pattern in the bottom anti-reflection layer;
4)于所述第二开口图形侧壁形成侧墙结构，所述侧墙结构定义出所述埋入式栅极字线区域的位置及形状，所述侧墙结构之外的所述第二开口图形定义出所述位线接触区域的位置及形状；及4) A spacer structure is formed on the sidewall of the second opening pattern. The spacer structure defines the position and shape of the buried gate word line region. The second spacer structure other than the spacer structure is formed. an opening pattern defines the location and shape of the bit line contact region; and
5)于所述侧墙结构之外的所述第二开口图形内形成填充层，其中，于相同的刻蚀条件下，所述填充层的去除速率小于所述底部抗反射层的去除速率及所述侧墙结构的去除速率。5) A filling layer is formed in the second opening pattern outside the sidewall structure, wherein, under the same etching conditions, the removal rate of the filling layer is less than the removal rate of the bottom anti-reflection layer and The removal rate of the sidewall structure.
在步骤1)中，请参阅图1的S11步骤及图2至图5，提供一半导体基底10，于所述半导体基底10的表面形成垫层结构11；并于所述半导体基底10及所述垫层结构11内形成浅沟槽隔离结构12，所述浅沟槽隔离结构12于所述半导体基底10内隔离出若干个间隔排布的有源区13。In step 1), please refer to step S11 of FIG. 1 and FIG. 2 to FIG. 5 , a semiconductor substrate 10 is provided, a pad layer structure 11 is formed on the surface of the semiconductor substrate 10 ; A shallow trench isolation structure 12 is formed in the pad structure 11 , and the shallow trench isolation structure 12 isolates a plurality of spaced active regions 13 in the semiconductor substrate 10 .
作为示例，所述半导体衬底10可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，所述半导体衬底10为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是轻微掺杂的硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。As an example, the semiconductor substrate 10 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, the semiconductor substrate 10 may be a single crystal substrate or a polycrystalline substrate When the substrate is used, it can also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it can be an N-type polysilicon substrate or a P-type polysilicon substrate.
作为示例，可以采用物理气相沉积工艺或化学气相沉积工艺形成所述垫层结构11，具体的，所述垫层结构11可以包括垫氧化层111及垫氮化层112，其中，所述垫氧化层位于所述半导体基底10的表面，所述垫氮化层112位于所述垫氧化层111的表面，如图3所示。As an example, the pad layer structure 11 may be formed by a physical vapor deposition process or a chemical vapor deposition process. Specifically, the pad layer structure 11 may include a pad oxide layer 111 and a pad nitride layer 112 , wherein the pad oxide layer The layers are located on the surface of the semiconductor substrate 10 , and the pad nitride layer 112 is located on the surface of the pad oxide layer 111 , as shown in FIG. 3 .
作为示例，所述浅沟槽隔离结构12可以通过在所述半导体衬底10内形成隔离沟槽后，再采用化学气相沉积或其他的沉积技术在所述隔离沟槽内沉积绝缘层而形成。所述浅沟槽隔离结构12的材料可以包括氮化硅或氧化硅等等。所述浅沟槽隔离结构12的截面形状可以根据实际需要进行设定，其中，在图5中以所述浅沟槽隔离结构12的截面形状包括倒梯形作为示例，但在实际示例中并不以此为限。需要说明的是，在所述隔离沟槽内沉积所述绝缘层时，若所述绝缘层填满所述隔离沟槽且覆盖所述垫层结构11的表面，此时需要采用化学机械研磨工艺去除所述垫层结构11表面的所述绝缘层。As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10 and then depositing an insulating layer in the isolation trench by chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, or the like. The cross-sectional shape of the shallow trench isolation structure 12 can be set according to actual needs, wherein the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example in FIG. This is the limit. It should be noted that, when the insulating layer is deposited in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required at this time. The insulating layer on the surface of the pad structure 11 is removed.
作为示例，所述浅沟槽隔离结构12可以在所述半导体衬底10隔离出的若干个所述有源区13可以为但不仅限于如图4所示的呈阵列排布。As an example, several of the active regions 13 that can be isolated from the semiconductor substrate 10 by the shallow trench isolation structure 12 can be, but not limited to, arranged in an array as shown in FIG. 4 .
作为示例，所述有源区13内形成有MOS器件(未示出)，所述MOS器件包括栅极、源极及漏极，其中，所述源极与所述漏极分别位于所述栅极相对的两侧。As an example, a MOS device (not shown) is formed in the active region 13, and the MOS device includes a gate electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively located at the gate electrode very opposite sides.
作为示例，步骤1)之后还包括如下步骤：As an example, the following steps are also included after step 1):
去除所述垫层结构11，如图6所示；具体的，可以干法刻蚀工艺或湿法刻蚀工艺去除所述垫层结构11；The pad layer structure 11 is removed, as shown in FIG. 6 ; specifically, the pad layer structure 11 can be removed by a dry etching process or a wet etching process;
于所述有源区13内进行离子注入，以于所述有源区13内形成深阱区域131，如图7所示；具体的，形成的所述深阱区域131的类型可以根据实际需要进行选择，可以根据实际需要选择为P型掺杂区域或N型掺杂区域；及Ion implantation is performed in the active region 13 to form a deep well region 131 in the active region 13, as shown in FIG. 7; specifically, the type of the deep well region 131 formed can be based on actual needs selection, and can be selected as a P-type doped region or an N-type doped region according to actual needs; and
于离子注入后的所述半导体基底10表面再次形成垫层结构11，如图8所示。A pad layer structure 11 is formed again on the surface of the semiconductor substrate 10 after ion implantation, as shown in FIG. 8 .
在离子注入前先去除所述位于所述半导体基底10表面的所述垫层结构11，可以有效降低离子注入对能量和剂量的要求，降低离子注入的难度；同时，还可以减少后续可以工序边缘效应的累积。Removing the pad structure 11 on the surface of the semiconductor substrate 10 before ion implantation can effectively reduce the energy and dose requirements of ion implantation, and reduce the difficulty of ion implantation; at the same time, it can also reduce the edge of subsequent processes. accumulation of effects.
所述垫层结构11作为去除后续形成的硬掩膜层的刻蚀终止层，可以有效防止移除所述硬掩膜层时等离子体对所述半导体基底10的等离子损伤；同时，所述垫层结构11还可以作为后续形成的栅极导电层平坦化处理的终止层。The pad layer structure 11 is used as an etch stop layer for removing the hard mask layer formed subsequently, which can effectively prevent plasma damage to the semiconductor substrate 10 when the hard mask layer is removed; at the same time, the pad layer The layer structure 11 can also serve as a termination layer for the subsequent planarization of the gate conductive layer.
在步骤2)中，请参阅图1中的S12步骤及图9至图10，于垫层结构11的表面依次形成硬掩膜层14、底部抗反射层15及光刻胶层16，其中，所述硬掩膜层14、所述底部抗反射层(BARC)15及所述光刻胶层16由下至上依次叠置，且所述光刻胶层16中形成有第一开口图形161，所述第一开口图形161暴露出需要形成位线接触的位线接触区域162及需要形成埋入式栅极字线的埋入式栅极字线区域163。In step 2), referring to step S12 in FIG. 1 and FIG. 9 to FIG. 10 , a hard mask layer 14 , a bottom anti-reflection layer 15 and a photoresist layer 16 are sequentially formed on the surface of the pad structure 11 , wherein, The hard mask layer 14 , the bottom anti-reflection layer (BARC) 15 and the photoresist layer 16 are sequentially stacked from bottom to top, and a first opening pattern 161 is formed in the photoresist layer 16 . The first opening pattern 161 exposes a bit line contact region 162 where a bit line contact needs to be formed and a buried gate word line region 163 where a buried gate word line needs to be formed.
作为示例，于所述垫层结构11的表面形成所述硬掩膜层14可以包括如下步骤：As an example, forming the hard mask layer 14 on the surface of the pad structure 11 may include the following steps:
于所述垫层结构11表面形成第一硬掩膜层141；及forming a first hard mask layer 141 on the surface of the pad structure 11; and
于所述第一硬掩膜层141表面形成第二硬掩膜层142。A second hard mask layer 142 is formed on the surface of the first hard mask layer 141 .
作为示例，所述第一硬掩膜层141可以包括非定型碳(α-C)层、无定型硅(α-Si)层或氮氧化硅层(SiON)；所述第二硬掩膜层142同样可以包括包括非定型碳层、无定型硅层或氮氧化硅层；所述第一硬掩膜层141的材料可以与所述第二硬掩膜层142的材料相同，也可以与所述第二硬掩膜层142的材料不同；优选地，本实施例中，所述第一硬掩膜层141的材料与所述第二硬掩膜层142的材料不同。As an example, the first hard mask layer 141 may include an amorphous carbon (α-C) layer, an amorphous silicon (α-Si) layer or a silicon oxynitride (SiON) layer; the second hard mask layer 142 may also include an amorphous carbon layer, an amorphous silicon layer or a silicon oxynitride layer; the material of the first hard mask layer 141 may be the same as the material of the second hard mask layer 142, or may be the same as the material of the second hard mask layer 142. The material of the second hard mask layer 142 is different; preferably, in this embodiment, the material of the first hard mask layer 141 and the material of the second hard mask layer 142 are different.
在步骤3)中，请参阅图1中的S13步骤及图11，依据所述光刻胶层16刻蚀所述底部抗反射层15，将所述第一开口图形161转移至所述底部抗反射层15内，以于所述底部抗反射层15内形成第二开口图形151。In step 3), please refer to step S13 in FIG. 1 and FIG. 11, the bottom anti-reflection layer 15 is etched according to the photoresist layer 16, and the first opening pattern 161 is transferred to the bottom resist In the reflection layer 15 , a second opening pattern 151 is formed in the bottom anti-reflection layer 15 .
作为示例，可以依据所述光刻胶层16采用但不仅限于干法刻蚀工艺刻蚀所述底部抗反射层15，以在所述底部抗反射层15内形成与所述第一开口图形161一致的所述第二开口图形 151。As an example, the bottom anti-reflection layer 15 may be etched according to the photoresist layer 16 by but not limited to a dry etching process, so as to form the first opening pattern 161 in the bottom anti-reflection layer 15 The second opening pattern 151 is consistent.
作为示例，于所述底部抗反射层15内形成所述第二开口图形151之后，还包括去除所述光刻胶层16的步骤。As an example, after the second opening pattern 151 is formed in the bottom anti-reflection layer 15, the step of removing the photoresist layer 16 is further included.
在步骤4)中，请参阅图1中的S14步骤及图12至图13，于所述第二开口图形151侧壁形成侧墙结构17，所述侧墙结构17定义出所述埋入式栅极字线区域163的位置及形状，所述侧墙结构17之外的所述第二开口图形151定义出所述位线接触区域162的位置及形状。In step 4), please refer to step S14 in FIG. 1 and FIG. 12 to FIG. 13 , a sidewall structure 17 is formed on the sidewall of the second opening pattern 151 , and the sidewall structure 17 defines the embedded type The position and shape of the gate word line region 163 and the second opening pattern 151 outside the spacer structure 17 define the position and shape of the bit line contact region 162 .
作为示例，于所述第二开口图形151侧壁形成所述侧墙结构17可以包括如下步骤：As an example, forming the sidewall structure 17 on the sidewall of the second opening pattern 151 may include the following steps:
4-1)采用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺于所述底部抗反射层 15的表面、所述第二开口图形151的侧壁及底部形成侧墙材料层；及4-1) using atomic layer deposition process, physical vapor deposition process or chemical vapor deposition process to form a sidewall material layer on the surface of the bottom anti-reflection layer 15, the sidewall and bottom of the second opening pattern 151; and
4-2)采用干法刻蚀工艺去除位于所述底部抗反射层15表面及所述第二开口图形151底部的所述侧墙材料层，保留于所述第二开口图形151侧壁的所述侧墙材料层即构成所述侧墙结构17。4-2) Use a dry etching process to remove the sidewall material layer located on the surface of the bottom anti-reflection layer 15 and the bottom of the second opening pattern 151, and keep all the sidewalls of the second opening pattern 151. The sidewall material layer constitutes the sidewall structure 17 .
作为示例，所述侧墙结构17可以包括氧化物侧墙结构，即所述侧墙结构17的材料可以包括氧化物，譬如，氧化硅等等。As an example, the spacer structure 17 may include an oxide spacer structure, that is, the material of the spacer structure 17 may include oxide, such as silicon oxide and the like.
需要说明的是，“所述侧墙结构17之外的所述第二开口图形151”是指所述第二开口图形151内形成所述侧墙结构17后保留的区域。It should be noted that “the second opening pattern 151 outside the sidewall structure 17 ” refers to the area remaining after the sidewall structure 17 is formed in the second opening pattern 151 .
在步骤5)中，请参阅图1中的S15步骤及图14至图15，于所述侧墙结构17之外的所述第二开口图形151内形成填充层18，其中，于相同的刻蚀条件下，所述填充层18的去除速率小于所述底部抗反射层15的去除速率及所述侧墙结构17的去除速率。In step 5), please refer to step S15 in FIG. 1 and FIG. 14 to FIG. 15 , a filling layer 18 is formed in the second opening pattern 151 outside the sidewall structure 17 , wherein, in the same etching process Under the etching conditions, the removal rate of the filling layer 18 is lower than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the spacer structure 17 .
作为示例，于所述侧墙结构17之外的所述第二开口图形151内形成填充层18包括如下步骤：As an example, forming the filling layer 18 in the second opening pattern 151 outside the sidewall structure 17 includes the following steps:
5-1)于所述侧墙结构17之外的所述开口图形151内及所述底部抗反射层15的表面形成填充层18；及5-1) forming a filling layer 18 in the opening pattern 151 outside the sidewall structure 17 and on the surface of the bottom anti-reflection layer 15; and
5-2)采用干法刻蚀工艺回刻去除位于所述底部抗反射层15表面的所述填充层18。5-2) The filling layer 18 located on the surface of the bottom anti-reflection layer 15 is removed by using a dry etching process.
作为示例，所述填充层18的材料应与所述底部抗反射层15的材料及所述侧墙结构17的材料均不相同，以使得所述填充层18具有与所述底部抗反射层15及所述侧墙结构17不同的刻蚀选择比；优选地，于相同的刻蚀条件下，所述填充层18的去除速率小于所述底部抗反射层15的去除速率及所述侧墙结构17的去除速率，即在相同的刻蚀条件下，所述填充层18与所述底部抗反射层15及所述侧墙结构17具有较高的选择比。更为优选地，本实施例中，所述填充层18可以但不仅限于包括氮化物层，即所述填充层18的材料可以包括但不仅限于氮化物，譬如，氮化硅。所述填充层18的材料的选择比高于所述底部抗反射层15及所述侧墙结构17的选择比，在刻蚀去除所述底部抗反射层15及所述侧墙结构17时，可以使得所述填充层18被保留下来，从而可以在需要形成位线接触孔时实现自对准。As an example, the material of the filling layer 18 should be different from the material of the bottom anti-reflection layer 15 and the material of the spacer structure 17 , so that the filling layer 18 has the same material as the bottom anti-reflection layer 15 . and the different etching selectivity ratios of the sidewall structures 17; preferably, under the same etching conditions, the removal rate of the filling layer 18 is lower than the removal rate of the bottom anti-reflection layer 15 and the sidewall structures. 17 , that is, under the same etching conditions, the filling layer 18 has a higher selectivity ratio to the bottom anti-reflection layer 15 and the spacer structure 17 . More preferably, in this embodiment, the filling layer 18 may include, but is not limited to, a nitride layer, that is, the material of the filling layer 18 may include, but is not limited to, nitride, such as silicon nitride. The selection ratio of the material of the filling layer 18 is higher than the selection ratio of the bottom anti-reflection layer 15 and the sidewall structure 17. When the bottom anti-reflection layer 15 and the sidewall structure 17 are removed by etching, The filling layer 18 can be made to remain so that self-alignment can be achieved when bit line contact holes need to be formed.
本实用新型的半导体结构的制备方法制备的半导体结构可以在形成所述侧墙结构17及所述填充层18时即同时自对准定义出需要形成埋入式栅极字线的埋入式栅极字线区域163及需要形成位线接触的所述位线接触区域162的位置及形状，在基于所述半导体结构制备埋入式栅极字线及位线接触时，不需要额外的光刻工艺来定义位线接触孔，从而开避免光刻形成位线接触孔时存在的曝光偏移，进而确保位线接触的精确对准；同时，本实用新型的半导体结构的制备方法工艺步骤简洁，可以有效节约材料成本及工艺成本。The semiconductor structure prepared by the method for preparing the semiconductor structure of the present invention can self-align and define the buried gate to be formed with the buried gate word line at the same time when the spacer structure 17 and the filling layer 18 are formed. The position and shape of the pole word line region 163 and the bit line contact region 162 where the bit line contact needs to be formed. When preparing the buried gate word line and the bit line contact based on the semiconductor structure, no additional photolithography is required. process to define the bit line contact hole, so as to avoid the exposure offset existing when the bit line contact hole is formed by photolithography, thereby ensuring the precise alignment of the bit line contact; at the same time, the process steps of the preparation method of the semiconductor structure of the present invention are concise, It can effectively save material cost and process cost.
实施例二Embodiment 2
请继续参阅图2至图15，本实用新型还提供一种半导体结构，所述半导体结构包括：半导体基底10；垫层结构11，所述垫层结构11位于所述半导体基底10的表面；浅沟槽隔离结构12，所述浅沟槽隔离结构12位于所述半导体基底10及所述垫层结构11内，以于所述半导体基底10内隔离出若干个间隔排布的有源区13；硬掩膜层14，硬掩膜层14位于所述垫层结构11的表面；底部抗反射涂层15，所述底部抗反射涂层15位于所述硬掩膜层14的表面；填充层18，所述填充层18位于所述底部抗反射涂层15内，所述填充层18定义出需要形成的位线接触的位置及形状；及侧墙结构17，所述侧墙结构17位于所述底部抗反射涂层15内，且位于所述填充层18的外侧，所述侧墙结构17定义出需要形成的埋入式栅极字线的位置及形状；其中，于相同的刻蚀条件下，所述填充层18的去除速率小于所述底部抗反射层15的去除速率及所述侧墙结构17的去除速率。Please continue to refer to FIG. 2 to FIG. 15 , the present invention further provides a semiconductor structure, the semiconductor structure includes: a semiconductor substrate 10 ; a pad layer structure 11 , the pad layer structure 11 is located on the surface of the semiconductor substrate 10 ; a trench isolation structure 12, the shallow trench isolation structure 12 is located in the semiconductor substrate 10 and the pad structure 11, so as to isolate a plurality of spaced active regions 13 in the semiconductor substrate 10; Hard mask layer 14, the hard mask layer 14 is located on the surface of the cushion structure 11; bottom anti-reflection coating 15, the bottom anti-reflection coating 15 is located on the surface of the hard mask layer 14; filling layer 18 , the filling layer 18 is located in the bottom anti-reflection coating 15, the filling layer 18 defines the position and shape of the bit line contact to be formed; and the spacer structure 17, the spacer structure 17 is located in the Inside the bottom anti-reflective coating 15 and outside the filling layer 18, the spacer structure 17 defines the position and shape of the buried gate word line to be formed; wherein, under the same etching conditions , the removal rate of the filling layer 18 is lower than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the sidewall structure 17 .
作为示例，所述半导体衬底10可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，所述半导体衬底10为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是轻微掺杂的硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。As an example, the semiconductor substrate 10 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, the semiconductor substrate 10 may be a single crystal substrate or a polycrystalline substrate When the substrate is used, it can also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it can be an N-type polysilicon substrate or a P-type polysilicon substrate.
作为示例，所述垫层结构11包括垫氧化层111及垫氮化层112，其中，所述垫氧化层位于所述半导体基底10的表面，所述垫氮化层112位于所述垫氧化层111的表面，如图3所示。As an example, the pad structure 11 includes a pad oxide layer 111 and a pad nitride layer 112 , wherein the pad oxide layer is located on the surface of the semiconductor substrate 10 , and the pad nitride layer 112 is located on the pad oxide layer 111, as shown in Figure 3.
作为示例，所述浅沟槽隔离结构12可以通过在所述半导体衬底10内形成隔离沟槽后，再采用化学气相沉积或其他的沉积技术在所述隔离沟槽内沉积绝缘层而形成。所述浅沟槽隔离结构12的材料可以包括氮化硅或氧化硅等等。所述浅沟槽隔离结构12的截面形状可以根据实际需要进行设定，其中，在图5中以所述浅沟槽隔离结构12的截面形状包括倒梯形作为示例，但在实际示例中并不以此为限。需要说明的是，在所述隔离沟槽内沉积所述绝缘层时，若所述绝缘层填满所述隔离沟槽且覆盖所述垫层结构11的表面，此时需要采用化学机械研磨工艺去除所述垫层结构11表面的所述绝缘层。As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10 and then depositing an insulating layer in the isolation trench by chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, or the like. The cross-sectional shape of the shallow trench isolation structure 12 can be set according to actual needs, wherein the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example in FIG. This is the limit. It should be noted that, when the insulating layer is deposited in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required at this time. The insulating layer on the surface of the pad structure 11 is removed.
作为示例，所述浅沟槽隔离结构12可以在所述半导体衬底10隔离出的若干个所述有源区13可以为但不仅限于如图4所示的呈阵列排布。As an example, several of the active regions 13 that can be isolated from the semiconductor substrate 10 by the shallow trench isolation structure 12 can be, but not limited to, arranged in an array as shown in FIG. 4 .
作为示例，所述有源区13内形成有MOS器件(未示出)，所述MOS器件包括栅极、源极及漏极，其中，所述源极与所述漏极分别位于所述栅极相对的两侧。As an example, a MOS device (not shown) is formed in the active region 13, and the MOS device includes a gate electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively located at the gate electrode very opposite sides.
作为示例，所述有源区13内还形成有深阱区域131，如图7所示；具体的，形成的所述深阱区域131的类型可以根据实际需要进行选择，可以根据实际需要选择为P型掺杂区域或 N型掺杂区域。As an example, a deep well region 131 is also formed in the active region 13, as shown in FIG. 7; specifically, the type of the deep well region 131 formed can be selected according to actual needs, and can be selected according to actual needs as P-type doped regions or N-type doped regions.
所述垫层结构11作为去除后续形成的硬掩膜层的刻蚀终止层，可以有效防止移除所述硬掩膜层时等离子体对所述半导体基底10的等离子损伤；同时，所述垫层结构11还可以作为后续形成的栅极导电层平坦化处理的终止层。The pad layer structure 11 is used as an etch stop layer for removing the hard mask layer formed subsequently, which can effectively prevent plasma damage to the semiconductor substrate 10 when the hard mask layer is removed; at the same time, the pad layer The layer structure 11 can also serve as a termination layer for the subsequent planarization of the gate conductive layer.
作为示例，所述硬掩膜层14包括：第一硬掩膜层141，所述第一硬掩膜层141位于所述垫层结构11的表面；及第二硬掩膜层142，所述第二硬掩膜层142位于所述第一硬掩膜层141 的表面。As an example, the hard mask layer 14 includes: a first hard mask layer 141, the first hard mask layer 141 is located on the surface of the pad structure 11; and a second hard mask layer 142, the The second hard mask layer 142 is located on the surface of the first hard mask layer 141 .
作为示例，所述第一硬掩膜层141可以包括非定型碳(α-C)层、无定型硅(α-Si)层或氮氧化硅层(SiON)；所述第二硬掩膜层142同样可以包括包括非定型碳层、无定型硅层或氮氧化硅层；所述第一硬掩膜层141的材料可以与所述第二硬掩膜层142的材料相同，也可以与所述第二硬掩膜层142的材料不同；优选地，本实施例中，所述第一硬掩膜层141的材料与所述第二硬掩膜层142的材料不同。As an example, the first hard mask layer 141 may include an amorphous carbon (α-C) layer, an amorphous silicon (α-Si) layer or a silicon oxynitride (SiON) layer; the second hard mask layer 142 may also include an amorphous carbon layer, an amorphous silicon layer or a silicon oxynitride layer; the material of the first hard mask layer 141 may be the same as the material of the second hard mask layer 142, or may be the same as the material of the second hard mask layer 142. The material of the second hard mask layer 142 is different; preferably, in this embodiment, the material of the first hard mask layer 141 and the material of the second hard mask layer 142 are different.
作为示例，所述侧墙结构17定义出需要形成所述埋入式栅极字线的所述埋入式栅极字线区域163的位置及形状，所述侧墙结构17可以包括氧化物侧墙结构，即所述侧墙结构17的材料可以包括氧化物，譬如，氧化硅等等。As an example, the spacer structure 17 defines the position and shape of the buried gate word line region 163 where the buried gate word line needs to be formed, and the spacer structure 17 may include an oxide side The wall structure, that is, the material of the side wall structure 17 may include oxides, such as silicon oxide and the like.
作为示例，所述填充层18定义出需要形成的所述位线接触的位线接触区域162的位置及形状，所述填充层18的材料应与所述底部抗反射层15的材料及所述侧墙结构17的材料均不相同，以使得所述填充层18具有与所述底部抗反射层15及所述侧墙结构17不同的刻蚀选择比；优选地，于相同的刻蚀条件下，所述填充层18的去除速率小于所述底部抗反射层15的去除速率及所述侧墙结构17的去除速率，即在相同的刻蚀条件下，所述填充层18与所述底部抗反射层15及所述侧墙结构17具有较高的选择比。更为优选地，本实施例中，所述填充层18可以但不仅限于包括氮化物层，即所述填充层18的材料可以包括但不仅限于氮化物，譬如，氮化硅。所述填充层18的材料的选择比高于所述底部抗反射层15及所述侧墙结构17 的选择比，在刻蚀去除所述底部抗反射层15及所述侧墙结构17时，可以使得所述填充层18 被保留下来，从而可以在需要形成位线接触孔时实现自对准。As an example, the filling layer 18 defines the position and shape of the bit line contact region 162 to be formed. The material of the filling layer 18 should be the same as the material of the bottom anti-reflection layer 15 and the The materials of the sidewall structures 17 are all different, so that the filling layer 18 has a different etching selectivity ratio from the bottom anti-reflection layer 15 and the sidewall structures 17; preferably, under the same etching conditions , the removal rate of the filling layer 18 is smaller than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the spacer structure 17, that is, under the same etching conditions, the filling layer 18 and the bottom anti- The reflective layer 15 and the sidewall structure 17 have a high selectivity ratio. More preferably, in this embodiment, the filling layer 18 may include, but is not limited to, a nitride layer, that is, the material of the filling layer 18 may include, but is not limited to, nitride, such as silicon nitride. The selection ratio of the material of the filling layer 18 is higher than the selection ratio of the bottom anti-reflection layer 15 and the spacer structure 17. When the bottom anti-reflection layer 15 and the spacer structure 17 are removed by etching, The filling layer 18 can be made to remain so that self-alignment can be achieved when bit line contact holes need to be formed.
本实用新型的半导体结构的制备方法制备的半导体结构可以在形成所述侧墙结构17及所述填充层18时即同时自对准定义出需要形成埋入式栅极字线的埋入式栅极字线区域163及需要形成位线接触的所述位线接触区域162的位置及形状，在基于所述半导体结构制备埋入式栅极字线及位线接触时，不需要额外的光刻工艺来定义位线接触孔，从而开避免光刻形成位线接触孔时存在的曝光偏移，进而确保位线接触的精确对准；同时，本实用新型的半导体结构的制备方法工艺步骤简洁，可以有效节约材料成本及工艺成本。The semiconductor structure prepared by the method for preparing the semiconductor structure of the present invention can self-align and define the buried gate to be formed with the buried gate word line at the same time when the spacer structure 17 and the filling layer 18 are formed. The position and shape of the pole word line region 163 and the bit line contact region 162 where the bit line contact needs to be formed. When preparing the buried gate word line and the bit line contact based on the semiconductor structure, no additional photolithography is required. process to define the bit line contact hole, so as to avoid the exposure offset existing when the bit line contact hole is formed by photolithography, thereby ensuring the precise alignment of the bit line contact; at the same time, the process steps of the preparation method of the semiconductor structure of the present invention are concise, It can effectively save material cost and process cost.
实施例三Embodiment 3
请参阅图16，本实用新型还提供一种存储器结构的制备方法，所述存储器结构的制备方法包括以下步骤：Please refer to FIG. 16 , the present invention also provides a method for preparing a memory structure. The method for preparing a memory structure includes the following steps:
1)提供一半导体基底，于所述半导体基底的表面形成垫层结构；并于所述半导体基底及所述垫层结构内形成浅沟槽隔离结构，所述浅沟槽隔离结构于所述半导体基底内隔离出若干个间隔排布的有源区；1) A semiconductor substrate is provided, a pad layer structure is formed on the surface of the semiconductor substrate; and a shallow trench isolation structure is formed in the semiconductor substrate and the pad layer structure, and the shallow trench isolation structure is formed on the semiconductor substrate A number of spaced active regions are isolated in the substrate;
2)于垫层结构的表面依次形成硬掩膜层、底部抗反射层及光刻胶层，其中，所述硬掩膜层、所述底部抗反射层及所述光刻胶层由下至上依次叠置，且所述光刻胶层中形成有第一开口图形，所述第一开口图形暴露出需要形成位线接触的位线接触区域及需要形成埋入式栅极字线的埋入式栅极字线区域；2) forming a hard mask layer, a bottom anti-reflection layer and a photoresist layer on the surface of the pad structure in turn, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer are from bottom to top are stacked in sequence, and a first opening pattern is formed in the photoresist layer, and the first opening pattern exposes a bit line contact area that needs to form a bit line contact and a buried gate word line that needs to be formed. type gate word line area;
3)依据所述光刻胶层刻蚀所述底部抗反射层，将所述第一开口图形转移至所述底部抗反射层内，以于所述底部抗反射层内形成第二开口图形；3) etching the bottom anti-reflection layer according to the photoresist layer, and transferring the first opening pattern into the bottom anti-reflection layer, so as to form a second opening pattern in the bottom anti-reflection layer;
4)于所述第二开口图形侧壁形成侧墙结构，所述侧墙结构定义出所述埋入式栅极字线区域的位置及形状，所述侧墙结构之外的所述第二开口图形定义出所述位线接触区域的位置及形状；4) A spacer structure is formed on the sidewall of the second opening pattern. The spacer structure defines the position and shape of the buried gate word line region. The second spacer structure other than the spacer structure is formed. The opening pattern defines the position and shape of the bit line contact area;
5)于所述侧墙结构之外的所述第二开口图形内形成填充层，其中，于相同的刻蚀条件下，所述填充层的去除速率小于所述底部抗反射层的去除速率及所述侧墙结构的去除速率；5) A filling layer is formed in the second opening pattern outside the sidewall structure, wherein, under the same etching conditions, the removal rate of the filling layer is less than the removal rate of the bottom anti-reflection layer and the removal rate of the sidewall structure;
6)刻蚀去除所述侧墙结构、位于所述埋入式栅极字线区域的所述硬掩膜层，以于所述底部抗反射层及所述硬掩膜层内形成图形沟道，所述图形沟道定义出所述埋入式栅极字线的位置及形状；6) Etching and removing the spacer structure and the hard mask layer located in the buried gate word line region, so as to form a pattern channel in the bottom anti-reflection layer and the hard mask layer , the pattern channel defines the position and shape of the buried gate word line;
7)去除所述填充层及所述底部抗反射层；7) removing the filling layer and the bottom anti-reflection layer;
8)去除所述图形沟道底部的所述垫层结构，并去除所述位线接触区域之外的所述硬掩膜层；8) removing the pad layer structure at the bottom of the pattern channel, and removing the hard mask layer outside the bit line contact region;
9)依据所述图形沟道刻蚀所述半导体基底，以于所述半导体基底内形成埋入式栅极字线沟槽；9) etching the semiconductor substrate according to the pattern channel to form a buried gate word line trench in the semiconductor substrate;
10)于所述埋入式栅极字线沟槽内形成埋入式栅极字线，所述埋入式栅极字线的上表面低于所述半导体基底的上表面；10) forming a buried gate word line in the buried gate word line trench, and the upper surface of the buried gate word line is lower than the upper surface of the semiconductor substrate;
11)于所述埋入式栅极字线沟槽内及所述垫层结构表面形成介质层；所述介质层填满所述埋入式栅极字线沟槽并覆盖所述垫层结构的表面；11) forming a dielectric layer in the buried gate word line trench and on the surface of the pad structure; the dielectric layer fills the buried gate word line trench and covers the pad structure s surface;
12)去除所述位线接触区域的所述硬掩膜层并刻蚀所述半导体基底，以于所述介质层及所述半导体基底内形成位线接触孔，所述位线接触孔，所述位线接触孔的底部陷入于所述半导体基底内；及12) Remove the hard mask layer of the bit line contact region and etch the semiconductor substrate, so as to form a bit line contact hole in the dielectric layer and the semiconductor substrate, the bit line contact hole, so the bottom of the bit line contact hole is recessed into the semiconductor substrate; and
13)于所述位线接触孔内填充接触材料，以形成位线接触。13) Filling the bit line contact hole with contact material to form a bit line contact.
在步骤1)中，请参阅图16中的S21步骤及图17至图20，提供一半导体基底10，于所述半导体基底10的表面形成垫层结构11；并于所述半导体基底10及所述垫层结构11内形成浅沟槽隔离结构12，所述浅沟槽隔离结构12于所述半导体基底10内隔离出若干个间隔排布的有源区13。In step 1), please refer to step S21 in FIG. 16 and FIG. 17 to FIG. 20 , a semiconductor substrate 10 is provided, a pad structure 11 is formed on the surface of the semiconductor substrate 10 ; A shallow trench isolation structure 12 is formed in the pad structure 11 , and the shallow trench isolation structure 12 isolates a plurality of spaced active regions 13 in the semiconductor substrate 10 .
作为示例，所述半导体衬底10可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，所述半导体衬底10为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是轻微掺杂的硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。As an example, the semiconductor substrate 10 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, the semiconductor substrate 10 may be a single crystal substrate or a polycrystalline substrate When the substrate is used, it can also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it can be an N-type polysilicon substrate or a P-type polysilicon substrate.
作为示例，可以采用物理气相沉积工艺或化学气相沉积工艺形成所述垫层结构11，具体的，所述垫层结构11可以包括垫氧化层111及垫氮化层112，其中，所述垫氧化层位于所述半导体基底10的表面，所述垫氮化层112位于所述垫氧化层111的表面，如图20所示。As an example, the pad layer structure 11 may be formed by a physical vapor deposition process or a chemical vapor deposition process. Specifically, the pad layer structure 11 may include a pad oxide layer 111 and a pad nitride layer 112 , wherein the pad oxide layer The layers are located on the surface of the semiconductor substrate 10 , and the pad nitride layer 112 is located on the surface of the pad oxide layer 111 , as shown in FIG. 20 .
作为示例，所述浅沟槽隔离结构12可以通过在所述半导体衬底10内形成隔离沟槽后，再采用化学气相沉积或其他的沉积技术在所述隔离沟槽内沉积绝缘层而形成。所述浅沟槽隔离结构12的材料可以包括氮化硅或氧化硅等等。所述浅沟槽隔离结构12的截面形状可以根据实际需要进行设定，其中，在图20中以所述浅沟槽隔离结构12的截面形状包括倒梯形作为示例，但在实际示例中并不以此为限。需要说明的是，在所述隔离沟槽内沉积所述绝缘层时，若所述绝缘层填满所述隔离沟槽且覆盖所述垫层结构11的表面，此时需要采用化学机械研磨工艺去除所述垫层结构11表面的所述绝缘层。As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10 and then depositing an insulating layer in the isolation trench by chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, or the like. The cross-sectional shape of the shallow trench isolation structure 12 can be set according to actual needs. In FIG. 20 , the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example, but in an actual example, it is not This is the limit. It should be noted that, when the insulating layer is deposited in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required at this time. The insulating layer on the surface of the pad structure 11 is removed.
作为示例，所述浅沟槽隔离结构12可以在所述半导体衬底10隔离出的若干个所述有源区13可以为但不仅限于如图19所示的呈阵列排布。As an example, several of the active regions 13 that can be isolated from the semiconductor substrate 10 by the shallow trench isolation structure 12 can be, but not limited to, arranged in an array as shown in FIG. 19 .
作为示例，所述有源区13内形成有MOS器件(未示出)，所述MOS器件包括栅极、源极及漏极，其中，所述源极与所述漏极分别位于所述栅极相对的两侧。As an example, a MOS device (not shown) is formed in the active region 13, and the MOS device includes a gate electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively located at the gate electrode very opposite sides.
作为示例，步骤1)之后还包括如下步骤：As an example, the following steps are also included after step 1):
去除所述垫层结构11，如图21所示；具体的，可以干法刻蚀工艺或湿法刻蚀工艺去除所述垫层结构11；The pad layer structure 11 is removed, as shown in FIG. 21 ; specifically, the pad layer structure 11 can be removed by a dry etching process or a wet etching process;
于所述有源区13内进行离子注入，以于所述有源区13内形成深阱区域131，如图22所示；具体的，形成的所述深阱区域131的类型可以根据实际需要进行选择，可以根据实际需要选择为P型掺杂区域或N型掺杂区域；及Ion implantation is performed in the active region 13 to form a deep well region 131 in the active region 13, as shown in FIG. 22; specifically, the type of the deep well region 131 formed can be based on actual needs selection, and can be selected as a P-type doped region or an N-type doped region according to actual needs; and
于离子注入后的所述半导体基底10表面再次形成垫层结构11，如图23所示。A pad layer structure 11 is formed again on the surface of the semiconductor substrate 10 after ion implantation, as shown in FIG. 23 .
在离子注入前先去除所述位于所述半导体基底10表面的所述垫层结构11，可以有效降低离子注入对能量和剂量的要求，降低离子注入的难度；同时，还可以减少后续可以工序边缘效应的累积。Removing the pad structure 11 on the surface of the semiconductor substrate 10 before ion implantation can effectively reduce the energy and dose requirements of ion implantation, and reduce the difficulty of ion implantation; at the same time, it can also reduce the edge of subsequent processes. accumulation of effects.
所述垫层结构11作为去除后续形成的硬掩膜层的刻蚀终止层，可以有效防止移除所述硬掩膜层时等离子体对所述半导体基底10的等离子损伤；同时，所述垫层结构11还可以作为后续形成的栅极导电层平坦化处理的终止层。The pad layer structure 11 is used as an etch stop layer for removing the hard mask layer formed subsequently, which can effectively prevent plasma damage to the semiconductor substrate 10 when the hard mask layer is removed; at the same time, the pad layer The layer structure 11 can also serve as a termination layer for the subsequent planarization of the gate conductive layer.
在步骤2)中，请参阅图16中的S22步骤及图24至图25，于垫层结构11的表面依次形成硬掩膜层14、底部抗反射层15及光刻胶层16，其中，所述硬掩膜层14、所述底部抗反射层(BARC)15及所述光刻胶层16由下至上依次叠置，且所述光刻胶层16中形成有第一开口图形161，所述第一开口图形161暴露出需要形成位线接触的位线接触区域162及需要形成埋入式栅极字线的埋入式栅极字线区域163。In step 2), referring to step S22 in FIG. 16 and FIGS. 24 to 25 , a hard mask layer 14 , a bottom anti-reflection layer 15 and a photoresist layer 16 are sequentially formed on the surface of the pad structure 11 , wherein, The hard mask layer 14 , the bottom anti-reflection layer (BARC) 15 and the photoresist layer 16 are sequentially stacked from bottom to top, and a first opening pattern 161 is formed in the photoresist layer 16 . The first opening pattern 161 exposes a bit line contact region 162 where a bit line contact needs to be formed and a buried gate word line region 163 where a buried gate word line needs to be formed.
作为示例，于所述垫层结构11的表面形成所述硬掩膜层14可以包括如下步骤：As an example, forming the hard mask layer 14 on the surface of the pad structure 11 may include the following steps:
于所述垫层结构11表面形成第一硬掩膜层141；及forming a first hard mask layer 141 on the surface of the pad structure 11; and
于所述第一硬掩膜层141表面形成第二硬掩膜层142。A second hard mask layer 142 is formed on the surface of the first hard mask layer 141 .
作为示例，所述第一硬掩膜层141可以包括非定型碳(α-C)层、无定型硅(α-Si)层或氮氧化硅层(SiON)；所述第二硬掩膜层142同样可以包括包括非定型碳层、无定型硅层或氮氧化硅层；所述第一硬掩膜层141的材料可以与所述第二硬掩膜层142的材料相同，也可以与所述第二硬掩膜层142的材料不同；优选地，本实施例中，所述第一硬掩膜层141的材料与所述第二硬掩膜层142的材料不同。As an example, the first hard mask layer 141 may include an amorphous carbon (α-C) layer, an amorphous silicon (α-Si) layer or a silicon oxynitride (SiON) layer; the second hard mask layer 142 may also include an amorphous carbon layer, an amorphous silicon layer or a silicon oxynitride layer; the material of the first hard mask layer 141 may be the same as the material of the second hard mask layer 142, or may be the same as the material of the second hard mask layer 142. The material of the second hard mask layer 142 is different; preferably, in this embodiment, the material of the first hard mask layer 141 and the material of the second hard mask layer 142 are different.
在步骤3)中，请参阅图16中的S23步骤及图26，依据所述光刻胶层16刻蚀所述底部抗反射层15，将所述第一开口图形161转移至所述底部抗反射层15内，以于所述底部抗反射层15内形成第二开口图形151。In step 3), please refer to step S23 in FIG. 16 and FIG. 26, the bottom anti-reflection layer 15 is etched according to the photoresist layer 16, and the first opening pattern 161 is transferred to the bottom resist In the reflection layer 15 , a second opening pattern 151 is formed in the bottom anti-reflection layer 15 .
作为示例，可以依据所述光刻胶层16采用但不仅限于干法刻蚀工艺刻蚀所述底部抗反射层15，以在所述底部抗反射层15内形成与所述第一开口图形161一致的所述第二开口图形 151。As an example, the bottom anti-reflection layer 15 may be etched according to the photoresist layer 16 by but not limited to a dry etching process, so as to form the first opening pattern 161 in the bottom anti-reflection layer 15 The second opening pattern 151 is consistent.
作为示例，于所述底部抗反射层15内形成所述第二开口图形151之后，还包括去除所述光刻胶层16的步骤。As an example, after the second opening pattern 151 is formed in the bottom anti-reflection layer 15, the step of removing the photoresist layer 16 is further included.
在步骤4)中，请参阅图16中的S24步骤及图27至图28，于所述第二开口图形151侧壁形成侧墙结构17，所述侧墙结构17定义出所述埋入式栅极字线区域163的位置及形状，所述侧墙结构17之外的所述第二开口图形151定义出所述位线接触区域162的位置及形状。In step 4), please refer to step S24 in FIG. 16 and FIGS. 27 to 28 , a sidewall structure 17 is formed on the sidewall of the second opening pattern 151 , and the sidewall structure 17 defines the embedded type The position and shape of the gate word line region 163 and the second opening pattern 151 outside the spacer structure 17 define the position and shape of the bit line contact region 162 .
作为示例，于所述第二开口图形151侧壁形成所述侧墙结构17可以包括如下步骤：As an example, forming the sidewall structure 17 on the sidewall of the second opening pattern 151 may include the following steps:
4-1)采用原子层沉积工艺、物理气相沉积工艺或化学气相沉积工艺于所述底部抗反射层 15的表面、所述第二开口图形151的侧壁及底部形成侧墙材料层；及4-1) using atomic layer deposition process, physical vapor deposition process or chemical vapor deposition process to form a sidewall material layer on the surface of the bottom anti-reflection layer 15, the sidewall and bottom of the second opening pattern 151; and
4-2)采用干法刻蚀工艺去除位于所述底部抗反射层15表面及所述第二开口图形151底部的所述侧墙材料层，保留于所述第二开口图形151侧壁的所述侧墙材料层即构成所述侧墙结构17。4-2) Use a dry etching process to remove the sidewall material layer located on the surface of the bottom anti-reflection layer 15 and the bottom of the second opening pattern 151, and keep all the sidewalls of the second opening pattern 151. The sidewall material layer constitutes the sidewall structure 17 .
作为示例，所述侧墙结构17可以包括氧化物侧墙结构，即所述侧墙结构17的材料可以包括氧化物，譬如，氧化硅等等。As an example, the spacer structure 17 may include an oxide spacer structure, that is, the material of the spacer structure 17 may include oxide, such as silicon oxide and the like.
需要说明的是，“所述侧墙结构17之外的所述第二开口图形151”是指所述第二开口图形151内形成所述侧墙结构17后保留的区域。It should be noted that “the second opening pattern 151 outside the sidewall structure 17 ” refers to the area remaining after the sidewall structure 17 is formed in the second opening pattern 151 .
在步骤5)中，请参阅图16中的S25步骤及图29至图30，于所述侧墙结构17之外的所述第二开口图形151内形成填充层18，其中，于相同的刻蚀条件下，所述填充层18的去除速率小于所述底部抗反射层15的去除速率及所述侧墙结构17的去除速率。In step 5), please refer to step S25 in FIG. 16 and FIG. 29 to FIG. 30 , a filling layer 18 is formed in the second opening pattern 151 other than the sidewall structure 17 , wherein, in the same etching process Under the etching conditions, the removal rate of the filling layer 18 is lower than the removal rate of the bottom anti-reflection layer 15 and the removal rate of the spacer structure 17 .
作为示例，于所述侧墙结构17之外的所述第二开口图形151内形成填充层18包括如下步骤：As an example, forming the filling layer 18 in the second opening pattern 151 outside the sidewall structure 17 includes the following steps:
5-1)于所述侧墙结构17之外的所述开口图形151内及所述底部抗反射层15的表面形成填充层18；及5-1) forming a filling layer 18 in the opening pattern 151 outside the sidewall structure 17 and on the surface of the bottom anti-reflection layer 15; and
5-2)采用干法刻蚀工艺回刻去除位于所述底部抗反射层15表面的所述填充层18。5-2) The filling layer 18 located on the surface of the bottom anti-reflection layer 15 is removed by using a dry etching process.
作为示例，所述填充层18的材料应与所述底部抗反射层15的材料及所述侧墙结构17的材料均不相同，以使得所述填充层18具有与所述底部抗反射层15及所述侧墙结构17不同的刻蚀选择比；优选地，于相同的刻蚀条件下，所述填充层18的去除速率小于所述底部抗反射层15的去除速率及所述侧墙结构17的去除速率，即在相同的刻蚀条件下，所述填充层18与所述底部抗反射层15及所述侧墙结构17具有较高的选择比。更为优选地，本实施例中，所述填充层18可以但不仅限于包括氮化物层，即所述填充层18的材料可以包括但不仅限于氮化物，譬如，氮化硅。所述填充层18的材料的选择比高于所述底部抗反射层15及所述侧墙结构17的选择比，在刻蚀去除所述底部抗反射层15及所述侧墙结构17时，可以使得所述填充层18被保留下来，从而可以在需要形成位线接触孔时实现自对准。As an example, the material of the filling layer 18 should be different from the material of the bottom anti-reflection layer 15 and the material of the spacer structure 17 , so that the filling layer 18 has the same material as the bottom anti-reflection layer 15 . and the different etching selectivity ratios of the sidewall structures 17; preferably, under the same etching conditions, the removal rate of the filling layer 18 is lower than the removal rate of the bottom anti-reflection layer 15 and the sidewall structures. 17 , that is, under the same etching conditions, the filling layer 18 has a higher selectivity ratio to the bottom anti-reflection layer 15 and the spacer structure 17 . More preferably, in this embodiment, the filling layer 18 may include, but is not limited to, a nitride layer, that is, the material of the filling layer 18 may include, but is not limited to, nitride, such as silicon nitride. The selection ratio of the material of the filling layer 18 is higher than the selection ratio of the bottom anti-reflection layer 15 and the sidewall structure 17. When the bottom anti-reflection layer 15 and the sidewall structure 17 are removed by etching, The filling layer 18 can be made to remain so that self-alignment can be achieved when bit line contact holes need to be formed.
在步骤6)中，请参阅图16中的S26步骤及图31，刻蚀去除所述侧墙结构17、位于所述埋入式栅极字线区域163的所述硬掩膜层14，以于所述底部抗反射层15及所述硬掩膜层14内形成图形沟道19，所述图形沟道19定义出所述埋入式栅极字线的位置及形状。In step 6), referring to step S26 in FIG. 16 and FIG. 31, the spacer structure 17 and the hard mask layer 14 located in the buried gate word line region 163 are etched and removed to remove A patterned channel 19 is formed in the bottom anti-reflective layer 15 and the hard mask layer 14, and the patterned channel 19 defines the position and shape of the buried gate word line.
作为示例，可以采用但不仅限于干法刻蚀工艺刻蚀去除所述侧墙结构17、位于所述侧墙结构17正下方(即位于所述埋入式栅极字线区域163)的所述硬掩膜层14，刻蚀过程停止于所述垫层结构11，即所述垫层结构11作为刻蚀阻挡层。As an example, but not limited to, a dry etching process may be used to etch and remove the spacer structure 17 and the spacer structure 17 directly below the spacer structure 17 (ie, located in the buried gate word line region 163 ). For the hard mask layer 14 , the etching process stops at the pad layer structure 11 , that is, the pad layer structure 11 serves as an etching barrier layer.
在步骤7)中，请参阅图16中的S27步骤及图32至图33，去除所述填充层18及所述底部抗反射层15。In step 7), referring to step S27 in FIG. 16 and FIGS. 32 to 33 , the filling layer 18 and the bottom anti-reflection layer 15 are removed.
作为示例，去除所述填充层18及所述底部抗反射层15包括如下步骤：As an example, removing the filling layer 18 and the bottom anti-reflection layer 15 includes the following steps:
7-1)刻蚀去除所述底部抗反射层15，如图32所示；具体的，可以采用干法刻蚀工艺刻蚀去除所述底部抗反射层15；7-1) Etching and removing the bottom anti-reflection layer 15, as shown in FIG. 32; specifically, the bottom anti-reflection layer 15 can be etched and removed by using a dry etching process;
7-2)刻蚀去除所述位线接触区域162之外的所述第二硬掩膜层142，即去除除了所述填充层18正下方之外所述第二硬掩膜层142；具体的，可以依据所述填充层18作为掩膜层，采用但不仅限于干法刻蚀工艺刻蚀去除所述位线接触区域162之外的所述第二硬掩膜层142；及7-2) Etching and removing the second hard mask layer 142 other than the bit line contact region 162, that is, removing the second hard mask layer 142 except directly under the filling layer 18; specifically Alternatively, according to the filling layer 18 as a mask layer, the second hard mask layer 142 outside the bit line contact region 162 can be etched and removed by but not limited to a dry etching process; and
7-3)去除所述填充层18，如图33所示；具体的，可以采用但不仅限于干法刻蚀工艺去除所述填充层18。7-3) Remove the filling layer 18, as shown in FIG. 33; specifically, the filling layer 18 may be removed by but not limited to a dry etching process.
在步骤8)中，请参阅图16中的S28步骤及图34至图36，去除所述图形沟道19底部的所述垫层结构11，并去除所述位线接触区域162之外的所述硬掩膜层14。In step 8), referring to step S28 in FIG. 16 and FIG. 34 to FIG. 36 , the pad layer structure 11 at the bottom of the pattern channel 19 is removed, and all parts other than the bit line contact region 162 are removed. The hard mask layer 14 is described.
作为示例，去除所述图形沟道19底部的所述垫层结构11，并去除所述位线接触区域162 之外的所述硬掩膜层14包括如下步骤：As an example, removing the pad layer structure 11 at the bottom of the pattern channel 19 and removing the hard mask layer 14 outside the bit line contact region 162 includes the following steps:
8-1)去除所述图形沟道19底部的所述垫层结构11，如图34所示；具体的，依据所述硬掩膜层14刻蚀所述垫层结构11，以去除裸露的位于所述图形沟道19底部的所述垫层结构11；更为具体的，可以采用但不仅限于干法刻蚀工艺刻蚀位于所述图形沟道19底部的所述垫层结构11；8-1) Remove the pad layer structure 11 at the bottom of the pattern channel 19, as shown in FIG. 34; specifically, the pad layer structure 11 is etched according to the hard mask layer 14 to remove the exposed The pad layer structure 11 located at the bottom of the pattern channel 19; more specifically, the pad layer structure 11 located at the bottom of the pattern channel 19 may be etched by but not limited to a dry etching process;
8-2)去除所述位线接触区域162之外的所述第一硬掩膜层141，如图35所示；具体的，可以依据保留的所述第二硬掩膜层142作为掩膜，采用但不仅限于干法刻蚀工艺刻蚀去除所述位线接触区域162之外的所述第一硬掩膜层141；需要说明的是，去除所述第一硬掩膜层 141的过程中，刻蚀终止于所述垫层结构11，即以所述垫层结构11作为刻蚀阻挡层；及8-2) Remove the first hard mask layer 141 outside the bit line contact region 162, as shown in FIG. 35; specifically, the second hard mask layer 142 that remains can be used as a mask , using but not limited to dry etching process to etch and remove the first hard mask layer 141 outside the bit line contact region 162; it should be noted that the process of removing the first hard mask layer 141 , the etching is terminated at the pad structure 11, that is, the pad structure 11 is used as an etch stop; and
8-3)去除所述位线接触区域162的所述第二硬掩膜层142，如图36所示；具体的，可以采用但不仅限于干法刻蚀工艺去除位于所述位线接触区域162的所述第二硬掩膜层142；具体的，在去除所述第二硬掩膜层142时，不会对所述垫层结构11、位于所述位线接触区域162 的所述第一硬掩膜层141及所述半导体基底10造成刻蚀，即刻蚀去除所述第二硬掩膜层142 的刻蚀气体对所述垫层结构11、所述第一硬掩膜层141及所述半导体基底10的刻蚀去除速率非常小，几乎可以忽略不计；这样就可以确保在去除所述第二硬掩膜层142时，位于所述位线解除区域162的所述第一硬掩膜层141可以被保留下来。8-3) Remove the second hard mask layer 142 of the bit line contact region 162, as shown in FIG. 36; specifically, a dry etching process can be used but not limited to removing the bit line contact region the second hard mask layer 142 of A hard mask layer 141 and the semiconductor substrate 10 are etched, that is, the etching gas for removing the second hard mask layer 142 is etched to the pad layer structure 11 , the first hard mask layer 141 and the The etch removal rate of the semiconductor substrate 10 is very small, almost negligible; this ensures that when the second hard mask layer 142 is removed, the first hard mask located in the bit line release region 162 The film layer 141 may be left.
在步骤9)中，请参阅图16中的S29步骤及图37至图38，依据所述图形沟道19刻蚀所述半导体基底10，以于所述半导体基底10内形成埋入式栅极字线沟槽20。In step 9), please refer to step S29 in FIG. 16 and FIGS. 37 to 38 , the semiconductor substrate 10 is etched according to the pattern channel 19 to form a buried gate in the semiconductor substrate 10 Word line trenches 20 .
作为示例，可以采用但不仅限于干法刻蚀工艺刻蚀所述半导体基底10以于所述半导体基底10内形成所述埋入式栅极字线沟槽20。需要说明的是，在刻蚀过程中，可以依据保留的所述第一硬掩膜层141及所述垫层结构11作为掩膜刻蚀所述半导体基底10。As an example, the semiconductor substrate 10 may be etched by, but not limited to, a dry etching process to form the buried gate word line trenches 20 in the semiconductor substrate 10 . It should be noted that, in the etching process, the semiconductor substrate 10 may be etched according to the remaining first hard mask layer 141 and the pad layer structure 11 as masks.
在步骤10)中，请参阅图16中的S210及图39至图41，于所述埋入式栅极字线沟槽20内形成埋入式栅极字线21，所述埋入式栅极字线21的上表面低于所述半导体基底10的上表面。In step 10), referring to S210 in FIG. 16 and FIGS. 39 to 41 , a buried gate word line 21 is formed in the buried gate word line trench 20 . The buried gate The upper surface of the pole word line 21 is lower than the upper surface of the semiconductor substrate 10 .
作为示例，于所述埋入式栅极字线沟槽20内形成埋入式栅极字线21包括如下步骤：As an example, forming the buried gate word line 21 in the buried gate word line trench 20 includes the following steps:
10-1)于所述埋入式栅极字线沟槽20的侧壁及底部形成栅极氧化层211，如图39所示；具体的，可以采用但不仅限于热氧化工艺于所述埋入式栅极字线沟槽20的侧壁及底部形成所述栅极氧化层211；10-1) A gate oxide layer 211 is formed on the sidewall and bottom of the buried gate word line trench 20, as shown in FIG. 39; The gate oxide layer 211 is formed on the sidewalls and the bottom of the in-gate word line trench 20;
10-2)于所述埋入式栅极字线沟槽20内及所述垫层结构11表面形成栅极导电层212，所述栅极导电层212填满所述埋入式栅极字线沟槽20及所述位线接触区域162之间的间隙(即保留的所述第一硬掩膜层141之间的间隙)，并覆盖保留的所述硬掩膜层14(此时，保留的所述硬掩膜层14为所述第一硬掩膜层141)；10-2) A gate conductive layer 212 is formed in the buried gate word line trench 20 and on the surface of the pad structure 11 , and the gate conductive layer 212 fills the buried gate word The gap between the line trench 20 and the bit line contact region 162 (ie, the gap between the remaining first hard mask layers 141 ), and covers the remaining hard mask layer 14 (at this time, The remaining hard mask layer 14 is the first hard mask layer 141);
10-3)采用化学研磨(CMP)工艺去除部分所述栅极导电层212，使得保留的所述栅极导电层212的上表面与保留的所述硬掩膜层14(即如图40中的所述第一硬掩膜层141)的上表面相平齐，如图40所示；及10-3) Use a chemical polishing (CMP) process to remove part of the gate conductive layer 212, so that the remaining upper surface of the gate conductive layer 212 and the remaining hard mask layer 14 (ie, as shown in FIG. 40 ) The upper surface of the first hard mask layer 141) is flush, as shown in FIG. 40; and
10-4)回刻所述栅极导电层212，以去除位于所述垫层结构11表面的所述栅极导电层212，并去除部分位于所述埋入式栅极字线沟槽20内的所述栅极导电层212，以形成所述埋入式栅极字线21，如图41所示。需要说明的是，本示例中所述的“所述埋入式栅极字线21的上表面低于所述半导体基底10的上表面”严格意义上是指所述埋入式栅极字线21中的苏搜栅极导电层212的上表面低于所述半导体基底10的上表面。10-4) Etch back the gate conductive layer 212 to remove the gate conductive layer 212 located on the surface of the pad structure 11 , and remove part of the gate conductive layer 212 located in the buried gate word line trench 20 of the gate conductive layer 212 to form the buried gate word line 21, as shown in FIG. 41 . It should be noted that, in this example, "the upper surface of the buried gate word line 21 is lower than the upper surface of the semiconductor substrate 10" strictly refers to the buried gate word line The upper surface of the Soso gate conductive layer 212 in 21 is lower than the upper surface of the semiconductor substrate 10 .
作为示例，所述埋入式栅极字线21中的所述栅极导电层212的材料包括氮化钛、氮化钽及钨中的至少一种，即所述栅极导电层212的材料可以包括氮化钛、氮化钽或钨等低电阻率金属，也可以包括氮化钛、氮化钽及钨中的至少两种，即此时，所述栅极导电层212可以为氮化钛、氮化钽及钨至少两种材料组成的复合材料的导电层，也可以为包括氮化钛层、氮化钽层及钨层中的至少两层的导电层。As an example, the material of the gate conductive layer 212 in the buried gate word line 21 includes at least one of titanium nitride, tantalum nitride and tungsten, that is, the material of the gate conductive layer 212 It may include low resistivity metals such as titanium nitride, tantalum nitride or tungsten, and may also include at least two of titanium nitride, tantalum nitride and tungsten, that is, at this time, the gate conductive layer 212 may be nitrided The conductive layer of the composite material composed of at least two materials of titanium, tantalum nitride and tungsten may also be a conductive layer including at least two layers of titanium nitride layer, tantalum nitride layer and tungsten layer.
在步骤11)中，请参阅图16中的步骤S211及图42，于所述埋入式栅极字线沟槽20内及所述垫层结构11表面形成介质层22；所述介质层22填满所述埋入式栅极字线沟槽20并覆盖所述垫层结构11的表面。In step 11), please refer to step S211 and FIG. 42 in FIG. 16, a dielectric layer 22 is formed in the buried gate word line trench 20 and on the surface of the pad structure 11; the dielectric layer 22 The buried gate word line trenches 20 are filled and the surface of the pad structure 11 is covered.
作为示例，可以采用但不仅限于物理气相沉积工艺或化学气相沉积工艺形成所述介质层 22，所述介质层22可以包括但不仅限于氧化物层或氮化物层，即所述介质层22的材料可以包括但不仅限于氧化物或氮化物。具体的，所述氧化物可以包括氧化硅，所述氮化物可以包括氮化硅。该步骤中，保留的所述第一硬掩膜层141，所述第一硬掩膜层141定义出后续要形成的位线接触孔23的位置，可以在后续形成所述位线接触孔23实现自对准。As an example, the dielectric layer 22 may be formed by, but not limited to, a physical vapor deposition process or a chemical vapor deposition process, and the dielectric layer 22 may include, but is not limited to, an oxide layer or a nitride layer, that is, the material of the dielectric layer 22 Can include, but is not limited to, oxides or nitrides. Specifically, the oxide may include silicon oxide, and the nitride may include silicon nitride. In this step, the remaining first hard mask layer 141 defines the position of the bit line contact hole 23 to be formed later, and the bit line contact hole 23 can be formed later achieve self-alignment.
在步骤12中)，请参阅图16中的步骤S212及图43至图44，去除所述位线接触区域162 的所述硬掩膜层14并刻蚀所述半导体基底10，以于所述介质层22及所述半导体基底10内形成位线接触孔23，所述位线接触孔23的底部陷入于所述半导体基底10内。In step 12), please refer to step S212 in FIG. 16 and FIG. 43 to FIG. 44, the hard mask layer 14 of the bit line contact region 162 is removed and the semiconductor substrate 10 is etched, so that the A bit line contact hole 23 is formed in the dielectric layer 22 and the semiconductor substrate 10 , and the bottom of the bit line contact hole 23 is recessed into the semiconductor substrate 10 .
作为示例，可以采用干法刻蚀工艺刻蚀所述硬掩膜层14及所述半导体基底10以形成所述位线接触孔23，由于保留的所述第一硬掩膜层141已经预先定义出所述位线接触孔23的位置及形状，此时不需要光刻工艺就可以依据保留的所述第一硬掩膜层141刻蚀形成所述位线接触孔23，从而实现位线接触孔23的精确自对准。As an example, a dry etching process may be used to etch the hard mask layer 14 and the semiconductor substrate 10 to form the bit line contact hole 23, since the remaining first hard mask layer 141 has been predefined The position and shape of the bit line contact hole 23 can be obtained. At this time, the bit line contact hole 23 can be formed by etching according to the remaining first hard mask layer 141 without a photolithography process, so as to realize the bit line contact Precise self-alignment of holes 23.
需要说明的是，由于保留的所述第一硬掩膜层141下方具有垫层结构11，刻蚀去除所述第一硬掩膜层141时，位于所述第一硬掩膜层141正下方的所述垫层结构11也被一并去除。It should be noted that, because the remaining first hard mask layer 141 has the pad layer structure 11 , when the first hard mask layer 141 is removed by etching, it is located directly under the first hard mask layer 141 The cushion layer structure 11 of , is also removed together.
所述位线接触孔23除了位于所述介质层22内之外，还延伸至所述半导体基底10内，这样可以增大后续形成的位线接触与所述有源区13的接触面积，即增大后续形成的位线与所述有源区13的接触面积，从而减小接触电阻。In addition to being located in the dielectric layer 22, the bit line contact hole 23 also extends into the semiconductor substrate 10, so that the contact area between the subsequently formed bit line contact and the active region 13 can be increased, that is, The contact area between the subsequently formed bit line and the active region 13 is increased, thereby reducing the contact resistance.
需要说明的是，所述位线接触孔23延伸至所述有源区13的尺寸可以与所述位线接触孔23位于所述介质层22内的部分的尺寸相同，所述位线接触孔23延伸至所述有源区13的尺寸也可以大于所述位线接触孔23位于所述介质层22内的部分的尺寸。It should be noted that the size of the bit line contact hole 23 extending to the active region 13 may be the same as the size of the portion of the bit line contact hole 23 located in the dielectric layer 22 . The size of the portion 23 extending to the active region 13 may also be larger than the size of the portion of the bit line contact hole 23 located in the dielectric layer 22 .
在步骤13)中，请参阅图16中的步骤S213及图45至图46，于所述位线接触孔23内填充接触材料，以形成位线接触24。In step 13), please refer to step S213 in FIG. 16 and FIGS. 45 to 46 , filling the bit line contact hole 23 with a contact material to form the bit line contact 24 .
作为示例，于所述位线接触孔23内填充接触材料，以形成位线接触24可以包括如下步骤：As an example, filling the bit line contact hole 23 with a contact material to form the bit line contact 24 may include the following steps:
13-1)采用物理气相沉积工艺或化学气相沉积工艺于所述位线接触孔23内及所述介质层 22表面形成接触材料；13-1) adopt physical vapor deposition process or chemical vapor deposition process to form contact material in the bit line contact hole 23 and the surface of the dielectric layer 22;
13-2)采用化学机械研磨工艺去除位于所述介质层22表面的所述接触材料，保留于所述位线接触孔23内的所述接触材料即构成所述位线接触24。13-2) The contact material on the surface of the dielectric layer 22 is removed by chemical mechanical polishing, and the contact material remaining in the bit line contact hole 23 constitutes the bit line contact 24 .
作为示例，所述位线接触24的材料包括但不仅限于多晶硅。具体的，所述位线接触24 的材料可以包括掺杂多晶硅，以使得所述位线接触24导电。所述位线接触24作为后续形成的位线与所述有源区13相连接的结构。As an example, the material of the bit line contact 24 includes, but is not limited to, polysilicon. Specifically, the material of the bit line contact 24 may include doped polysilicon, so that the bit line contact 24 is conductive. The bit line contact 24 serves as a structure for connecting a subsequently formed bit line with the active region 13 .
实施例四Embodiment 4
请结合图17至图46，本实用新型还提供一种存储器结构，半导体基底10，所述半导体基底10内形成有浅沟槽隔离结构12，所述浅沟槽隔离结构12在所述半导体基底10内隔离出若干个间隔排布的有源区13；若干个间隔排布的埋入式栅极字线21，位于所述有源区13内，且所述埋入式栅极字线21的上表面低于所述半导体基底10的上表面；位线接触24，所述位线接触24位于所述半导体基底10上；及介质层22，所述介质层22位于所述埋入式栅极字线21的表面，且填满所述位线接触24之间的间隙。Please refer to FIGS. 17 to 46 , the present invention further provides a memory structure, a semiconductor substrate 10 , a shallow trench isolation structure 12 is formed in the semiconductor substrate 10 , and the shallow trench isolation structure 12 is on the semiconductor substrate A plurality of spaced active regions 13 are isolated in 10; a plurality of spaced buried gate word lines 21 are located in the active region 13, and the buried gate word lines 21 the upper surface of which is lower than the upper surface of the semiconductor substrate 10; the bit line contact 24, the bit line contact 24 is located on the semiconductor substrate 10; and the dielectric layer 22, the dielectric layer 22 is located on the buried gate The surface of the word line 21 is polarized, and the gap between the bit line contacts 24 is filled.
作为示例，所述半导体衬底10可以包括但不限于单晶硅衬底、多晶硅衬底、氮化镓衬底或蓝宝石衬底，另外，所述半导体衬底10为单晶衬底或多晶衬底时，还可以是本征硅衬底或者是轻微掺杂的硅衬底，进一步，可以为N型多晶硅衬底或P型多晶硅衬底。As an example, the semiconductor substrate 10 may include, but is not limited to, a single crystal silicon substrate, a polycrystalline silicon substrate, a gallium nitride substrate or a sapphire substrate. In addition, the semiconductor substrate 10 may be a single crystal substrate or a polycrystalline substrate When the substrate is used, it can also be an intrinsic silicon substrate or a lightly doped silicon substrate, and further, it can be an N-type polysilicon substrate or a P-type polysilicon substrate.
作为示例，所述浅沟槽隔离结构12可以通过在所述半导体衬底10内形成隔离沟槽后，再采用化学气相沉积或其他的沉积技术在所述隔离沟槽内沉积绝缘层而形成。所述浅沟槽隔离结构12的材料可以包括氮化硅或氧化硅等等。所述浅沟槽隔离结构12的截面形状可以根据实际需要进行设定，其中，在图46中以所述浅沟槽隔离结构12的截面形状包括倒梯形作为示例，但在实际示例中并不以此为限。需要说明的是，在所述隔离沟槽内沉积所述绝缘层时，若所述绝缘层填满所述隔离沟槽且覆盖所述垫层结构11的表面，此时需要采用化学机械研磨工艺去除所述垫层结构11表面的所述绝缘层。As an example, the shallow trench isolation structure 12 may be formed by forming an isolation trench in the semiconductor substrate 10 and then depositing an insulating layer in the isolation trench by chemical vapor deposition or other deposition techniques. The material of the shallow trench isolation structure 12 may include silicon nitride or silicon oxide, or the like. The cross-sectional shape of the shallow trench isolation structure 12 can be set according to actual needs, wherein the cross-sectional shape of the shallow trench isolation structure 12 includes an inverted trapezoid as an example in FIG. This is the limit. It should be noted that, when the insulating layer is deposited in the isolation trench, if the insulating layer fills the isolation trench and covers the surface of the pad layer structure 11, a chemical mechanical polishing process is required at this time. The insulating layer on the surface of the pad structure 11 is removed.
作为示例，所述浅沟槽隔离结构12可以在所述半导体衬底10隔离出的若干个所述有源区13可以为但不仅限于如图45所示的呈阵列排布。As an example, several of the active regions 13 that can be isolated from the semiconductor substrate 10 by the shallow trench isolation structure 12 can be, but not limited to, arranged in an array as shown in FIG. 45 .
作为示例，所述有源区13内形成有MOS器件(未示出)，所述MOS器件包括栅极、源极及漏极，其中，所述源极与所述漏极分别位于所述栅极相对的两侧。As an example, a MOS device (not shown) is formed in the active region 13, and the MOS device includes a gate electrode, a source electrode and a drain electrode, wherein the source electrode and the drain electrode are respectively located at the gate electrode very opposite sides.
作为示例，所述有源区13内还形成有深阱区域131，如图46所示；具体的，形成的所述深阱区域131的类型可以根据实际需要进行选择，可以根据实际需要选择为P型掺杂区域或N型掺杂区域。As an example, a deep well region 131 is also formed in the active region 13, as shown in FIG. 46; specifically, the type of the deep well region 131 formed can be selected according to actual needs, and can be selected according to actual needs as P-type doped regions or N-type doped regions.
作为示例，所述存储器结构还包括垫层结构11，所述垫层结构11位于所述埋入式栅极字线21及所述位线接触24之间的所述半导体基底10的表面。As an example, the memory structure further includes a pad structure 11 located on the surface of the semiconductor substrate 10 between the buried gate word line 21 and the bit line contact 24 .
作为示例，所述垫层结构11包括垫氧化层111及垫氮化层112，其中，所述垫氧化层位于所述半导体基底10的表面，所述垫氮化层112位于所述垫氧化层111的表面，如图46所示。所述垫层结构11作为去除后续形成的硬掩膜层的刻蚀终止层，可以有效防止移除所述硬掩膜层时等离子体对所述半导体基底10的等离子损伤；同时，所述垫层结构11还可以作为后续形成的栅极导电层平坦化处理的终止层。As an example, the pad structure 11 includes a pad oxide layer 111 and a pad nitride layer 112 , wherein the pad oxide layer is located on the surface of the semiconductor substrate 10 , and the pad nitride layer 112 is located on the pad oxide layer 111, as shown in Figure 46. The pad layer structure 11 is used as an etch stop layer for removing the hard mask layer formed subsequently, which can effectively prevent plasma damage to the semiconductor substrate 10 when the hard mask layer is removed; at the same time, the pad layer The layer structure 11 can also serve as a termination layer for the subsequent planarization of the gate conductive layer.
作为示例，所述埋入式栅极字线21包括栅极氧化层211及栅极导电层212，所述栅极导电层212位于所述有源区13内，所述栅极导电层212的上表面低于所述半导体基底10的上表面；所述栅氧化层211位于所述有源区13内，且位于所述栅极导电层212与所述半导体基底10之间。As an example, the buried gate word line 21 includes a gate oxide layer 211 and a gate conductive layer 212, the gate conductive layer 212 is located in the active region 13, and the gate conductive layer 212 has a The upper surface is lower than the upper surface of the semiconductor substrate 10 ; the gate oxide layer 211 is located in the active region 13 and between the gate conductive layer 212 and the semiconductor substrate 10 .
作为示例，所述埋入式栅极字线21中的所述栅极导电层212的材料包括氮化钛、氮化钽及钨中的至少一种，即所述栅极导电层212的材料可以包括氮化钛、氮化钽或钨等低电阻率金属，也可以包括氮化钛、氮化钽及钨中的至少两种，即此时，所述栅极导电层212可以为氮化钛、氮化钽及钨至少两种材料组成的复合材料的导电层，也可以为包括氮化钛层、氮化钽层及钨层中的至少两层的导电层。As an example, the material of the gate conductive layer 212 in the buried gate word line 21 includes at least one of titanium nitride, tantalum nitride and tungsten, that is, the material of the gate conductive layer 212 It may include low resistivity metals such as titanium nitride, tantalum nitride or tungsten, and may also include at least two of titanium nitride, tantalum nitride and tungsten, that is, at this time, the gate conductive layer 212 may be nitrided The conductive layer of the composite material composed of at least two materials of titanium, tantalum nitride and tungsten may also be a conductive layer including at least two layers of titanium nitride layer, tantalum nitride layer and tungsten layer.
作为示例，所述位线接触24的底部陷入于所述半导体基底10内。所述位线接触24的底部陷入所述半导体基底10内，可以增大所述位线接触24与所述有源区13的接触面积，从而增大所述位线25与所述有源区13的接触面积，降低接触电阻。As an example, the bottom of the bit line contact 24 is recessed into the semiconductor substrate 10 . The bottom of the bit line contact 24 is recessed into the semiconductor substrate 10 , which can increase the contact area between the bit line contact 24 and the active region 13 , thereby increasing the bit line 25 and the active region. 13 contact area, reduce contact resistance.
作为示例，所述位线接触24的材料包括但不仅限于多晶硅。具体的，所述位线接触24 的材料可以包括掺杂多晶硅，以使得所述位线接触24导电。所述位线接触24作为后续形成的位线与所述有源区13相连接的结构。As an example, the material of the bit line contact 24 includes, but is not limited to, polysilicon. Specifically, the material of the bit line contact 24 may include doped polysilicon, so that the bit line contact 24 is conductive. The bit line contact 24 serves as a structure for connecting a subsequently formed bit line with the active region 13 .
综上所述，本实用新型提供一种半导体结构及存储器结构，所述半导体结构的制备方法包括如下步骤：1)提供一半导体基底，于所述半导体基底的表面形成垫层结构；并于所述半导体基底及所述垫层结构内形成浅沟槽隔离结构，所述浅沟槽隔离结构于所述半导体基底内隔离出若干个间隔排布的有源区；2)于垫层结构的表面依次形成硬掩膜层、底部抗反射层及光刻胶层，其中，所述硬掩膜层、所述底部抗反射层及所述光刻胶层由下至上依次叠置，且所述光刻胶层中形成有第一开口图形，所述第一开口图形暴露出需要形成位线接触的位线接触区域及需要形成埋入式栅极字线的埋入式栅极字线区域；3)依据所述光刻胶层刻蚀所述底部抗反射层，将所述第一开口图形转移至所述底部抗反射层内，以于所述底部抗反射层内形成第二开口图形；4)于所述第二开口图形侧壁形成侧墙结构，所述侧墙结构定义出所述埋入式栅极字线区域的位置及形状，所述侧墙结构之外的所述第二开口图形定义出所述位线接触区域的位置及形状；及5)于所述侧墙结构之外的所述第二开口图形内形成填充层，其中，于相同的刻蚀条件下，所述填充层的去除速率小于所述底部抗反射层的去除速率及所述侧墙结构的去除速率。本实用新型的半导体结构及其制备方法，在形成侧墙结构及填充层时即定义出埋入式栅极字线及位线接触的位置及形状，在基于所述半导体结构制备埋入式栅极字线及位线接触时，不需要额外的光刻工艺来定义位线接触孔，从而可以避免光刻曝光偏移，确保位线接触的精确对准；同时，半导体结构的制备方法简单，工艺步骤简洁，节约材料成本和工艺成本；本实用新型的存储器结构及其制备方法，通过形成侧墙结构及填充层分别定义出埋入式栅极字线及位线接触的位置及形状，在形成位线接触孔时不需要额外的光刻工艺来定义位线接触孔，从而可以避免光刻曝光偏移，确保位线接触的精确对准；同时，存储器结构的制备方法简单，工艺步骤简洁，节约材料成本和工艺成本。In summary, the present invention provides a semiconductor structure and a memory structure, and a method for preparing the semiconductor structure includes the following steps: 1) providing a semiconductor substrate, and forming a pad structure on the surface of the semiconductor substrate; A shallow trench isolation structure is formed in the semiconductor substrate and the pad structure, and the shallow trench isolation structure isolates a plurality of spaced active regions in the semiconductor substrate; 2) On the surface of the pad structure A hard mask layer, a bottom anti-reflection layer and a photoresist layer are sequentially formed, wherein the hard mask layer, the bottom anti-reflection layer and the photoresist layer are sequentially stacked from bottom to top, and the photoresist layer is A first opening pattern is formed in the resist layer, and the first opening pattern exposes a bit line contact region that needs to form a bit line contact and a buried gate word line region that needs to form a buried gate word line; 3 ) etching the bottom anti-reflection layer according to the photoresist layer, and transferring the first opening pattern into the bottom anti-reflection layer to form a second opening pattern in the bottom anti-reflection layer; 4 ) forming a spacer structure on the sidewall of the second opening pattern, the spacer structure defines the position and shape of the buried gate word line region, the second opening outside the spacer structure The pattern defines the position and shape of the bit line contact area; and 5) a filling layer is formed in the second opening pattern outside the spacer structure, wherein, under the same etching conditions, the filling The removal rate of the layer is less than the removal rate of the bottom anti-reflection layer and the removal rate of the spacer structure. In the semiconductor structure and its preparation method of the present invention, when the sidewall structure and the filling layer are formed, the position and shape of the contact between the word line and the bit line of the buried gate are defined, and the buried gate is prepared based on the semiconductor structure. When the pole word line and the bit line are in contact, no additional photolithography process is needed to define the bit line contact hole, so that the photolithography exposure offset can be avoided, and the precise alignment of the bit line contact can be ensured; at the same time, the preparation method of the semiconductor structure is simple, The process steps are simple, and the material cost and the process cost are saved; the memory structure and the preparation method thereof of the present invention respectively define the position and shape of the contact of the buried gate word line and the bit line by forming the sidewall structure and the filling layer. When forming the bit line contact hole, no additional photolithography process is needed to define the bit line contact hole, so that the photolithography exposure offset can be avoided, and the precise alignment of the bit line contact can be ensured; at the same time, the preparation method of the memory structure is simple, and the process steps are concise , saving material cost and process cost.
上述实施例仅例示性说明本实用新型的原理及其功效，而非用于限制本实用新型。任何熟悉此技术的人士皆可在不违背本实用新型的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本实用新型所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本实用新型的权利要求所涵盖。The above-mentioned embodiments merely illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
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