CN209045531U - A kind of semiconductor chip package - Google Patents

Abstract

The present disclosure discloses a semiconductor chip packaging structure, which includes: a semiconductor chip; a wiring substrate having a wiring pattern composed of at least one trace and/or a pad; A bonding pad, at least a part of the redistribution structure is distributed on the wiring substrate; an encapsulation structure is used for encapsulating the semiconductor chip, the wiring substrate and the redistribution structure. The wiring substrate of the present disclosure includes features such as complex multi-circuit designs, which can be embedded in the assembled package structure, thereby improving the performance of the entire package structure, making the interconnection between the semiconductor chip and the routing circuit a internal structure, thus shortening the circuit path.

Description

A semiconductor chip packaging structure

This disclosure claims priority to patent application No. 10201707613W filed in Singapore on September 15, 2017, which is hereby incorporated by reference in its entirety.

technical field

The present disclosure relates to the field of semiconductor chip packaging, and in particular, to a semiconductor chip packaging structure.

Background technique

With the development of semiconductor technology, the size of the chip is getting smaller and smaller, and the I/O pin density on the chip surface is getting higher and higher, and the fan-out package comes into being. Pin fan-outs are low density package pins.

The existing fan-out packaging method mainly includes: providing a carrier board, arranging an adhesive layer on the carrier board, attaching the front side of the chip to the adhesive layer, plastic-sealing the chip, and then peeling off the adhesive layer and the carrier board, A redistribution layer is formed on the front side of the chip, solder balls are implanted, and dicing.

This traditional fan-out packaging method requires wiring after the chip is pasted, and board-level packaging needs to process multiple layers of high-density wiring at one time, so the packaging process is difficult to control and will affect the yield after packaging; in order to achieve chip packaging Due to the miniaturization of the chip, there will be fine wiring patterns formed with high density in the rewiring layer, and the fine wiring patterns are prone to open circuit or short circuit problems in the wiring layer; in addition, if the internal circuit structure of the chip is complex, it needs to be formed on the front of the semiconductor chip. Therefore, the wiring is difficult because the surface area of the semiconductor chip is too small. In addition, the wiring is too dense and the wiring is easy to fail, resulting in a low yield of the product. In this case, the product is also easily damaged during use.

Utility model content

(1) Technical problems to be solved

In order to overcome the above-mentioned defects in the prior art, the present disclosure proposes a semiconductor chip packaging structure.

According to one aspect of the present disclosure, a semiconductor chip packaging structure is proposed, which includes: a semiconductor chip; a wiring substrate having a wiring pattern composed of at least one trace and/or a pad; and a rewiring structure for drawing out the A bonding pad on the front side of a semiconductor chip, at least a part of the rewiring structure is distributed on the wiring substrate; an encapsulation structure is used to encapsulate the semiconductor chip, the wiring substrate and the rewiring structure.

According to another aspect of the present disclosure, a semiconductor chip packaging structure is also proposed, including: a first chip packaging structure; at least one second chip packaging structure, the second chip packaging structure including a packaged chip and a lead-out The rewiring structure of the bonding pad on the front side of the chip; wherein, at least one rewiring structure of the second chip packaging structure is electrically connected to the connection layer of at least one wiring substrate of the first chip packaging structure.

(3) Beneficial effects

In the semiconductor chip packaging structure disclosed in the present disclosure, since the wiring substrate is provided, the wiring that needs to be completed on the front side of the semiconductor chip to be packaged can be transferred to the wiring substrate. The same, including features such as complex multi-circuit designs, which can be embedded in the assembled package structure, thereby improving the performance of the entire package structure, making the connection between the semiconductor chip and the routing circuit (routing circuit). The interconnection becomes an internal structure, thereby shortening the circuit path; in addition, further, the fine wiring in the rewiring layer is transferred to the wiring substrate, which reduces the probability of disconnection or short circuit of the rewiring layer, and can reduce the rewiring. The number of layers can achieve the purpose of miniaturization of the package; further, a pre-formed wiring substrate can be provided, which can be tested first and then packaged, and the defective units can be marked to ensure that the known defective units are not used, which is suitable for high complexity. , The packaging process with high integration density can not only improve the yield of the packaging process, but also effectively further reduce the unnecessary cost of manufacturing materials.

Description of drawings

1 is a flow chart of forming a semiconductor chip package structure of the present disclosure;

2 is a cross-sectional view of a first carrier plate according to the present disclosure;

FIG. 3 is a cross-sectional view of an adhesive layer on a first carrier board according to the present disclosure;

FIG. 4 is a cross-sectional view after mounting a semiconductor chip on the first carrier according to the present disclosure;

5 is a schematic plan view of setting position marks on the first carrier plate according to the present disclosure;

6a-6c are schematic diagrams of a wiring substrate according to an embodiment of the present disclosure;

7 is a cross-sectional view of a first carrier after mounting a wiring substrate and a semiconductor chip according to an embodiment of the present disclosure;

8 is a cross-sectional view after forming a first encapsulation layer according to an embodiment of the present disclosure;

9a and 9b are schematic diagrams of thinning the encapsulation layer according to an embodiment of the present disclosure;

9c is a schematic diagram of peeling off the first carrier plate and the adhesive layer according to an embodiment of the present disclosure;

10 is a flowchart of forming a redistribution structure according to an embodiment of the present disclosure;

11 is a cross-sectional view after forming a first insulating layer according to an embodiment of the present disclosure;

12 is a cross-sectional view after forming an opening in the first insulating layer according to an embodiment of the present disclosure;

13 is a cross-sectional view after forming filled vias and patterned lines according to an embodiment of the present disclosure;

14 is a cross-sectional view of forming a stud on a patterned circuit according to an embodiment of the present disclosure;

15 is a cross-sectional view after forming an outermost insulating layer according to an embodiment of the present disclosure;

16 is a cross-sectional view after forming two redistribution layers according to another embodiment of the present disclosure;

17, 18a and 18b are schematic diagrams of cutting a package structure according to an embodiment of the present disclosure;

19 is a cross-sectional view of a package structure formed according to an embodiment of the present disclosure soldered to a circuit board;

20 and 21 are schematic diagrams of connecting other circuit boards through a routing layer of a wiring substrate according to an embodiment of the present disclosure.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below with reference to the specific embodiments and the accompanying drawings.

The present disclosure is mainly proposed to address the problems in the prior art semiconductor chip board-level packaging structures and packaging methods that it is difficult to perform wiring on the front side of the semiconductor and is likely to cause damage to the semiconductor chip. The semiconductor chip packaging structure of the present disclosure is provided with a wiring substrate, and at least part of the wiring on the front side of the semiconductor chip and the rewiring layer can be led to the wiring substrate for wiring, which reduces the difficulty of wiring and increases the stability of the circuit. At the same time, the number of re-wiring layers is reduced, thereby reducing the package volume and improving the performance of the packaged chip; at the same time, the wiring substrate can be tested first, and the defective units can be eliminated and marked to screen out the non-defective units. This in turn improves the overall packaging yield.

FIG. 1 is a flow chart of forming a semiconductor chip package structure proposed in accordance with the present disclosure. Referring to Figure 1, include:

Step S1 , providing the first carrier board 100 .

As shown in FIG. 2 , the first carrier board 100 is preferably a square or rectangular panel, including a first surface and a second surface, the first surface is the upper surface of the first carrier board 100 , and the second surface is the upper surface of the first carrier board 100 . The lower surface, there is no substantial difference between the two surfaces, and the first surface and the second surface are referred to here only to distinguish the two. The first carrier 100 may be a metallic material, such as copper or steel, or a non-metallic material, such as a polymer, or a silicon wafer. At least one mark position is formed on the first surface of the first carrier board 100 by laser or mechanical engraving or drilling, or by chemical etching, and the positions of these marks correspond to the positions where the chip is arranged on the first carrier board 100. Each mark corresponds to the position of one semiconductor chip, and the purpose of setting the mark is to facilitate accurate placement of the semiconductor chip 300 on the first carrier board 100 . FIG. 5 shows a schematic diagram of chip placement on the first carrier board 100 .

In step S2 , the adhesive layer 200 is formed on the surface of the first carrier board 100 .

As shown in FIG. 3 , an adhesive layer 200 is formed on the first surface of the first carrier 100 , and the semiconductor chip 300 can be mounted on the first surface of the carrier 100 through the adhesive layer 200 . The adhesive layer 200 can be made of an easily peelable material, so that the carrier board 100 and the chip 300 packaged on the first surface thereof can be peeled off later, for example, a thermal separation material that can lose its adhesiveness by heating can be used. Alternatively, the adhesive layer 200 may adopt a two-layer structure, a thermal separation material layer and a chip attach layer. The thermal separation material layer is pasted on the carrier board 100 and loses its adhesiveness when heated, and then can be peeled off from the carrier board 100 , and The die attach layer is used for attaching the semiconductor chip 300; after the semiconductor chip 300 is peeled off from the carrier board 100, the die attach layer thereon can be removed by chemical cleaning; The adhesive layer 200 is formed.

In step S3 , at least one semiconductor chip 300 is arranged on a predetermined position of the first carrier board 100 .

As shown in FIG. 4 and FIG. 5 , at least one semiconductor chip 300 is mounted on the first surface 101 of the first carrier board 100 , with the backside of the semiconductor chip 300 facing upward and the front side facing the first carrier board 100 .

The semiconductor chip 300 is formed by thinning and cutting a semiconductor wafer. The front surface of the semiconductor chip 300 is composed of conductive electrodes drawn from the internal circuit of the chip to the surface of the chip, and bonding pads or connection points are prepared on these conductive electrodes.

Before the adhesive layer 200 is formed, the first surface 101 of the first carrier board 100 is provided with a bonding position 102 of the semiconductor chip 300 in advance. After the bonding layer 200 is formed, the semiconductor chip 300 is bonded on the first carrier board 100 . Predetermined location 102 . The semiconductor chip 300 is also provided with an alignment mark, so as to be aligned with the pasting position 102 on the first carrier board 100 when pasting. Each semiconductor chip 300 corresponds to a predetermined position 102 . In one packaging process, there may be at least one semiconductor chip 300 , that is, at least one semiconductor chip 300 is mounted on the first carrier board 100 at the same time for packaging, and after the packaging is completed, it is cut into at least one package body, one package body At least one semiconductor chip 300 may be included, and the position of the at least one semiconductor chip 300 may be set according to actual product requirements.

In step S4, a pre-formed wiring substrate 400 is provided.

6a is a cross-sectional view of the wiring board, and FIGS. 6b and 6c are plan views of the wiring board. 6a, 6b and 6c, preferably, the size and shape of the wiring substrate 400 are the same as those of the first substrate 100. During the packaging process, both the wiring substrate 400 and the semiconductor chip 300 are attached to the first substrate 400 through an adhesive layer. On the first surface 101 of the substrate 100, at least one opening 401 is set on the wiring substrate 400, and the semiconductor chip 300 is set at the opening position during mounting, and if there are other components, it needs to be mounted on the first surface through the adhesive layer 200. If the carrier board 100 is used, the wiring substrate 400 also needs to have openings 402 for accommodating these components. The present disclosure does not limit the mounting sequence. The semiconductor chip 300 may be mounted first and then the adhesive layer 200 may be mounted, or vice versa.

In the actual packaging process, it is possible that the area of the first carrier board 100 is relatively large, while the size of the wiring substrate 400 is relatively small. It is also possible to use two or more wiring substrates 400 to be spliced on the first carrier board 100 . is the same size as the surface area of the first carrier plate 100 . At least one opening 401 is provided on each wiring substrate 400 for accommodating the semiconductor chip 300, and other openings 402 may be provided for arranging other components.

For example, when the size of the first substrate 100 is 900cm*900cm, one wiring board with a size of 900cm*900cm may be used, nine wiring boards with a size of 300cm*300cm, or nine wiring boards with a size of 100cm*900cm may be used As the wiring board 400, one wiring board 400 of 100 cm*900 cm and four wiring boards 400 of 200 cm*900 cm may be used.

The selection of the wiring substrate 400 can be determined according to actual needs, and is not limited to the various situations listed in the present disclosure. However, no matter how many wiring substrates 400 are used, each wiring substrate 400 has at least one opening 401 for accommodating the semiconductor chip 300 . In the wiring substrate 400 shown in Fig. 6b, the upper opening 401 is used only for accommodating the semiconductor chip 300, and the upper opening 401 of the wiring substrate 400 shown in Fig. 6c is used for accommodating the semiconductor chip 300, and the opening 402 is used for accommodating other components. 6b and 6c are only exemplary, and the number and shape of the openings 401 and 402 need to be set according to the actual situation of the circuit.

The wiring substrate 400 may include a plurality of identical or different substrate units, each of which corresponds to at least one semiconductor chip 300 .

Each wiring substrate 400 includes at least one routing layer 403 and at least one connection layer 404 .

In the example shown in FIG. 6 a , the wiring substrate 400 has two upper and lower routing layers 403 and 404 , and the upper and lower routing layers 403 and 404 are connected by a connection layer 405 . Preferably, the connection layer 405 includes at least one solder post or a via hole filled with conductive material, and two ends of the solder post or the via hole filled with the routing layers 403 and 404 are respectively connected. The position of the opening 401 is used for arranging the semiconductor chip 300, and the position of the opening 402 is used for arranging other components.

The wiring board 400 may use existing products, or may be customized. There are wiring patterns on the routing layers 403 and 404, and the wiring patterns include traces and/or pads. If it is a customized wiring substrate, it is arranged on the wiring substrate according to the wiring requirements of the semiconductor chip 300. The wiring pattern is designed in advance. If the product is purchased for sale, the wiring pattern on the wiring substrate is standardized and designed, and usually only part of the traces and/or pads in the wiring pattern can be used.

The pre-provided wiring substrate can include at least part of the wiring in the rewiring layer, which reduces the difficulty of wiring, increases the stability of the circuit, and reduces the number of wiring layers, thereby reducing the package volume and improving the performance of the packaged chip. ; Further, the wiring substrate is provided in advance to test the wiring substrate, and the defective packaging units can be selected and marked, so as to screen out the non-defective packaging units, thereby improving the overall packaging yield.

The front surface of the semiconductor chip 300 is composed of conductive electrodes drawn from the internal circuits of the chip to the surface of the chip, and solder pads and/or connection points are prepared on these conductive electrodes. In the packaging process of the semiconductor chip 300 , in order to realize the predetermined function of the packaging structure, optionally, it is also necessary to establish electrical connections between some of the pads or connection points. Then at least one solder pad and/or connection point needs to be drawn out of the package for connection with other circuit elements. This process is the rewiring process of the semiconductor chip.

Rewiring in the prior art is done on the front side of the semiconductor chip. The rewiring of the present disclosure is implemented at least in part on a wiring substrate.

In step S5 , the wiring substrate 400 is arranged on the first carrier board 100 .

FIG. 7 shows a cross-sectional view of the wiring substrate 400 after the wiring substrate 400 is disposed on the first carrier board 100 . In this step, the wiring substrate 400 is aligned on the first carrier board 100 by an alignment mark (the mark is not shown in the figure) formed in advance on the first carrier board 100 and the wiring substrate 400, and is bonded by bonding The layer 200 adheres the wiring substrate 400 to the first carrier board 100 .

Since the semiconductor chip 300 has already been pasted on the adhesive layer 200 , when the wiring substrate 400 is to be pasted, it is necessary to ensure that the wiring substrate 400 does not touch the semiconductor chip 300 . As shown in FIG. 7 , an opening has been formed in the wiring substrate 400 in advance. 401 , the opening area can accommodate the semiconductor chips 300 , and each semiconductor chip 300 is aligned with the opening 401 of the corresponding wiring substrate 400 . Alternatively, the wiring board 400 may be mounted first, and then the semiconductor chip 300 may be mounted.

In order to more conveniently attach the wiring substrate 400 to the first carrier board 100, a temporary support plate may be provided, an adhesive layer may be formed on the surface thereof, and the wiring substrate 400 may be attached to the temporary support plate by sticking During the installation process, one side of the wiring substrate 400 faces the upper surface of the first carrier board 100. Since the surface area of the temporary support board is the same as that of the first carrier board 100 and the shape is the same, aligning and contacting the two can The wiring substrate 400 is attached to the adhesive layer 200 , then the temporary support plate is peeled off, and the adhesive layer on the wiring substrate 400 is removed, and the attachment of the wiring substrate 400 is completed.

The temporary support plate and the temporary adhesive layer may be of the same material as the first carrier plate 100 and the adhesive layer 200 . In addition, the temporary support plate may also be a glass plate, and the temporary adhesive layer may also be an ultraviolet adhesive layer, which loses its viscosity when exposed to ultraviolet light, so that the temporary support plate can be peeled off.

According to the above description, the wiring substrate 400 is firstly attached to the temporary support plate and then transferred to the first carrier plate 100 .

In addition, the wiring substrate 400 can also be mounted on the first carrier board 100 after being held by a vacuum tool and pressed, so as to ensure that the mounting is complete.

Step S6 , an encapsulation layer 500 (Encapsulation layer) is formed on the first carrier board 100 .

FIG. 8 shows a cross-sectional view after the encapsulation layer 500 is added to the first carrier board 100 . When the encapsulation layer 500 is formed, the encapsulation material fills the opening on the wiring substrate 400 and encapsulates at least one semiconductor chip 300 and the wiring substrate 400 . 8, the encapsulation layer 500 encapsulates the back surface of at least one semiconductor chip 300, the upper surface of the wiring substrate 400, and the gap between the wiring substrate 400 and the semiconductor chip 300, the upper surface of which is a flat surface. The encapsulation layer 500 has an upper surface 501 .

The encapsulation layer 500 can be formed by lamination epoxy resin film or ABF (Ajinomoto buildup film), or by injection molding, compression molding or transfer of epoxy resin compound. Formed by transfer molding. The encapsulation layer 500 includes a first surface 501 (the upper surface shown in FIG. 10 ) opposite to the first carrier board, which is substantially flat and parallel to the surface of the first carrier board 100 .

In step S7, the first surface 501 of the encapsulation layer 500 is thinned.

In order to reduce the thickness of the final encapsulated product, the encapsulation layer 500 needs to be thinned, which can be thinned by mechanically grinding or polishing the first surface 501. FIG. 9a is a schematic diagram of thinning the encapsulation layer 500, and FIG. 9b It is a structural diagram after the encapsulation layer 500 is thinned. The thickness of the encapsulation layer 500 may be thinned to the upper surface of the wiring substrate 400 , thereby exposing the traces and pads of the wiring substrate 400 . In this thinning step, the wiring substrate is not damaged as much as possible, which requires that the wiring substrate is formed of a grindable material, and the wiring pattern (wiring pattern) is exposed on the surface of the wiring substrate. Although the wiring pattern is partially thinned, it is not affect its performance. According to the example shown in the figure, the upper routing layer 404 of the wiring substrate 400 has a wiring pattern formed by traces and pads, and the thinning step does not impair the performance of the wiring pattern. The wiring substrate described in the figure has two routing layers, a lower layer 403 and an upper layer 404 .

In step S8 , the first carrier 100 is peeled off from the encapsulation layer 500 .

9c shows a schematic diagram of peeling off the first carrier 100 from the encapsulation layer 500. After peeling the first carrier 100, the front surface 301 of the semiconductor chip 300, the lower surface 502 of the encapsulation layer 500 and the lower surface of the wiring substrate 400 are exposed . In this step, the first and first carrier board 100 can be directly mechanically peeled off, but the encapsulation layer 500 is easily damaged. Therefore, preferably, the adhesive layer 200 is a thermal separation material, and by heating, the adhesive layer 200 is made of The thermal separation material reduces the viscosity after being heated, and then peels off the first carrier plate 100 without damaging the encapsulation layer 500 .

Step S9, forming a rewiring structure.

11-16 show schematic diagrams of forming a redistribution structure after the first carrier 100 is peeled off.

FIG. 10 is a flowchart of forming a redistribution structure in a semiconductor chip packaging method according to the present disclosure; as shown in FIG. 10 , step S9 further includes:

In step S901, a first insulating layer 600 is formed.

11 , after peeling off the first carrier board 100 , a first insulating layer 600 is formed on the position of the first carrier board 100 , that is, the front surface of the semiconductor chip 300 , the wiring substrate 100 and the lower surface of the encapsulation layer 500 . FIG. 11 is a cross-sectional view after the first insulating layer 600 is formed. The insulating layer 600 covers the front surface of the semiconductor chip 300, the wiring substrate 100 and the lower surface of the encapsulation layer 500. The first insulating layer 600 is formed by coating paste, spraying (fluid) or lamination film, etc. The preferred material may be ABF (Ajinomoto Buildup Film) Insulating film, polyimide (polyimide) or lead monoxide (PBO). The first insulating layer 600 needs to be firmly adhered to the entire surface, completely covering the lower surface of the wiring substrate 400, the front surface of the semiconductor chip 300, and the lower surface of the encapsulation layer 500, preferably after the first insulating layer 600 is disposed. A curing process is carried out, for example, high temperature or ultraviolet curing can be used.

The insulating layer 600 is formed to protect the front surface of the semiconductor chip 300 and the surface of the wiring substrate 400, and also to provide a flat surface for subsequent processes.

Step S902 , at least one opening 601 is formed on the first insulating layer 600 .

As shown in FIG. 12 , at least one opening 601 is provided on the first insulating layer 600 . The openings 601 are used for routing the bonding pads on the front surface of the semiconductor chip 300 to the routing layer 403 of the wiring substrate 400, and to facilitate circuit connection between the bonding pads. Therefore, at least one opening 601 is positioned at a position corresponding to at least one bonding pad on the front surface of semiconductor chip 300, and/or positioned at a position corresponding to at least one trace and/or bonding pad of routing layer 403.

Through the openings 601 , the bonding pads on the front side of the semiconductor chip 300 can be routed to the traces and/or bonding pads on the routing layer 403 of the circuit substrate 400 , and the semiconductor chip 300 can be realized through the wiring pattern on the routing layer 403 . wiring.

The present disclosure does not limit the shape of the opening 601, which may be a circle, an ellipse, or a linear shape. The first insulating layer 600 can be patterned and at least one opening 601 is formed by using photolithography using mask exposure to pattern, in this case, the material of the first insulating layer 600 is a photosensitive material. It is also possible to directly image the first insulating layer 600 by laser irradiation, and form the openings 601 in sequence (one opening at a time, and then sequentially). In this case, the material of the first insulating layer 600 is laser reactive. (laser-reactive) material.

Step S903 , the wiring is completed by forming at least one filled via 602 and patterned traces 603 .

In order to complete the wiring of the semiconductor chip 300 through the wiring substrate 400, it is necessary to wire the pads on the front side of the semiconductor chip 300 to the traces and/or pads corresponding to the wiring substrate 400, that is, to connect the first insulating layer 600 to the semiconductor chip 300. The openings 601 corresponding to the bonding pads of the chip 300 are electrically connected to the openings 601 corresponding to the traces and/or bonding pads of the wiring substrate 400 .

Therefore, in step 903, as shown in FIG. 13, firstly, a conductive material (eg, copper) is filled into the opening 601 of the first insulating layer 600, which needs to be completely filled, thereby forming the filled via hole 602. Additive electroplating process (semi-additive electrolytic plating process) to achieve filling. These filled vias 602 are physically and electrically connected to the pads of the semiconductor chip 300 and the traces/pads of the wiring substrate 400 . Then, according to actual circuit design requirements, the filled vias 602 that need to be electrically connected are electrically connected on the surface of the first insulating layer 600 through conductive materials, thereby forming patterned lines 603 on the surface of the first insulating layer 600 . The form of the patterned circuit 603 shown in FIG. 13 is only exemplary, and its specific form needs to be designed according to the specific function to be implemented by the packaged semiconductor chip, and is not limited to the situation shown in FIG. 13 .

In this way, it can be realized but not limited to the following situations: the front side of the semiconductor chip has first and second filled vias that need to be electrically connected to each other, and the routing layer 403 is provided with third and fourth filled vias at corresponding positions The holes, the third and fourth filled vias are electrically connected by traces on the routing layer 403, and the first filled vias can be electrically connected to the third filled vias by using patterned lines on the surface of the first insulating layer , the second filled via is electrically connected to the third filled via, thereby realizing the electrical connection between the first and the second filled via, and transferring the rewiring that needs to be completed on the front side of the semiconductor chip in the prior art onto the wiring board.

In the present disclosure, the filled vias corresponding to the semiconductor chip 300 may be all electrically connected to the filled vias corresponding to the wiring substrate 400 , or may be partially connected. When partially connected, the front surface of the semiconductor chip 300 may also be partially reconnected. wiring.

The first insulating layer 600 can be chemically treated to further improve the adhesion to the patterned lines 603, especially those exposed surfaces in contact with the patterned lines 603 are chemically treated to further improve the adhesion to the patterned lines 603. adhesion.

Step S904 , forming pads or bumps 604 and a second insulating layer 605 on the patterned circuit 603 .

According to step S904, after the wiring of the semiconductor chip 300 is completed, at least one bonding pad needs to be drawn out to facilitate connection with other circuit elements.

As shown in FIG. 14 , at least one pad or bump 604 is formed on the patterned circuit 603 by photolithography or electroplating, and the pad or bump 604 is made of a conductive material (such as metal). The shape is preferably a circle, but can also be other shapes, such as a rectangle or a square, etc. The shape and size can be set according to the actual situation, which is not limited in the present disclosure. The pads or bumps 604 are physically and electrically connected to the patterned lines 603 .

A second insulating layer 605 is formed on the first insulating layer 600 . The second insulating layer 605 completely encapsulates the patterned circuit 603 and has a thickness that can encapsulate the periphery of the pad or the bump 604 , and the surface of the pad or bump 604 is exposed. , to facilitate electrical connection with other circuits. The second insulating layer may be formed by coating paste, spraying (fluid), or lamination film, etc., and preferably the same material as the first insulating layer 600 is used, For example, ABF (Ajinomoto Buildup Film) insulating film, polyimide (polyimide) or lead monoxide (PBO).

If the second insulating layer 605 is the last layer, other materials such as solder mask or epoxy molding compound may be used, preferably by curing, such as high temperature or UV curing.

The example shown in FIG. 15 forms a first redistribution layer formed of a first insulating layer 600, openings 601, filled vias 602, and patterned traces 603. However, the present disclosure is not limited to this, and according to actual wiring requirements, a second rewiring layer, a third rewiring layer, . Similar to the wiring layer, for example, forming the second redistribution layer includes: forming a second insulating layer on the first insulating layer 600 in the same manner as forming the first insulating layer 600, the second insulating layer encapsulating the patterned circuit 603, At least one second opening is formed on the second insulating layer at a position corresponding to the patterned line 603, the second opening is filled with a conductive material to form a second filled via, and the second filled via is electrically connected to the A second patterned line is formed on the second insulating layer, at least one second pad or bump is formed on the second patterned line, a third insulating layer is formed on the second insulating layer as the outermost insulating layer, the third The insulating layer encapsulates the second patterned circuit and the periphery of the second pad or the bump, and exposes the surface of the second pad or bump.

The third redistribution layer, . . . , the Nth redistribution layer can also be formed by a similar method.

After the required number of rewiring layers are formed, the outermost insulating layer is formed, thereby completing the package structure.

Step S10, dividing the assembly structure into at least one packaging unit.

A preformed wiring substrate is provided first, and then a rewiring process is performed on the chip. Since the wiring substrate includes some wiring patterns of the rewiring layer, the probability of chip damage can be effectively reduced.

In this step, as shown in FIG. 17 , along the dividing line 607 , cutting is performed by laser or mechanical means to divide the assembled structure into at least one package unit, each package unit including at least one semiconductor chip 300 . Figure 18b shows a cross-sectional view of the diced package unit, wherein the structure of 18b has two insulating layers.

19 shows a schematic diagram of the package unit in use. During use, the conductive pads or bumps 604 on the package unit are soldered to the substrate or circuit board 800 through solder 700, and then connected with other circuit components.

Referring to the examples described in the drawings of the present disclosure, the wiring substrate 400 includes routing layers 403 and 404 , and the routing layers 403 and 404 are connected by connection layers. The routing layers 403, 404 are individually distributed with patterned lines formed by traces and/or pads.

20 and 21 illustrate a package-on-package structure suitable for use in the present disclosure. 20, when the top surface of the wiring substrate 400 is exposed, active and/or passive components 405 may be connected to patterned lines on the routing layer 404 of the wiring substrate 400. As shown in the package structure unit 10 ″ shown in FIG. 21 , the second package unit can also be attached to the routing layer 404 of the wiring substrate 400 of the first package unit to realize the stacking package of the package units, which can be attached by solder 406

The semiconductor chip package structure proposed in the present disclosure is obtained by the above method.

FIG. 18a illustrates a semiconductor chip package structure according to an embodiment of the present disclosure. 18a, the semiconductor chip package structure includes: a semiconductor chip 300, the front surface of which is composed of conductive electrodes drawn from the internal circuit of the chip to the surface of the chip, on which pads or connection points are prepared; a wiring substrate 400, which has A wiring pattern formed by at least one trace and/or a pad; the encapsulation layer 500 is used to encapsulate the semiconductor chip 300 and the wiring substrate 400 .

A rewiring structure is formed on the lower surface of the encapsulation layer 500 , the lower surface of the wiring substrate 400 , and the front surface of the semiconductor chip 300 . The rewiring structure is used for rewiring the semiconductor chip, and at least a part of the rewiring structure is distributed on the wiring substrate.

In the embodiment shown in FIG. 18a, the re-wiring structure has one wiring layer, that is, a first wiring layer, the first wiring layer includes a first insulating layer 600, and at least one wiring layer is disposed on the first insulating layer 600 A first opening 601, the position of the first opening corresponds to at least one bonding pad on the front surface of the semiconductor chip 300, and corresponds to at least one trace and/or bonding pad of the wiring substrate 400, the at least one first opening The first filled via hole 602 is filled with a conductive material, and the first insulating layer has a first filled via hole 602 formed of a conductive material for electrically connecting two or more first filled via holes. A patterned circuit 603 . The first patterned circuit 603 includes at least one conductive bump. The wiring structure includes a second insulating layer 605, the second insulating layer encapsulates the first wiring layer and the conductive bumps, and exposes the surfaces of the conductive bumps. In this embodiment, the second insulating layer is the outermost layer.

The wiring layer of the present disclosure is not limited to one layer, and an Nth wiring layer may be formed on the first wiring layer in sequence, where N is greater than or equal to 2, and the Nth wiring layer includes an Nth insulating layer, an Nth opening, an Nth Filling the via hole and the Nth patterned line, when the Nth wiring layer is the last wiring layer, the Nth patterned line includes at least one conductive bump, and the wiring structure further includes an N+1th insulating layer. An N+1 insulating layer encapsulates the Nth wiring layer and the conductive bump, and exposes the surface of the conductive bump. The Nth wiring layer is formed in a manner similar to that of the first wiring layer.

FIG. 16 shows the case where N is 2, there are two wiring layers, and the third insulating layer 606 is the outermost insulating layer.

The wiring substrate 400 includes at least one routing layer 403, and the at least one routing layer includes at least one wiring pattern formed by traces and/or pads. In another embodiment, if the wiring substrate 400 includes two or more routing layers 403, 404, the wiring substrate further includes at least one connecting layer 405, and one of the two or more routing layers 403, 404 are connected to each other through the at least one connecting layer. Preferably, the connection layer includes at least one solder post or a via hole filled with conductive material, and two ends of the solder post or the via hole filled are respectively connected to different routing layers in the wiring substrate.

According to yet another aspect of the present disclosure, a stacked chip package structure is also proposed, including: a first chip package structure; at least one second chip package structure, wherein the second chip package structure includes packaged chips and a A rewiring structure for drawing out the bonding pads on the front side of the chip; wherein, at least one rewiring structure of the second chip packaging structure is electrically connected to a connection layer of at least one wiring substrate of the first chip packaging structure. The redistribution structure of the second chip package structure includes a redistribution layer and conductive bumps, the conductive bumps are used to lead the redistribution layer from the chip package structure, and the conductive bumps are connected to the first chip package. The pads or connection points on the connection layer of the structured wiring substrate are electrically connected. The first chip package structure and the second package structure can be fabricated using the methods described above.

The semiconductor packaging structure of the present disclosure can be prepared by the semiconductor packaging method described above, and the specific process is not repeated here. However, the present disclosure is not limited thereto, and semiconductor package structures with the same structure as those of the present disclosure prepared by methods different from the present disclosure all belong to the protection scope of the present disclosure.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included within the protection scope of the present disclosure.

Claims (14)

1. A semiconductor chip package structure, which includes a semiconductor chip, is characterized by further comprising: a wiring substrate having a wiring pattern constituted by at least one trace and/or pad; the rewiring structure is used for leading out a welding pad on the front surface of the semiconductor chip, and at least one part of the rewiring structure is distributed on the wiring substrate; and an encapsulation structure for encapsulating the semiconductor chip, the wiring substrate and the rewiring structure.

2. The semiconductor chip package structure according to claim 1, wherein the wiring substrate comprises at least one routing layer, each routing layer having thereon a wiring pattern of at least one trace and/or pad.

3. The semiconductor chip package structure of claim 2, wherein the different routing layers are connected by a connection layer formed of a conductive material.

4. The semiconductor chip package structure of claim 3, wherein the connection layer comprises at least one solder post corresponding to a location of a trace and/or a pad on the two routing layers to which it is connected.

5. The semiconductor chip package structure according to claim 4, wherein: the wiring substrate includes at least one opening for accommodating the semiconductor chip.

6. The semiconductor chip package structure of claim 5, wherein the rewiring structure comprises at least one wiring layer.

7. The semiconductor chip package structure according to claim 6, wherein the wiring layer is formed on the front surface of the semiconductor chip and on the surface of a routing layer of a wiring substrate.

8. The semiconductor chip package structure according to claim 7, wherein the wiring layer comprises a first wiring layer including a first insulating layer formed on the lower surface of the wiring substrate and the front surface of the semiconductor chip, at least one first opening is provided on the first insulating layer, the first opening is positioned to correspond to at least one pad of the front surface of the semiconductor chip and to correspond to at least one trace and/or pad of the routing layer, the at least one first opening is filled with a conductive material to form a first filled via, and a first patterned line formed of a conductive material for electrically connecting two or more first filled vias is formed on the first insulating layer.

9. The semiconductor chip package structure of claim 8, wherein the wiring layer comprises an Nth wiring layer, the Nth wiring layer comprises an Nth insulating layer, at least one Nth opening, at least one Nth filled via and an Nth patterned line, the position of the at least one Nth opening corresponds to the (N-1) th patterned line, and N is greater than or equal to 2.

10. The semiconductor chip package structure of claim 9, comprising at least one conductive post on the patterned trace of the last wiring layer, wherein the encapsulation structure comprises an outermost insulating layer encapsulating the last wiring layer and the conductive post, exposing a surface of the conductive post.

11. The semiconductor chip package structure according to claim 10, wherein: the packaging structure further comprises a packaging layer used for packaging the back surface of the semiconductor chip and/or the upper surface of the wiring substrate, and the upper surface of the wiring substrate is the upper surface of the routing layer.

12. The semiconductor chip package structure according to claim 11, wherein: the wiring pattern of one routing layer is exposed outside the encapsulating layer.

13. A semiconductor chip package structure comprising:

at least one chip package structure according to any one of claims 1 to 12;

the second chip packaging structure comprises a packaged chip and a rewiring structure for leading out a welding pad on the front surface of the chip; wherein,

at least one of the rewiring structures of the second chip package is electrically connected to the connection layer of the wiring substrate of at least one of the chip packages according to any one of claims 1 to 12.

14. The semiconductor chip package structure according to claim 13, wherein the second chip package structure is a chip package structure according to any one of claims 1 to 12.