CN208888840U - Image object detection device - Google Patents
Image object detection device Download PDFInfo
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- CN208888840U CN208888840U CN201821767557.8U CN201821767557U CN208888840U CN 208888840 U CN208888840 U CN 208888840U CN 201821767557 U CN201821767557 U CN 201821767557U CN 208888840 U CN208888840 U CN 208888840U
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Abstract
This application discloses image object detection devices, the equipment includes image acquiring device, FPGA acquisition device and the FPGA accelerator for realizing target detection neural network, described image acquisition device is connected with the FPGA acquisition device signal, and the FPGA acquisition device is connected with the FPGA accelerator signal.The hardware configuration that the equipment uses FPGA acquisition+FPGA to accelerate, has the characteristics that high-performance, low-power consumption relative to general processor CPU.
Description
Technical field
This application involves image object detection field, in particular to a kind of image object detection device.
Background technique
Image object detection is the important component of computer vision technique, main by extracting characteristics of image, is realized
Identification or positioning to target.Such as in the manufacturing process of product, it is often necessary to the product surface after production or processing into
Row detection, since the mistake of means rate using artificial detection is high and low efficiency, is gradually sent out in recent years with judging whether there is defect
The image object detection technique based on machine vision is opened up to replace artificial detection.In the prior art, usually using FPGA as
Acquisition chip acquires image and utilizes the detection algorithm (example run in cpu chip then by the image transmitting of acquisition to cpu chip
Such as neural network model) image is detected target is identified.Image object detection algorithm is adopted more in the prior art
With neural network algorithm, the speed of service on the cpu chip of monokaryon is lagged behind significantly in the FPGA with circuit parallel
The speed of service on chip.
Summary of the invention
In view of problem above, embodiments herein provides a kind of image object detection device, can solve above-mentioned background
The problem of technology segment.
According to the image object detection device of embodiments herein, including image acquiring device, FPGA acquisition device and
Realize that the FPGA accelerator of target detection neural network, described image acquisition device and the FPGA acquisition device signal connect
It connects, the FPGA acquisition device is connected with the FPGA accelerator signal.
In an embodiment of above-mentioned image object detection device, described image acquisition device include sensor module and
AD conversion module, the signal output end of the sensor module are connect with the signal input part of the AD conversion module.
In an embodiment of above-mentioned image object detection device, the sensor module includes cmos sensor module
Or CIS sensor module or ccd sensor module.
In an embodiment of above-mentioned image object detection device, the FPGA acquisition device includes acquisition master control mould
The signal input part of block, the acquisition main control module is connect with the signal output end of the AD conversion module.
In an embodiment of above-mentioned image object detection device, the FPGA acquisition device further includes image output mould
Block, described image output module are connect with the acquisition main control module signal.
In an embodiment of above-mentioned image object detection device, the FPGA accelerator includes accelerating master control mould
Block, the acceleration main control module are connect with the acquisition main control module signal.
In an embodiment of above-mentioned image object detection device, the FPGA accelerator further includes memory module,
The memory module is connect with the acceleration main control module signal.
In an embodiment of above-mentioned image object detection device, the FPGA accelerator further includes communication module,
The communication module is connect with the acceleration main control module, for communicating with host computer.
In an embodiment of above-mentioned image object detection device, the communication module includes Peripheral Component Interconnect standard
Interface, high speed serialization computer expansion bus standard interface, Universal Serial Bus Interface, advanced extensive interface at least one
Kind.
In an embodiment of above-mentioned image object detection device, the acceleration main control module includes that at least one storage is single
Member, at least a computing unit and control unit；An at least storage unit is for storing operational order, operational data and institute
State the weighted data of target detection neural network；An at least computing unit is used for according to the operational order, the operation
Data and the weighted data execute the multiply-add operation of vector in the target detection neural computing to obtain calculated result；Institute
It states control unit to be connected with an at least storage unit, an at least computing unit, for via at least one storage
Unit obtains the operational order, and parses the operational order to control an at least computing unit.
It can be seen from the above that the hardware that the scheme of embodiments herein uses FPGA acquisition+FPGA to accelerate
Structure has the characteristics that high-performance, low-power consumption relative to general processor CPU.
Detailed description of the invention
Fig. 1 is the structural schematic diagram according to the image object detection device of one embodiment of the application；
Fig. 2 is the connection schematic diagram according to the acquisition main control module and image acquiring device of one embodiment of the application；
Fig. 3 is the schematic diagram according to the acceleration main control module of one embodiment of the application；
Fig. 4 is the structural schematic diagram according to the image object detection device of another embodiment of the application；
Fig. 5 is the functional block diagram according to the image object detection device of one embodiment of the application.
Specific embodiment
Theme described herein is discussed referring now to example embodiment.It should be understood that discussing these embodiments only
It is in order to enable those skilled in the art can better understand that being not to claim to realize theme described herein
Protection scope, applicability or the exemplary limitation illustrated in book.It can be in the protection scope for not departing from present disclosure
In the case of, the function and arrangement of the element discussed are changed.Each example can according to need, omit, substitute or
Add various processes or component.For example, described method can be executed according to described order in a different order, with
And each step can be added, omits or combine.In addition, feature described in relatively some examples is in other examples
It can be combined.
The meaning of " plurality " is two or more in the description of the present invention, unless otherwise clearly specific
It limits.
In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, term " is pacified
Dress ", " connected ", " connection " shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integrally
Connection；It can be mechanical connection, be also possible to be electrically connected or can be in communication with each other；It can be directly connected, it can also be in
Between medium be indirectly connected, can be the connection inside two elements or the interaction relationship of two elements.For this field
For those of ordinary skill, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.
Following disclosure provides many different embodiments or example is used to realize the different structure of the utility model.
In order to simplify the disclosure of the utility model, hereinafter to the component of specific examples and being set for describing.Certainly, they are only
Example, and purpose does not lie in limitation the utility model.In addition, various specific techniques and material that the utility model provides
Example, but those of ordinary skill in the art may be aware that other techniques application and/or other materials use.
As shown in Figure 1, image object detection device includes that image acquiring device 100, FPGA acquisition device 200 and FPGA add
Speed variator 300.Wherein, image acquiring device 100 is connect with 200 signal of FPGA acquisition device, FPGA acquisition device 200 and FPGA
The connection of 300 signal of accelerator.Image acquiring device 100 is for obtaining image, and FPGA acquisition device 200 is for acquiring picture number
According to FPGA accelerator 300 is for realizing the acceleration of target detection neural network.
Image acquiring device 100 further comprises LED drive module 102, CIS sensor module 1041 and AD conversion module
106, the signal output end of LED drive module 102 is connect with the signal input part of CIS sensor module 1041, CIS sensor die
The signal output end of block 1041 is connect with the signal input part of AD conversion module 106.
FPGA acquisition device 200 includes acquisition main control module 202, and the signal output end and LED for acquiring main control module 202 drive
The signal input part of dynamic model block 102 connects, and the signal input part for acquiring main control module 202 and the signal of AD conversion module 106 are defeated
Outlet connection.Acquiring main control module 202 can be using such as Spartan-6 of Xilinx company or altera corp
EP2C8Q208C8 chip.Acquisition main control module 202 is used to control LED drive module 102 and the AD conversion module 106 of acquisition passes
Defeated data.It is the connection schematic diagram of the acquisition main control module and image acquiring device of an embodiment with reference to Fig. 2.The present embodiment
By taking two CIS units as an example, it is illustrated below with one of CIS unit.As shown in Fig. 2, CIS sensor module 1041
To analog picture signal be input in AD conversion module 106 by channel 9, realize analog-to-digital conversion, the digital picture that will be obtained
Data are input in acquisition main control module 202 by channel 8, and 5,6,7 be acquisition main control module 202 to AD conversion module 106
Control line, communication mode SPI.It acquires main control module 202 and LED drive module 102 is controlled by control bus 1, LED drives mould
Block 102 controls the LED light source of CIS sensor module 1041 by control bus 2.3 sense CIS for acquisition main control module 202
The control signal of device module 1041 controls work, stopping and the sweep speed etc. of CIS sensor module 1041, and 4 believe for clock
Number.
Above-mentioned CIS (Contact Image Sensor, contact-sensing device) is a kind of electrooptical device, CIS
The model such as can be used CM201A4, SML1R183N of sensor module 1041 exports five kinds of light sources of R, G, B, IR, UV, uses
Three-channel parallel output signal mode exports 1/3 pixel of every line using three sections of every line pixel point while output and every road.
CIS sensor module 1041 is used to receive different light source transmitting signals, and transmits a signal to AD conversion module 106.It needs
Illustrate, the application does not limit the quantity of CIS sensor module 1041.CIS sensor is compared to CCD (Charge
Coupled Device, photosensitive coupling component) sensor have light-source brightness is good, the distortion factor is small, production cost is low, small power consumption,
For ease of maintenaince the advantages that.
Above-mentioned LED drive module 102 can use the switching characteristic of N-channel field-effect tube such as 2SK2978, for controlling
The light source switch of CIS sensor module 1041 processed exports constant current and controls light according to the invariable principle of field-effect tube electric current
Source constant output.
Above-mentioned AD conversion module 106 can use such as CIS signal processor AD80066 chip or high-speed parallel modulus
The analog signal of converter TLC5510, the CIS sensor module 1041 for will receive are converted into digital signal, for FPGA
Main control module 202 acquires.
In an embodiment of above-mentioned FPGA acquisition device 200, FPGA acquisition device 200 further includes image output module
204, image output module 204 is connect with acquisition 202 signal of main control module, for exporting the figure of the acquisition of FPGA acquisition device 200
As to host computer 400 or exterior display device 500.Image output module 204 for example may include HDMI output interface, VGA defeated
At least one of outgoing interface, USB output interface, pci interface.FPGA acquisition device 200 can by image output module 204 with it is upper
Position machine 400 is communicated, and specifically, can be communicated by AXI bus protocol with host computer 400.Content of Communication includes FPGA
The image information of acquisition is transmitted to host computer 400 and/or host computer 400 for operational order or configuration information by acquisition device 200
It is transmitted to FPGA acquisition device 200.
FPGA accelerator 300 includes accelerating main control module 302, and main control module 302 and acquisition main control module 202 is accelerated to believe
Number connection.Accelerate main control module 302 can be using such as Spartan-6 of Xilinx company or altera corp
EP2C8Q208C8 chip.Main control module 302 is accelerated to be used to detect the data performance objective collected of FPGA acquisition device 200
The multiply-add operation of vector is in neural computing to obtain calculated result, to realize that target detection neural network accelerates.With reference to figure
3, it is the schematic diagram of the acceleration main control module 302 of an embodiment.As shown in figure 3, main control module 302 is accelerated to include at least one storage
Unit, at least a computing unit and control unit；An at least storage unit is for storing operational order, operational data and target
Detect the weighted data of neural network；An at least computing unit is used to be executed according to operational order, operational data and weighted data
The multiply-add operation of vector is in target detection neural computing to obtain calculated result；Control unit and an at least storage unit, extremely
A few computing unit is connected, for obtaining operational order via an at least storage unit, and parse operational order with control to
A few computing unit.Wherein storage unit include input data storage unit, output data storage unit, weight storage unit and
The location of instruction.
In an embodiment of above-mentioned FPGA accelerator 300, FPGA accelerator 300 further includes memory module 304,
Memory module 304 is connect with 302 signal of main control module is accelerated.Memory module 304 include SDRAM register, SSRAM register,
At least one of FLASH register.
In another embodiment of above-mentioned FPGA accelerator 300, FPGA accelerator 300 further includes communication module
306, accelerate main control module 302 to connect with 306 signal of communication module.Communication module 306 is communicated for communicating with host computer 400
Content include FPGA accelerator 300 by calculated result be transmitted to host computer 400 and/or host computer 400 by operational order or
Configuration information is transmitted to FPGA accelerator 300.
Above-mentioned communication module 306 includes Peripheral Component Interconnect standard interface (PCI), high speed serialization computer expansion bus
Standard interface (PCI-E), Universal Serial Bus Interface (USB), advanced extensive interface (AXI) it is one or more.
With reference to Fig. 4, in another embodiment, image object detection device includes image acquiring device 100, FPGA acquisition dress
Set 200 and FPGA accelerator 300.Wherein, image acquiring device 100 is connect with 200 signal of FPGA acquisition device, FPGA acquisition
Device 200 is connect with 300 signal of FPGA accelerator.Image acquiring device 100 is for obtaining image, FPGA acquisition device 200
For acquiring image data, FPGA accelerator 300 is for realizing the acceleration of target detection neural network.Wherein, image obtains dress
Setting 100 includes ccd sensor module 1042 and AD conversion module 106, and the signal output end and AD of ccd sensor module 1042 turn
Change the mold the signal input part connection of block 106.FPGA acquisition device 200 includes acquisition main control module 202, acquires main control module 202
Signal output end connect with the signal input part of ccd sensor module 1042, the signal output end of AD conversion module 106 with adopt
Collect the signal input part connection of main control module 202.
Above-mentioned CCD (Charge Coupled Device, photosensitive coupling component) is in digital camera for recording light
The semiconductor subassembly of variation.Ccd sensor module 1042 is linear CCD sensor, and model can be using such as Toshiba
TCD1209D, or can be matrix CCD.
Above-mentioned AD conversion module 106 can use such as AD9824 or AD6645 chip, for passing the CCD received
The analog signal of sensor module 1042 is converted into digital signal, acquires for FPGA main control module 202.
Above-mentioned acquisition main control module 202 can be using such as Spartan-6 of Xilinx company or altera corp
EP2C8Q208C8 chip.Acquisition main control module 202 is for controlling ccd sensor module 1042 and acquisition 106 institute of AD conversion module
The data of collection.Accelerate main control module 302 can be using such as Spartan-6 of Xilinx company or altera corp
EP2C8Q208C8 chip.Main control module 302 is accelerated to be used to detect the data performance objective collected of FPGA acquisition device 200
The multiply-add operation of vector is in neural computing to obtain calculated result, to realize that target detection neural network accelerates.
In an embodiment of above-mentioned FPGA acquisition device 200, FPGA acquisition device 200 further includes image output module
204, image output module 204 is connect with acquisition 202 signal of main control module, for exporting the figure of the acquisition of FPGA acquisition device 200
As to host computer 400 or exterior display device 500.Image output module 204 for example may include HDMI output interface, VGA defeated
At least one of outgoing interface, USB output interface, pci interface.FPGA acquisition device 200 can by image output module 204 with it is upper
Position machine 400 is communicated, and specifically, can be communicated by AXI bus protocol with host computer 400.Content of Communication includes FPGA
The image information of acquisition is transmitted to host computer 400 and/or host computer 400 for operational order or configuration information by acquisition device 200
It is transmitted to FPGA acquisition device 200.
In an embodiment of above-mentioned FPGA accelerator 300, FP6A accelerator 300 further includes memory module 304,
Memory module 304 is connect with 302 signal of main control module is accelerated.Memory module 304 include SDRAM register, SSRAM register,
At least one of FLASH register.
In another embodiment of above-mentioned FPGA accelerator 300, FPGA accelerator 300 further includes communication module
306, accelerate main control module 302 to connect with 306 signal of communication module.Communication module 306 is communicated for communicating with host computer 400
Content include FPGA accelerator 300 by calculated result be transmitted to host computer 400 and/or host computer 400 by operational order or
Configuration information is transmitted to FPGA accelerator 300.
Above-mentioned communication module 306 includes Peripheral Component Interconnect standard interface (PCI), high speed serialization computer expansion bus
Standard interface (PCI-E), Universal Serial Bus Interface (USB), advanced extensive interface (AXI) it is one or more.
In the embodiment shown in fig. 4, ccd sensor module can also be replaced using cmos sensor module, it is above-mentioned
CMOS (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductor) is a kind of usual
The sensor of 10 times of sensitivity lower than ccd sensor.
It is the functional block diagram of the image object detection device of an embodiment with reference to Fig. 5.As shown in figure 5, FPGA accelerates dress
It sets including accelerating main control module, memory module (piece external storage SSRAM, SDRAM, FLASH) and communication module；Wherein, accelerate master
Control module include storage unit (input-buffer buffer, output caching buffer, on piece ROM, on piece RAM), computing unit (simultaneously
Row computing array) and control unit (on piece cache controller, piece outer controller, master controller).Main control module is accelerated to pass through logical
Letter module receives the weighted data of target detection neural network and then a series of operational order is saved, by by FPGA
The image data of acquisition device acquisition is stored in on-chip memory (ROM, RAM), starts to transport when accelerating main control module to receive
After row instruction, activation system main program enters the image data being stored in on-chip memory by input-buffer buffer
Input data is assigned in different PE units and holds according to different calculating tasks by parallel computation array, parallel computation array
The multiply-add operation of vector in row neural computing.If what parallel computation array computation obtained is the intermediate meter of neural network structure layer
It calculates as a result, then waiting for the calculation processing of next step back to parallel computation array by output caching buffer；If parallel
The layer end calculated result for the neural network structure layer that computing array is calculated, then for example can be transmitted to chip external memory (i.e.
SSRAM, SDRAM, FLASH) in save, wait the calculating of next neural network structure layer to start；If parallel computation array computation obtains
To be final calculation result, then final calculation result can be exported by communication module.On piece cache controller and piece external control
Device processed controls the work of on-chip memory and chip external memory respectively.Master controller macro adjustments and controls accelerate all inside main control module
The co-ordination of resource.
From the above, it can be seen that the hardware knot that the scheme of embodiments herein uses FPGA acquisition+FPGA to accelerate
Structure has the characteristics that high-performance, low-power consumption relative to general processor CPU.
The specific embodiment illustrated above in conjunction with attached drawing describes exemplary embodiment, it is not intended that may be implemented
Or fall into all embodiments of the protection scope of claims." exemplary " meaning of the term used in entire this specification
Taste " be used as example, example or illustration ", be not meant to than other embodiments " preferably " or " there is advantage ".For offer pair
The purpose of the understanding of described technology, specific embodiment include detail.However, it is possible in these no details
In the case of implement these technologies.In some instances, public in order to avoid the concept to described embodiment causes indigestion
The construction and device known is shown in block diagram form.
The foregoing description of present disclosure is provided so that any those of ordinary skill in this field can be realized or make
Use present disclosure.To those skilled in the art, the various modifications carried out to present disclosure are apparent
, also, can also answer generic principles defined herein in the case where not departing from the protection scope of present disclosure
For other modifications.Therefore, present disclosure is not limited to examples described herein and design, but disclosed herein with meeting
Principle and novel features widest scope it is consistent.
Claims (10)
1. image object detection device, which is characterized in that including image acquiring device, FPGA acquisition device and realize target detection
The FPGA accelerator of neural network, described image acquisition device are connected with the FPGA acquisition device signal, and the FPGA is adopted
Acquisition means are connected with the FPGA accelerator signal.
2. image object detection device according to claim 1, which is characterized in that described image acquisition device includes sensing
The signal input part of device module and AD conversion module, the signal output end of the sensor module and the AD conversion module connects
It connects.
3. image object detection device according to claim 2, which is characterized in that the sensor module includes that CMOS is passed
Sensor module or CIS sensor module or ccd sensor module.
4. image object detection device according to claim 2, which is characterized in that the FPGA acquisition device includes acquisition
The signal input part of main control module, the acquisition main control module is connect with the signal output end of the AD conversion module.
5. image object detection device according to claim 4, which is characterized in that the FPGA acquisition device further includes figure
As output module, described image output module is connect with the acquisition main control module signal.
6. image object detection device according to claim 4 or 5, which is characterized in that the FPGA accelerator includes
Accelerate main control module, the acceleration main control module is connect with the acquisition main control module signal.
7. image object detection device according to claim 6, which is characterized in that the FPGA accelerator further includes depositing
Module is stored up, the memory module is connect with the acceleration main control module signal.
8. image object detection device according to claim 6, which is characterized in that the FPGA accelerator further includes leading to
Believe that module, the communication module are connect with the acceleration main control module, for communicating with host computer.
9. image object detection device according to claim 8, which is characterized in that the communication module includes external components
Interconnection standards interface, high speed serialization computer expansion bus standard interface, Universal Serial Bus Interface, advanced extensive interface
It is at least one.
10. image object detection device according to claim 6, which is characterized in that the acceleration main control module includes extremely
Few a storage unit, at least a computing unit and control unit；An at least storage unit is for storing operational order, fortune
The weighted data of the evidence that counts and the target detection neural network；An at least computing unit is used to be referred to according to the operation
It enables, the operational data and the weighted data execute the multiply-add operation of vector in the target detection neural computing to obtain
Calculated result；Described control unit is connected with an at least storage unit, an at least computing unit, for via described
An at least storage unit obtains the operational order, and parses the operational order to control an at least computing unit.
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| CN201821767557.8U CN208888840U (en) | 2018-10-30 | 2018-10-30 | Image object detection device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113259604A (en) * | 2021-05-14 | 2021-08-13 | 厦门壹普智慧科技有限公司 | Intelligent perception image acquisition device and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113259604A (en) * | 2021-05-14 | 2021-08-13 | 厦门壹普智慧科技有限公司 | Intelligent perception image acquisition device and method |
| CN113259604B (en) * | 2021-05-14 | 2023-05-30 | 厦门壹普智慧科技有限公司 | Intelligent perception image acquisition device and method |
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