CN208588917U - An industrial robot motion controller based on ARM+DSP+FPGA - Google Patents

Abstract

The utility model discloses an industrial robot motion controller based on ARM+DSP+FPGA, which comprises an upper computer level and a lower computer level. The upper computer level has a microprocessor ARM with built-in human-computer interaction interface software, and the lower computer level includes a main processing unit. On the one hand, the DSP receives the data of the host computer, performs arithmetic operations, transmits, receives and analyzes the communication data, and stores the data. On the other hand, the DSP reads the FPGA and collects the status and input signals of other modules. Send control signals to other modules; FPGA is used to design external general IO, collect external states, send real-time external signals to DSP, read control signals sent by DSP, and generate the output of driver position pulses. The control system of the utility model has stable performance, is easy to use, can be operated without failure for a long time, has strong expansibility, simple parameter configuration and easy maintenance.

Description

A kind of industrial robot motion controller based on ARM+DSP+FPGA

Technical field

The utility model relates to industrial robot motion control field, specially a kind of industry based on ARM+DSP+FPGA Robot Motion Controller.

Background technique

Industrial robot motion control system is made of motion controller, actuator, sensor, sensing element.Wherein, Motion controller is the top device for planning that robot is moved, its movement to be completed robot is converted into accordingly Controller instruction, and acquire signal and provide control signal by operation for the robots such as motor power device, keep robot correct Movement, so it is the brain of industrial robot.Conventional industrial robot is completed various expected dynamic by programming and emulating Work and job task, execution movement is single, simple, is unable to complete compound action.And requirement day of the modern industrialization to robot Benefit improves, and for processing emergency case and completes more complicated movement, it is desirable that robot integrates multiple sensors, as vision, Sound sensation, tactile etc..Environmental modeling and Decision Control are carried out by the integration technology of multisensor, can be more intelligent, and energy Increasingly complex movement is enough handled, the automation of production engineering is sufficiently improved.Using multi-sensor fusion technology, it is related to a large amount of Generating date and instruction control etc., it is more demanding to main control chip.And existing system less stable, it operates Not very convenient, scalability is also not very strong, and operation and maintenance all acquires a certain degree of difficulty.

Utility model content

(1) the technical issues of solving

In view of the deficiencies of the prior art, the utility model provides a kind of industrial robot fortune based on ARM+DSP+FPGA Industrial robot working efficiency can be improved by the utility model in movement controller.

(2) technical solution

To achieve the above object, the utility model provides the following technical solutions:

A kind of industrial robot motion controller based on ARM+DSP+FPGA, including host computer level and slave computer layer Face, the host computer level microprocessor ARM are simultaneously built-in with human-computer interaction interface software, which is characterized in that the slave computer layer Face includes on the one hand primary processor DSP and coprocessor FPGA, DSP are used to receive host computer data and carry out algorithm operation, lead to Transmission, reception and the parsing of letter data, the storage of data, another aspect DSP are also used to read the shape that FPGA acquires other modules State and input signal, and control signal is sent to other modules；FPGA acquires external shape for being responsible for external general purpose I/O design State sends real-time external signal to DSP, reads the control signal that DSP is sent, and generates the output of drive location pulse and right The input and latch of DAC module.

Preferably, the ARM selects the S3C2440 processor of ARM9 series Samsung.

Preferably, the host computer mainly includes following module: memory module Nand Flash and SDRAM, Ethernet mould Block, the first power module, the first reseting module, Keysheet module, touch screen module and LCD display module, debugging module.

Preferably, the memory module Nand Flash is for needing the data of power down protection to store, memory module SDRAM For storing operation code, data and stack space；Ethernet module forms local area network for accessing internet；First power supply Module is converted to host computer disparate modules for realizing voltage and provides different voltages；First reseting module is for replying each module To original state；Keysheet module is inputted for robotary；Touch screen module and LCD display module are for robot operation letter In breath feedback to LCD touch screen；Debugging module is used to by jtag interface download to compiled program in host computer chip, System is emulated and is debugged.

Preferably, the model TMS320C6713, the DSP of the DSP includes DSP hardware module design and dsp interface Design.

Preferably, the DSP hardware module design include: second power supply module, the second reseting module, SDRAM module, FLASH module, CPLD module；Dsp interface design includes: McBSP interface, EMIF interface, HPI interface and jtag interface.

Preferably, the model XC3S400A, the FPGA of the FPGA includes that module, I/O interface mould occur for variable-frequency pulse Block and D/A interface module.

Preferably, it includes two modules of frequency generator and impulse generator, frequency hair that module, which occurs, for the variable-frequency pulse Raw device module is used for output pulse signal, and pulse generator module exports certain umber of pulse for controlling frequency generator.

(3) beneficial effect

The utility model provides a kind of industrial robot motion controller based on ARM+DSP+FPGA, and having following has Beneficial effect:

(1), 4 channel DMA, 3 channel UART, 2 channel SPI, single purpose LCD control are externally provided on the utility model ARM chip slapper Device, touch screen interface, usb host and equipment processed, the memory management unit with 16K instruction buffer and 16K data buffer storage etc..It is main Frequency is up to 400MHZ, operating voltage 1.2V, has low price, low-power consumption, high performance characteristics.

(2), the utility model control system performance stablize, upper hand be easy, can long-time failure-free operation, scalability pole By force, parameter configuration is simple, easy to maintain.

(3), the utility model ensure that the real-time control of system based on the robot functional component of high-performance treatments chip System and scheduling, enhance the anti-interference ability of system, realize the linkage and interpolation of functional component under more servos, particular surroundings.

(4), the control unit of the utility model multi-processor cooperation；The same operating system of multimachine multiaxis.

(5), the utility model ARM operates in (SuSE) Linux OS, develops in Qtopia-2.2.0 development platform man-machine Interactive interface has good portability, can be transplanted to other platforms.

Detailed description of the invention

Fig. 1 is the utility model controller general structure design；

Fig. 2 is the utility model DSP overall structure block diagram.

Specific embodiment

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work Every other embodiment obtained, fall within the protection scope of the utility model.

As depicted in figs. 1 and 2, the utility model provides a kind of technical solution:

A kind of industrial robot motion controller based on ARM+DSP+FPGA, including host computer level and slave computer layer Face, the host computer level microprocessor ARM are simultaneously built-in with human-computer interaction interface software, and the slave computer level includes main process task On the one hand device DSP and coprocessor FPGA, DSP are used to receive host computer data and carry out the hair of algorithm operation, communication data It send, receive and parses, the storage of data, another aspect DSP is also used to read the state and input letter that FPGA acquires other modules Number, and control signal is sent to other modules；FPGA acquires external status, sends to DSP for being responsible for external general purpose I/O design Real-time external signal reads the control signal that DSP is sent, and generates the output of drive location pulse and to the defeated of DAC module Enter to latch.

The ARM selects the S3C2440 processor of ARM9 series Samsung.

ARM operates in (SuSE) Linux OS, develops human-computer interaction interface in Qtopia-2.2.0 development platform, has Good portability can be transplanted to other platforms.

The host computer mainly includes following module: memory module Nand Flash and SDRAM, ethernet module, first Power module, the first reseting module, Keysheet module, touch screen module and LCD display module, debugging module.

The memory module Nand Flash is for needing the data of power down protection to store, and memory module SDRAM is for depositing Put operation code, data and stack space；Ethernet module forms local area network for accessing internet；First power module is used Host computer disparate modules are converted in realization voltage, and different voltages are provided；First reseting module is for being returned to each module initially State；Keysheet module is inputted for robotary；Touch screen module and LCD display module are fed back for robot operation information Onto LCD touch screen；Debugging module is for downloading in host computer chip compiled program by jtag interface, to system It is emulated and is debugged.

The model TMS320C6713 of the DSP.

The DSP includes DSP hardware module design and dsp interface design.

The DSP hardware module design include: second power supply module, the second reseting module, SDRAM module, FLASH, CPLD；Dsp interface design includes: McBSP interface, EMIF interface, HPI interface.

(1) second power supply module

Lower computer system needs an external 5V power supply according to the power consumption calculations of all devices, system, by MAX660, MAX603, MAX604 power supply chip are converted into the voltages such as 3.3V, 2.5V, 1.8V, 1.2V of system needs.

(2) second reseting modules

Reset function is realized using MAX811T chip, MAX811T can detect voltage and reset, and reset pin is looked into It askes key to reset, generates reset signal when voltage is less than the critical value of setting, low-pressure state continues at least 140ms and is just returned to Normal condition, it can be ensured that DSP normal reset.

(3) SDRAM module

SDRAM is run for dynamic data storage or program.In controller operational process, DSP need to carry out algorithm process, The operations such as poor complementary operation, instruction control, data processing, it is required interior with the continuous improvement of the complexity and arithmetic accuracy of algorithm Increase is deposited, to operate normally controller, needs to be extended DSP memory.

(4) FLASH

C6713 chip extends out a piece of FLASH, facilitates the program debugged that can be solidificated in FLASH.FLASH is for counting According to backing up and controlling program storage, the control of DSP is signally attached to CPLD, realizes address decoding, piece choosing, timing control by CPLD The work such as system, general line system, and then control erasing and the read-write operation of FLASH.

(5) CPLD

There are two effects by CPLD in DSP expansion structure: 1) extending DSP memory space, be not take up DSP Resources on Chip, operate It is convenient；2) DSP external interface is extended, such as C6713 only provides two McBSP, if desired handles more multichannel voice signal, then needs It to be extended using CPLD.

Two .DSP Interface designs

(1) McBSP interface

AIC23 is a stereo audio Codec for being integrated with analog functuion that TI company releases.AIC23 chip has one The simulation that a most of Codec do not have bypasses setting, it can convert without A/D, directly see back analog signal off It puts.AIC23 chip can be with number and analog voltage operation, and voltage is compatible with the I/O voltage of DSP, the end McBSP with DSP Cause for gossip is now seamlessly connected, and keeps system design simpler.

When processing multi-path voice signal processing, when using CPLD, only need 1 McBSP for communicating with AIC23, AIC23 work Make mode by CPLD to configure, CPLD provides the clock signal and CS signal of AIC23 work.

(2) EMIF interface

When DSP and chip external memory contact, it is necessary to pass through the control of EMIF.The synchronous device that EMIF interface is supported has SDRAM,SBSRAM;Asynchronous device has SRAM, ROM and FIFO etc., is that C6000 series DSP accesses outside in a manner of parallel bus The unique channel of equipment.All these devices are by same address and data/address bus, when to make DSP access a device, other Device is in high configuration, needs to carry out Bus isolation.Tri-state gate is added i.e. before each device, is carried out by EMIF control bus Control.There are four separate space CE0 ~ CE3, data-bus width 32bit by EMIF, while also providing 8/16bit register Read/write is supported.Not only transmission rate is higher for EMIF interface, interface capability is strong, stability number, and designs simple.

FPGA is handled as the external memory of DSP, by realizing in two mutually independent FIFO of FPGA interior design For EMIF to the data access of FPGA, data processed result is input to the caching of DSP by FIFO_ R, and FIFO_W is for DSP to FPGA Middle data processing module sends the caching of data.The status register in FPGA is used to record the state of two FIFO simultaneously, is DSP Control two FIFO information.There are one control logics in FPGA, for controlling two FIFO work, it is ensured that data correctly pass It is defeated.

(3) HPI interface

TMS320C6713 DSP host interface (HPI) is a 16 parallel-by-bit interfaces, passes through HPI and outside ARM micro process Device is attached, and ARM can directly access the internal storage of DSP.Make ARM and DSP connection side with by a piece of dual port RAM Formula is compared, more simple and convenient using HPI connection type, does not need to increase peripheral logical circuit.ARM and DSP is realized by HPI Data exchange is completed the logic control of HPI interface by CPLD, coordinates the communication of system front and back.

DSP control program is write using embedded type C language, and exploitation environment is the CCS6.0 Integrated Development Environment of TI company.

(4) jtag interface

Jtag port can be used to configure chip and programming, by control processor and can also access internal register, The software of embeded processor is developed and debugged, to increase circuit production efficiency.Carrying out DSP hardware system emulation In the process, the internal control registers of DSP, program storage and data storage can be by jtag boundary scan interfaces to it Be monitored, and can be in the exploitation environment of CCS(TI company) in program downloaded in DSP then carry out emulation testing.JTAG It is mainly concerned with four interfaces: TCK, TDI, TDO, TMS, respectively clock, data input, data output, selection.

The model XC3S400A of the FPGA.

The FPGA includes that module, I/O interface module and D/A interface module occur for variable-frequency pulse.

It includes two modules of frequency generator and impulse generator, frequency generator module that module, which occurs, for the variable-frequency pulse For output pulse signal, pulse generator module exports certain umber of pulse for controlling frequency generator.

FPGA selects a multi-functional control chip XC3S400A of U.S. Xilinx company exploitation to belong to Spartan-3A Series, high-performance low-power-consumption.FPGA can be carried out parallelization data processing, and pin is resourceful, and there is very strong interface to handle energy Power and logic control ability.Can complete pulse in parallel input, output control, feed speed control, communication module control, difference it is defeated Enter the functions such as signal processing, origin position detection.

(1) module occurs for variable-frequency pulse

The module includes two modules of frequency generator and impulse generator, frequency generator module output pulse signal, Pulse generator module controls frequency generator and exports certain umber of pulse.When the speed enable signal that DSP transmission comes is enabled, The frequency generator of FPGA receives the frequency signal that DSP is transmitted, and according to the frequency signal of regulation, sends pulse；When DSP is transmitted When the position enable signal come is enabled, FPGA pulse generating module receives the position signal that DSP is transmitted, and by signal be sent into two into The preset end of down counter processed often sends a pulse toward motor, and position signal subtracts 1, and when numerical value reduces to zero, generation one is quick Feel signal feedback and module occurs to frequency, forbids it to export pulse again, controlled so as to complete one.

(2) I/O interface module

The I/O signal that motion controller is related to is more, if directly can consume I/O signal access FPGA inside a large amount of FPGA I/O resource, be unfavorable for system IO expand and controller reconstitution design.The design realizes that IO believes in the form of IO bus Number control, i.e., transmit chip by bidirectional bus with tri-state gate for one group of I/O signal of FPGA and access bus, then pass through control Signal processed draws multiple groups I/O signal from bus.Which plays the role of IO expansion.

(3) D/A interface module

Corresponding analog voltage is converted digital signals into, analog voltage output is mainly used for.What the design selected XC3S400A fpga chip does not have D/A conversion module, needs external D/A conversion chip.The design selects the input of 16 Bits Serials DACA chip AD5541, meets high-speed, high precision requirement.

It should be noted that, in this document, relational terms such as first and second and the like are used merely to a reality Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or its any other variant are intended to Non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that There is also other identical elements in process, method, article or equipment including the element.

While there has been shown and described that the embodiments of the present invention, for the ordinary skill in the art, It is understood that these embodiments can be carried out with a variety of variations in the case where not departing from the principles of the present invention and spirit, repaired Change, replacement and variant, the scope of the utility model is defined by the appended claims and the equivalents thereof.

Claims (8)

1. a kind of industrial robot motion controller based on ARM+DSP+FPGA, including host computer level and slave computer level, The host computer level microprocessor ARM is simultaneously built-in with human-computer interaction interface software, which is characterized in that the slave computer level packet It includes primary processor DSP and on the one hand coprocessor FPGA, DSP is used to receive host computer data and carries out algorithm operation, communication number According to transmission, reception and parsing, the storage of data, another aspect DSP be also used to read FPGA acquisition state and input signal, And send control signal；FPGA acquires external status, sends external letter in real time to DSP for being responsible for external general purpose I/O design Number, the control signal that DSP is sent is read, the output of drive location pulse and the input and latch to DAC module are generated.

2. a kind of industrial robot motion controller based on ARM+DSP+FPGA according to claim 1, feature exist In: the ARM selects the S3C2440 processor of ARM9 series Samsung.

3. a kind of industrial robot motion controller based on ARM+DSP+FPGA according to claim 1, feature exist In: the host computer mainly includes following module: memory module Nand Flash and SDRAM, ethernet module, the first power supply mould Block, the first reseting module, Keysheet module, touch screen module and LCD display module, debugging module.

4. a kind of industrial robot motion controller based on ARM+DSP+FPGA according to claim 3, feature exist In: the memory module Nand Flash is for needing the data of power down protection to store, and memory module SDRAM is for storing operation Code, data and stack space；Ethernet module forms local area network for accessing internet；First power module for realizing Voltage is converted to host computer disparate modules and provides different voltages；First reseting module is for making each module be returned to original state； Keysheet module is inputted for robotary；Touch screen module and LCD display module are fed back for robot operation information to LCD On touch screen；Debugging module carries out system for downloading in host computer chip compiled program by jtag interface Emulation and debugging.

5. a kind of industrial robot motion controller based on ARM+DSP+FPGA according to claim 1, feature exist In: the model TMS320C6713, the DSP of the DSP includes DSP hardware module design and dsp interface design.

6. a kind of industrial robot motion controller based on ARM+DSP+FPGA according to claim 5, feature exist In: the DSP hardware module design includes: second power supply module, the second reseting module, SDRAM module, FLASH module, CPLD Module；Dsp interface design includes: McBSP interface, EMIF interface, HPI interface and jtag interface.

7. a kind of industrial robot motion controller based on ARM+DSP+FPGA according to claim 1, feature exist In: the model XC3S400A, the FPGA of the FPGA includes that module, I/O interface module and D/A interface occur for variable-frequency pulse Module.

8. a kind of industrial robot motion controller based on ARM+DSP+FPGA according to claim 7, feature exist In: it includes two modules of frequency generator and impulse generator that module, which occurs, for the variable-frequency pulse, and frequency generator module is used for Output pulse signal, pulse generator module export certain umber of pulse for controlling frequency generator.