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CN208432932U - A kind of arbitrary waveform generator based on FPGA closed-loop control - Google Patents

A kind of arbitrary waveform generator based on FPGA closed-loop control Download PDF

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Publication number
CN208432932U
CN208432932U CN201821154732.6U CN201821154732U CN208432932U CN 208432932 U CN208432932 U CN 208432932U CN 201821154732 U CN201821154732 U CN 201821154732U CN 208432932 U CN208432932 U CN 208432932U
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China
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module
fpga
analog
waveform
conversion module
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CN201821154732.6U
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Inventor
王丽娜
许冉
张易晨
赵婧儒
王铭秋
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Nanjing Xinda Safety Emergency Management Research Institute Co Ltd
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Nanjing University of Information Science and Technology
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Abstract

本实用新型公开了一种基于FPGA闭环控制的任意波形发生器,包括依次连接的FPGA模块、数模转换模块、低通滤波电路、程控放大电路、模数转换模块,FPGA模块分别还连接程控放大电路和模数转换模块,所述FPGA模块包括控制模块、相位累加器和波形存储器,所述相位累加器由所述控制模块控制进行数据累加,所述波形存储器存储波形数据并根据所述相位累加器的数据累加结果输出波形至数模转换模块,所述控制模块接收模数转换模块采集的程控放大电路输出信号电压值并控制所述程控放大电路的放大倍数。本实用新型的任意波形发生器,采用ADC闭环控制使得输出更为稳定及精确,对电路的保护更为完善,同时实现了波形的存储、显示与分析。

The utility model discloses an arbitrary waveform generator based on FPGA closed-loop control. A circuit and an analog-to-digital conversion module, the FPGA module includes a control module, a phase accumulator and a waveform memory, the phase accumulator is controlled by the control module to accumulate data, and the waveform memory stores waveform data and accumulates according to the phase The data accumulation result of the controller outputs a waveform to the digital-to-analog conversion module, and the control module receives the output signal voltage value of the program-controlled amplifying circuit collected by the analog-to-digital conversion module and controls the amplification factor of the program-controlled amplifying circuit. The arbitrary waveform generator of the utility model adopts ADC closed-loop control to make the output more stable and accurate, the protection of the circuit is more perfect, and the storage, display and analysis of the waveform are realized at the same time.

Description

A kind of arbitrary waveform generator based on FPGA closed-loop control
Technical field
The utility model relates to a kind of waveform generators, more particularly to a kind of random waveform based on FPGA closed-loop control Generator.
Background technique
A kind of signal generator of the arbitrary waveform generator as multimode, it not only can produce sawtooth wave, sine wave Deng conventional waveform, and the diversified feature of carrier modulation can also be shown, make waveform that amplitude modulation, phase modulation, frequency modulation and pulse occur Modulation etc..The editor that waveform can be even realized using computer software, generates random waveform required for user.Random waveform hair Raw device is widely used in automatic control, electronic circuit and scientific experimentation field, is that a electron measurement work offer meets skill The electric signal equipment that art requires, therefore swift and violent development is all obtained in every field.
Arbitrary waveform generator is the best instrument of emulation experiment in laboratory, and arbitrary waveform generator is the one of signal source Kind, it has the characteristics that signal source is all.It is generally acknowledged that known signal required for signal source is mainly provided to circuit-under-test is (each Kind waveform), then with the interested parameter of other instrument measurements.Visible signal source is in electronic experiment and test processes, not Any parameter is measured according to the requirement of user, various test signals is emulated, is supplied to circuit-under-test, to reach test It needs.Arbitrary waveform generator passes through the data sample point for reading look-up table, to create function waveform and random waveform.It is most of Modern arbitrary waveform generator synthesizes (DDS) technology using direct signal, provides signal in extensive frequency range.
Utility model content
The task of the utility model is to provide a kind of arbitrary waveform generator based on FPGA closed-loop control, steady to realize Fixed output and large-scale voltage are adjusted.
Technical solutions of the utility model are such that a kind of arbitrary waveform generator based on FPGA closed-loop control, including FPGA module, D/A converter module, low-pass filter circuit, programmable amplifying circuit, analog-to-digital conversion module, the FPGA module difference It is connect with D/A converter module, programmable amplifying circuit and analog-to-digital conversion module, the output end connection of the D/A converter module is low The output end of bandpass filter circuit, the low-pass filter circuit connects programmable amplifying circuit, and the analog-to-digital conversion module is put with program-controlled The output end connection acquisition output signal voltage value of big circuit, the FPGA module includes control module, phase accumulator and wave Shape memory, the phase accumulator are controlled by the control module and carry out data accumulation, the wave memorizer stored waveform Data and according to the data accumulation result output waveform of the phase accumulator to D/A converter module, the control module receives The output signal voltage value of analog-to-digital conversion module acquisition and the amplification factor for controlling the programmable amplifying circuit.
Further, including keyboard input module and display module, the keyboard input module and display module with it is described Control module connection.
Further, including host computer, the FPGA module include RAM module, and the RAM module turns for storing modulus The output signal voltage value of block acquisition is changed the mold, the host computer is connect with FPGA module reads RAM module storing data.
Further, the wave memorizer includes sinusoidal wave data memory, square wave data storage, triangular wave data Memory and sawtooth wave data storage.
The utility model compared with prior art the advantages of be: use FPGA for hardware controls core, produced using FPGA The analog signal of raw specific waveforms, is filtered the DAC waveform signal exported by low-pass filter circuit, removes noise It influences, keeps its signal more steady.Filter output signal is sampled after programmable amplifier through high-speed ADC, and in real time ADC collection value be passed to FPFA in carry out parameter preset be compared, by pid algorithm change programmable amplifier amplification factor come Output voltage adjustable extent is bigger, more stable signal specific, more perfect to the protection of circuit.It is realized by host computer Storage, display and the analysis of waveform, it is more intuitive and convenient, more parameters and data can be obtained by analysis, convenient for wave The observation and analysis of shape.
Detailed description of the invention
Fig. 1 is the arbitrary waveform generator structural schematic diagram based on FPGA closed-loop control.
Fig. 2 is FPGA module schematic diagram.
Fig. 3 is phase accumulator and phase accumulator structural schematic diagram.
Fig. 4 is D/A converter module schematic diagram.
Fig. 5 is low-pass filter circuit schematic diagram.
Fig. 6 is programmable amplifying circuit schematic diagram.
Fig. 7 is programmable amplifying circuit gain control circuit schematic diagram.
Specific embodiment
Below with reference to embodiment, the utility model is described in further detail, but not as the restriction to the utility model.
Incorporated by reference to shown in Fig. 1, the arbitrary waveform generator based on FPGA closed-loop control that the present embodiment is related to, including FPGA Module 1, D/A converter module 2, low-pass filter circuit 3, programmable amplifying circuit 4, analog-to-digital conversion module 5,6 and of keyboard input module Display module 7.Using the EP4CE15FPGA of ALTERA, keyboard input module 6 and display module 7 are FPGA module 1 ILI9341TFT touch screen.Information exchange between FPGA module 1 and ILI9341TFT touch screen realizes the control of output parameter, According to touch screen be passed to information generate a cycle in voltage parameter and recycle output control D/A converter module continue it is defeated Out.
Specifically, as shown in connection with fig. 2, in FPGA module 1, the soft core of an embedded QSYS constructs II processor of NIOS Module forms control module 1a, and control module 1a includes CPU, EPCS, SDRAM, JTAG, SYSID and correlated inputs output end Mouth (I/O) etc. realizes key logic control, LCD screen driving and Correlation method for data processing etc..FPGA module 1 further includes that phase is tired Add device 1b, wave memorizer 1c and RAM module 1d, waveform generates mainly by two moulds of phase accumulator 1b and wave memorizer 1c Block is completed, and the data difference in wave memorizer 1c can generate different waveform signals, and wave memorizer 1c includes Sinusoidal wave data memory, square wave data storage, triangular wave data storage and sawtooth wave data storage.As shown in figure 3, This part-structure are as follows: phase accumulator 1b is connected with wave memorizer 1c.Input port RESET, frequency control word K and clock are defeated Enter CLK.Output port: Wave data sin.Phase accumulator 1b is substantially a counter, is controlled according to the frequency of input Number of words value is different, carries out the data accumulation that step value does not wait and output, the waveform of a cycle is stored in wave memorizer 1c Data export corresponding waveforms amplitude according to the accumulation result of phase accumulator 1b, these amplitude continuously exported points are just constituted Specific waveform.
As shown in Figures 4 and 5, the waveform continuously exported converts digital signals into simulation letter by D/A converter module 2 Number, then pass through 3 filtering and noise reduction of low-pass filter circuit.D/A converter module 1 uses AD9708 high-speed digital-analog conversion chip, such core Piece is eight bit data interface, and maximum speed reaches 125Msps, and eight bit parallel datas are inputted D/A converter module 2 by FPGA module, Analog signal is converted by digital signal, exports two-way analog difference signal.Low-pass filter circuit 3 is seven rank passive filter circuits Two-way analog difference signal is filtered, is mainly made of capacitance resistance and inductance, cutoff frequency is set as 40MHz, this Sample can remove the influence such as noise, improve signal anti-interference ability.Then two-way analog differential is believed by two amplifiers Number it is changed into one-channel signal, while output signal amplitude can be manually adjusted, maximum exportable 10VppSignal, convenient for applying Different occasions.
As shown in fig. 6, FPGA module 1 by control programmable amplifier, first makes precompensation parameter input programmable amplifying circuit 4 It generates certain amplification factor, and collected voltage value is returned to FPGA after the acquisition of analog-to-digital conversion module 5 in signal.One side 5 collection value of analog-to-digital conversion module is compared with predeterminated voltage in face, controls DAC output control electricity by pid algorithm FPGA Pressure changes the programmable amplifier gain in Fig. 7, changes the amplification factor of programmable amplifier, burning voltage, 16 lists can be used in DAC On the other hand collected voltage is stored in the RAM module 1c of FPGA module 1 by channel DAC8411, host computer 8 and FPGA mould RAM module 1d storing data is read in the connection of block 1, is analyzed by signal Tap tool and MATLAB output waveform.

Claims (4)

1.一种基于FPGA闭环控制的任意波形发生器,其特征在于,包括FPGA模块、数模转换模块、低通滤波电路、程控放大电路、模数转换模块,所述FPGA模块分别与数模转换模块、程控放大电路和模数转换模块连接,所述数模转换模块的输出端连接低通滤波电路,所述低通滤波电路的输出端连接程控放大电路,所述模数转换模块与程控放大电路的输出端连接采集输出信号电压值,所述FPGA模块包括控制模块、相位累加器和波形存储器,所述相位累加器由所述控制模块控制进行数据累加,所述波形存储器存储波形数据并根据所述相位累加器的数据累加结果输出波形至数模转换模块,所述控制模块接收模数转换模块采集的输出信号电压值并控制所述程控放大电路的放大倍数。1. an arbitrary waveform generator based on FPGA closed-loop control, is characterized in that, comprises FPGA module, digital-to-analog conversion module, low-pass filter circuit, program-controlled amplifying circuit, analog-to-digital conversion module, and described FPGA module is respectively with digital-to-analog conversion module. The module, the program-controlled amplifier circuit and the analog-to-digital conversion module are connected, the output end of the digital-to-analog conversion module is connected to a low-pass filter circuit, the output end of the low-pass filter circuit is connected to a program-controlled amplifier circuit, and the analog-to-digital conversion module is connected to the program-controlled amplifier circuit. The output end of the circuit is connected to the voltage value of the collected output signal, the FPGA module includes a control module, a phase accumulator and a waveform memory, the phase accumulator is controlled by the control module to accumulate data, and the waveform memory stores the waveform data according to The data accumulation result of the phase accumulator outputs a waveform to the digital-to-analog conversion module, and the control module receives the output signal voltage value collected by the analog-to-digital conversion module and controls the amplification factor of the program-controlled amplifying circuit. 2.根据权利要求1所述的基于FPGA闭环控制的任意波形发生器,其特征在于,包括按键输入模块和显示模块,所述按键输入模块和显示模块与所述控制模块连接。2. The arbitrary waveform generator based on FPGA closed-loop control according to claim 1, characterized in that it comprises a key input module and a display module, and the key input module and the display module are connected to the control module. 3.根据权利要求1所述的基于FPGA闭环控制的任意波形发生器,其特征在于,包括上位机,所述FPGA模块包括RAM模块,所述RAM模块用于存储模数转换模块采集的输出信号电压值,所述上位机与FPGA模块连接读取RAM模块存储数据。3. the arbitrary waveform generator based on FPGA closed-loop control according to claim 1, is characterized in that, comprises host computer, and described FPGA module comprises RAM module, and described RAM module is used to store the output signal collected by analog-digital conversion module voltage value, the host computer is connected to the FPGA module to read the data stored in the RAM module. 4.根据权利要求1所述的基于FPGA闭环控制的任意波形发生器,其特征在于,所述波形存储器包括正弦波数据存储器、方波数据存储器、三角波数据存储器和锯齿波数据存储器。4. The arbitrary waveform generator based on FPGA closed-loop control according to claim 1, wherein the waveform memory comprises a sine wave data memory, a square wave data memory, a triangular wave data memory and a sawtooth wave data memory.
CN201821154732.6U 2018-07-20 2018-07-20 A kind of arbitrary waveform generator based on FPGA closed-loop control Expired - Fee Related CN208432932U (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109708776A (en) * 2019-02-27 2019-05-03 上海拜安传感技术有限公司 An electronic system of a distributed optical fiber temperature measurement system with a large dynamic temperature measurement range and its realization method
CN111466874A (en) * 2020-03-12 2020-07-31 西安电子科技大学 Diffusion optical tomography system based on square wave modulation
CN112114614A (en) * 2020-08-21 2020-12-22 浪潮(北京)电子信息产业有限公司 A waveform data processing device, method, electronic device and storage medium

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109708776A (en) * 2019-02-27 2019-05-03 上海拜安传感技术有限公司 An electronic system of a distributed optical fiber temperature measurement system with a large dynamic temperature measurement range and its realization method
CN109708776B (en) * 2019-02-27 2024-11-29 上海拜安传感技术有限公司 Electronic system of distributed optical fiber temperature measurement system with large dynamic temperature measurement range and implementation method thereof
CN111466874A (en) * 2020-03-12 2020-07-31 西安电子科技大学 Diffusion optical tomography system based on square wave modulation
CN112114614A (en) * 2020-08-21 2020-12-22 浪潮(北京)电子信息产业有限公司 A waveform data processing device, method, electronic device and storage medium

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Effective date of registration: 20200618

Address after: 203-8, 2 / F, Beidou building, 6 Huida Road, Jiangbei new district, Nanjing, Jiangsu Province

Patentee after: Nanjing Xinda Safety Emergency Management Research Institute Co., Ltd

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