CN208239938U - A kind of computer motherboard circuit - Google Patents

Abstract

The application discloses a computer motherboard circuit, including a baseboard management controller, a platform path controller, and a flash memory; the flash memory is respectively connected to the baseboard management controller and the platform path controller, and stores a first program code and a second program code; The baseboard management controller is used to obtain and execute the first program code to perform baseboard management control; the platform path controller is used to obtain and execute the second program code to perform platform path control. This application effectively reduces the number of flash memory used in the computer motherboard circuit, so that only one flash memory needs to be maintained and updated, which is not only more convenient and simple, but also reduces the occupation of the circuit layout space, and effectively reduces the cost consumption of the computer motherboard circuit .

Description

A computer motherboard circuit

technical field

The present application relates to the field of computer technology, in particular to a computer motherboard circuit.

Background technique

Baseboard Management Controller (BMC) and Platform Controller Hub (PCH) are important devices on the computer motherboard circuit. Among them, the baseboard management controller is mainly used to realize the monitoring and management of the basic hardware drive devices of the computer, and the platform path controller is mainly used to realize the initialization of the basic input/output system (Basic Input/Output System, BIOS) of the computer after booting. Wait.

In the prior art, the baseboard management controller and the platform path controller are generally equipped with their own dedicated flash memory (Flash), so as to store the program codes required by them to perform their respective functions. However, since the price of the flash memory is not cheap, such a traditional design undoubtedly increases the manufacturing cost and maintenance cost of the product, and takes up a large space on the motherboard.

It can be seen that how to effectively solve the problem of cost consumption and space occupation of the flash memory in the mainboard circuit of the computer is a technical problem to be solved urgently by those skilled in the art.

Utility model content

The purpose of the present application is to provide a computer motherboard circuit that is easy to maintain, so as to effectively reduce cost consumption and reduce the occupied space of the flash memory in the circuit board.

In order to solve the above technical problems, the application provides a computer motherboard circuit, including a baseboard management controller, a platform path controller, and a flash memory;

The flash memory is respectively connected to the baseboard management controller and the platform path controller, and stores a first program code and a second program code;

The baseboard management controller is configured to obtain and execute the first program code to perform baseboard management control;

The platform path controller is used to acquire and execute the second program code for platform path control.

Optionally, the flash memory is NAND flash memory.

Optionally,

The I/O data terminal of the baseboard management controller and the I/O data terminal of the platform path controller are both connected to the I/O data terminal of the flash memory;

The addressing space of the baseboard management controller corresponds to the first program code;

The addressing space of the platform path controller corresponds to the second program code.

Optionally, the control signal terminal connected between the baseboard management controller and the flash memory includes:

a first clock signal terminal, a first enabling terminal, a first data output terminal, and a first data input terminal;

The control signal end used by the platform path controller to connect with the flash memory includes:

A second clock signal terminal, a second enabling terminal, a second data output terminal, and a second data input terminal.

Optionally,

Both the first clock signal terminal and the second clock signal terminal are connected to the third clock signal terminal of the flash memory;

Both the first enabling terminal and the second enabling terminal are connected to a third enabling terminal of the flash memory;

Both the first data output end and the second data output end are connected to the third data output end of the flash memory;

Both the first data input end and the second data input end are connected to a third data input end of the flash memory.

Optionally, the I/O bit width of the flash memory is 8 bits.

The computer motherboard circuit provided by this application includes a baseboard management controller, a platform path controller, and a flash memory; the flash memory is connected to the baseboard management controller and the platform path controller respectively, and stores the first program code and the second program code. Two program codes; the baseboard management controller is used to obtain and execute the first program code to perform baseboard management control; the platform path controller is used to obtain and execute the second program code to perform platform path control.

It can be seen that compared with the prior art, in the computer motherboard circuit provided by this application, by setting a single flash memory to provide storage services for the baseboard management controller and the platform path controller at the same time, the number of flash memories used in the computer motherboard circuit can be effectively reduced. Therefore, only one flash memory needs to be maintained and updated, which is not only more convenient and simple, but also reduces the occupation of circuit layout space, and effectively reduces the cost consumption of computer motherboard circuits.

Description of drawings

In order to illustrate the prior art and the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that need to be used in the description of the prior art and the embodiments of the present application. Of course, the following drawings related to the embodiments of the application describe only a part of the embodiments of the application, and those of ordinary skill in the art can obtain other The accompanying drawings, and other obtained drawings also belong to the protection scope of the present application.

Fig. 1 is the structural representation of a kind of computer motherboard circuit provided by the application;

FIG. 2 is a chip pin diagram of a flash memory provided by the present application.

Detailed ways

The core of the present application is to provide a computer motherboard circuit that is easy to maintain, so as to effectively reduce cost consumption and reduce the occupied space of the flash memory in the circuit board.

In order to describe the technical solutions in the embodiments of the present application more clearly and completely, the technical solutions in the embodiments of the present application will be introduced below in conjunction with the drawings in the embodiments of the present application. Apparently, the described embodiments are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

Please refer to Fig. 1, Fig. 1 is the structure schematic diagram of a kind of computer motherboard circuit provided by the present application; It comprises baseboard management controller 1, platform path controller 2 and flash memory 3; Flash memory 3 is connected with baseboard management controller 1 and platform path respectively The controller 2 is connected to and stores the first program code and the second program code; the baseboard management controller 1 is used to obtain and execute the first program code so as to perform baseboard management control; the platform path controller 2 is used to obtain and execute the second program code Program code for platform path control.

Specifically, as mentioned above, the baseboard management controller 1 is a device for monitoring and managing the basic hardware drive devices of the computer. It can monitor the machine state, restart, and re-power the machine when the machine is not powered on. , power-off and other baseboard control; it can also implement some hardware firmware upgrade operations. When the power of the computer is turned on, the baseboard management controller will obtain the corresponding function program code from its corresponding flash memory and run it, so as to provide the baseboard management service for the system.

Similarly, the platform path controller 2 will execute the relevant function program codes stored in the corresponding flash memory after the power of the computer is turned on, so as to initialize the mainboard chipset and the memory subsystem. Specifically, it mainly includes some diagnostic functions to ensure the normal function of some important hardware components, including keyboards, disks, I/O ports, etc.

In this application, specifically, the same flash memory 3 is used as both the flash memory corresponding to the baseboard management controller 1 and the flash memory corresponding to the platform path controller 2, that is, the same flash memory 3 is jointly used as the baseboard management controller 1 and the platform path controller. The path controller 2 provides services instead of using two flash memories as in the prior art, thereby effectively reducing the number of flash memories used in the computer motherboard circuit, achieving the purpose of reducing cost and reducing circuit layout space.

It is easy to understand that the flash memory 3 in the computer motherboard circuit provided by the present application is not only connected to the baseboard management controller 1 and the platform path controller 2 respectively, but also stores There are first program code and second program code. Wherein, the first program code is the functional program code corresponding to the baseboard management controller 1 , so that the baseboard management controller 1 acquires and executes the first program code to perform baseboard management control. The second program code is the functional program code corresponding to the platform path controller 2, so that the platform path controller 2 acquires and executes the second program code to control the platform path.

It can be seen that in the computer motherboard circuit provided by the present application, by setting a single flash memory 3 to provide storage services for the baseboard management controller 1 and the platform path controller 2 at the same time, the number of flash memories used in the computer motherboard circuit can be effectively reduced, so that only the The maintenance and update of a flash memory is not only more convenient and simple, but also reduces the occupation of circuit layout space, and effectively reduces the cost consumption of computer motherboard circuits.

The computer motherboard circuit provided by the application, on the basis of the above-mentioned embodiments:

As a preferred embodiment, the flash memory 3 is a NAND flash memory.

Specifically, NAND flash memory is a continuous storage medium suitable for storing large-capacity data. Therefore, NAND flash memory can be selected as the flash memory 3 in this application that simultaneously stores the first program code and the second program code. And, compared to NOR type flash memory, the speed of NAND type flash memory is faster.

As a preferred embodiment,

Both the I/O data terminal of the baseboard management controller 1 and the I/O data terminal of the platform path controller 2 are connected to the I/O data terminal of the flash memory;

The addressing space of the baseboard management controller 1 corresponds to the first program code;

The addressing space of the platform path controller 2 corresponds to the second program code.

Specifically, the address line and the data line of the NAND flash memory are shared, that is, its I/O port can be used to transmit the address code of the addressing space, and can also be used to transmit specific data information. Therefore, a NAND flash memory can be used, and the baseboard management controller 1 and the platform path controller 2 are address-encoded, so that the baseboard management controller 1 can read the first program code, and the platform path controller 2 can read the first program code. to the second program code. Of course, those skilled in the art can design the specific storage address of the first program code or the second program code by themselves, and then design the addressing code of the baseboard management controller 1 and the addressing code of the platform path controller 2 accordingly. This is not limited.

As a preferred embodiment, the control signal terminal connecting the baseboard management controller 1 to the flash memory 3 includes:

a first clock signal terminal, a first enabling terminal, a first data output terminal, and a first data input terminal;

The control signal terminals used by the platform path controller 2 to connect with the flash memory 3 include:

A second clock signal terminal, a second enabling terminal, a second data output terminal, and a second data input terminal.

Specifically, due to the information transmission requirements for system start-up and operation, the baseboard management controller 1 may have at least four signal control terminals: a first clock signal terminal, a first enable terminal, a first data output terminal and a first data input terminal. . Wherein, the first clock signal terminal SCLK is used to transmit the clock signal to ensure the normal operation of the chip; the first enable terminal CS is used to transmit the enable signal to enable the chip, that is, to make the chip start to work; the first data output terminal MISO is used for transmitting data output signals; the first data input terminal MISI is used for transmitting data input signals. The platform path controller 2 is similar to it, and will not be repeated here.

Please refer to FIG. 2 . FIG. 2 is a chip pin diagram of a flash memory 3 provided in this application.

As a preferred embodiment,

Both the first clock signal terminal and the second clock signal terminal are connected to the third clock signal terminal of the flash memory 3;

Both the first enabling terminal and the second enabling terminal are connected to the third enabling terminal of the flash memory 3;

Both the first data output end and the second data output end are connected to the third data output end of the flash memory 3;

Both the first data input terminal and the second data input terminal are connected to the third data input terminal of the flash memory 3 .

Specifically, a flash memory chip as shown in FIG. 2 may be used. Wherein, CLK is the third clock signal end of the flash memory 3, S_N is the third enabling end of the flash memory 3, SO is the third data output end of the flash memory 3, and SI is the third data input end of the flash memory 3, which are respectively used to communicate with The corresponding control signal terminals of the baseboard management controller 1 and the platform path controller 2 are connected.

As a preferred embodiment, the I/O bit width of the flash memory 3 is 8 bits.

Specifically, a flash memory 3 with a bit width of 8 bits can generally be used. As shown in the flash memory 3 shown in FIG. 2 , DU0 , DU1 , DU2 , DU3 , DU4 , DU5 , DU6 and DU7 are 8-bit data/address lines respectively. Of course, the larger the data bit width, the higher the processing speed of the system, but the cost of the flash memory 3 is also higher, which can be selected and set by those skilled in the art, which is not limited in this application.

Each embodiment in the present application is described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same and similar parts of the various embodiments can be referred to each other. As for what is disclosed in the embodiment, since it corresponds to what is disclosed in the embodiment, the description is relatively simple, please refer to the part of the description for relevant parts.

It should also be noted that in this application, relative terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, article or apparatus comprising a set of elements includes not only those elements but also items not expressly listed other elements, or also include elements inherent in the process, article, or equipment. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, article or device comprising said element.

The technical solution provided by the present application has been introduced in detail above. In this paper, specific examples are used to illustrate the principles and implementation methods of the present application, and the descriptions of the above embodiments are only used to help understand the present application and its core ideas. It should be pointed out that those skilled in the art can make some improvements and modifications to the application without departing from the principles of the application, and these improvements and modifications also fall within the protection scope of the claims of the application.

Claims (6)

1. a kind of computer motherboard circuit, which is characterized in that including baseboard management controller, platform path controller and flash memory；

The flash memory is connect with the baseboard management controller and the platform path controller respectively, and is stored with the first program Code and the second program code；

The baseboard management controller is for obtaining and executing first program code to carry out substrate management control；

The platform path controller is for obtaining and executing second program code to carry out platform path control.

2. computer motherboard circuit according to claim 1, which is characterized in that the flash memory is NAND-type flash memory.

3. computer motherboard circuit according to claim 2, which is characterized in that

The I/O data terminal of the I/O data terminal of the baseboard management controller and the platform path controller with the flash memory I/O data terminal connection；

The addressing space of the baseboard management controller corresponds to first program code；

The addressing space of the platform path controller corresponds to second program code.

4. computer motherboard circuit according to claim 3, which is characterized in that the baseboard management controller and the sudden strain of a muscle The control signal end for depositing connection includes:

First clock signal terminal, the first enable end, the first data output end, the first data input pin；

The platform path controller is used for the control signal end that connect with the flash memory

Second clock signal end, the second enable end, the second data output end, the second data input pin.

5. computer motherboard circuit according to claim 4, which is characterized in that

First clock signal terminal and the second clock signal end are connected to the third clock signal terminal of the flash memory；

First enable end and second enable end are connected to the third enable end of the flash memory；

First data output end and second data output end are connected to the third data output end of the flash memory；

First data input pin and second data input pin are connected to the third data input pin of the flash memory.

6. computer motherboard circuit according to any one of claims 1 to 5, which is characterized in that the I/O bit wide of the flash memory It is 8.