CN207742939U - A kind of insertion ECC reading circuit devices for MLC NAND flash storages - Google Patents
A kind of insertion ECC reading circuit devices for MLC NAND flash storages Download PDFInfo
- Publication number
- CN207742939U CN207742939U CN201820051423.XU CN201820051423U CN207742939U CN 207742939 U CN207742939 U CN 207742939U CN 201820051423 U CN201820051423 U CN 201820051423U CN 207742939 U CN207742939 U CN 207742939U
- Authority
- CN
- China
- Prior art keywords
- circuit
- data
- nand flash
- reading
- mlc nand
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000003860 storage Methods 0.000 title description 124
- 230000014759 maintenance of location Effects 0.000 title description 57
- 238000003780 insertion Methods 0.000 title description 12
- 230000037431 insertion Effects 0.000 title description 12
- 230000015654 memory Effects 0.000 claims abstract description 84
- 238000012795 verification Methods 0.000 claims description 17
- 238000012937 correction Methods 0.000 claims description 16
- 230000002093 peripheral effect Effects 0.000 claims description 16
- 239000000872 buffer Substances 0.000 claims description 4
- 208000011580 syndromic disease Diseases 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 6
- 238000013461 design Methods 0.000 abstract description 3
- 230000005662 electromechanics Effects 0.000 description 33
- 238000003491 array Methods 0.000 description 26
- 230000005611 electricity Effects 0.000 description 10
- 230000005540 biological transmission Effects 0.000 description 8
- 230000003455 independent Effects 0.000 description 7
- 241001269238 Data Species 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Landscapes
- Read Only Memory (AREA)
Abstract
提供了一种用于MLC NAND Flash存储器的嵌入ECC读取电路装置，包括：ECC译码器电路、读取状态机电路。对MLC NAND Flsah存储器读取操作时，从MLC NAND Flash存储器的阵列单元读出的数据经过ECC解码器译码后读出至I/O口。MLC NAND Flash存储器的嵌入ECC读取电路装置，具备一定的纠正读取数据出错的能力，从而很大程度上解决了MLC NAND Flash存储器读取操作中数据易出错的问题，降低了外部NAND Flash存储控制器的设计复杂度，极大地提高了MLC NAND Flash存储器芯片的可靠性，解决了现有存储器可靠性技术瓶颈。
Provided is an embedded ECC reading circuit device for MLC NAND Flash memory, comprising: an ECC decoder circuit and a reading state machine circuit. When reading the MLC NAND Flsah memory, the data read from the array unit of the MLC NAND Flash memory is decoded by the ECC decoder and then read to the I/O port. The embedded ECC reading circuit device of MLC NAND Flash memory has a certain ability to correct errors in reading data, thus largely solving the problem of error-prone data in the reading operation of MLC NAND Flash memory and reducing the external NAND Flash memory. The design complexity of the controller greatly improves the reliability of the MLC NAND Flash memory chip and solves the bottleneck of the existing memory reliability technology.
Description
Technical field
The utility model is related to flash memory (Flash Memory) memory technology fields, and in particular to one kind being used for MLC
Insertion ECC (the Error Correcting of NAND Flash (Multi Level Cell, multi-layered unit flash memory) memory
Code, error checking and correction) reading circuit device.
Background technology
With the rapid development of electronic information technology, the data of intelligent movable equipment, network data center and server are deposited
Explosive growth is presented in reserves.Demand of the data storage to capacity of memory device constantly drive flash memories rapidly to
More extensive, more high density, higher reliability direction is developed.NAND flash storages as non-volatile flash memory chip,
It has obtained widely grinding by feat of the features such as high density, large capacity in fields such as electronic system, communication system, computer systems
Study carefully and applies.However, the characteristic size with integrated circuit technology constantly reduces, and the continuous expansion of capacity of memory device, chip
Integrated level higher, the NAND flash storage chips of research and development more capacity become the power of memory development.It is existing
The NAND flash storage chips in stage, mainstream include SLC NAND flash storages and MLC NAND flash storages
Two kinds, each device can only store a bit data in SLC NAND flash storage chips, so being more likely to little Rong
The small application scenario of amount, error rate.Although the error rate of data is more than SLC NAND in MLC NAND flash storage chips
Flash storage chip, but each device can store two bits of data, institute in MLC NAND flash storage chips
With in equal areas and in the case of with quantity device, the memory capacity of MLC NAND flash storage chips is SLC
Twice of NAND Flash memory chips.It can be seen that the application scenario of MLC NAND Flash is more extensive.
In MLC NAND Flash, since there are four types of threshold values to be distributed for it, therefore it is being programmed, is being easy in reading process
There is Data flipping, easily causes data read errors.In addition, for the high performance requirement such as field of aerospace, military domain
Application field, to MLC NAND flash storage chips have more stringent high reliability request, therefore, exploitation height can
Become the important research of memory area by the MLC NAND flash storage chips of property.In the memory circuit of the prior art
In device, encoding and decoding algorithm is not added in memory inside, when especially for read operation, due to NAND Flash device technologies
Etc. various reasons, threshold voltage easily drifts about, and when causing memory read operations, corrupt data seriously restricts memory
Reliability.Therefore, while improving memory data reliability, there should be certain control to chip area, and need
Ensure that the efficient execution for reading algorithm and the correctness for reading data, the technology for becoming MLC NAND flash storages field are difficult
Point.
Invention content
The technical problem to be solved by the utility model is to provide a kind of insertions for MLC NAND flash storages
ECC reading circuit devices are embedded in ECC decoder circuits, to MLC NAND in MLC NAND flash storage chips
When Flash memory programs operate, the data to be programmed transfer data to MLC NAND after being encoded by ECC encoder
In Flash memory arrays；When to MLC NAND flash storage read operations, from MLC NAND flash storages
The data that array is read read out to I/O mouthfuls after ECC decoder for decoding.ECC is embedded in MLC NAND flash storages to compile
Decoder module has the ability of certain correction read-write corrupt data, to largely solve to MLC NAND Flash
The error-prone problem of memory data in read operation substantially increases the reliable of MLC NAND flash storage chips
Property, reduce the design complexities of external NAND Flash storage controls.
In order to solve the above technical problems, the utility model provides a kind of insertion for MLC NAND flash storages
ECC reading circuit devices, including：ECC decoder circuits, reading state electromechanics road；
The ECC decoder circuits are connected with caching of page circuit, are used for when reading storage operation, by caching of page electricity
The page of data of road storage is sent to ECC decoders into row decoding, and to the correcting data error of error；
Reading state electromechanics road is connected with peripheral high-voltage control circuit, is connected with memory array cell circuit
It connects, is connected with ECC decoder circuits, read out to caching of page circuit from memory array cell for controlling data, and depositing
Memory array cell word lines provide the logic control for reading voltage, and transfer data to IO after ECC decoder for decoding and connect
The overall logic control of mouth circuit；
The ECC decoder circuits include：It corrects minor counting circuit, errors present counting circuit, money search circuit, delay
Fifo circuit and error correcting circuit are deposited, correction minor circuit is entangled with errors present counting circuit, money search circuit and mistake
Positive circuit is sequentially connected, and the caching fifo circuit is connected with error correcting circuit, for being executed in MLC NAND Flash
When reading data from array, to reading data into row decoding error correction.
The caching fifo circuit caches the data bit and check bit come in from the transmission of caching of page circuit, and is transmitted
To error correcting circuit, it is compared by error correcting circuit with the data of money search circuit, corrects error data.
The ECC decoder circuits can correct 8 bit datas to every 4096 bit data.
Reading state electromechanics road includes：LSB digital independents control module, MSB data read control module, read control
State machine circuit processed reads verification circuit,
The LSB digital independents control module generates the first reading control signal and is sent to reading state of a control electromechanics road,
LSB logic control signals are generated, the read operation of the LSB data of MLC NAND flash storages is controlled；
The MSB data reads control module generation the second reading control signal and is sent to reading state of a control electromechanics road,
MSB volumes of control signals are patrolled in generation, control the read operation of the MSB data of MLC NAND flash storages；
Reading state of a control electromechanics road is connected to reading verification circuit, and mould is controlled by LSB digital independents for receiving
Block, MSB data read the logic control signal of control module transmission, and according to the Last status for reading state of a control machine, really
Surely next state on state of a control electromechanics road is read, the reading state of a control electromechanics routing digital circuit is made；
Reading verification circuit is connected to I/O interfaces, is patrolled for receives that reading state of a control electromechanics road sends
The state of collecting, verifies the correctness of read data, and is finally transferred to I/O interfaces.
Description of the drawings
Fig. 1 is embedded in the installation drawing of ECC circuit according to the MLC NAND flash storages of the utility model one embodiment；
Fig. 2 is according to the MLC NAND flash storage threshold value distribution maps of the utility model one embodiment；
Fig. 3 is embedded in ECC programming operation circuits according to the MLC NAND flash storages of the utility model one embodiment
Block diagram；
Fig. 4 is embedded in ECC programming operation flows according to the MLC NAND flash storages of the utility model one embodiment
Figure；
Fig. 5 is embedded in the LSB programming operations of ECC according to the MLC NAND flash storages of the utility model one embodiment
Flow chart；
Fig. 6 is embedded in the MSB programming operations of ECC according to the MLC NAND flash storages of the utility model one embodiment
Flow chart；
Fig. 7 is embedded in ECC read operation frameworks according to the MLC NAND flash storages of the utility model one embodiment
Figure；
Fig. 8 is distributed according to the MLC NAND flash storages LSB and MSB data threshold value of the utility model one embodiment
Figure；
Fig. 9 is embedded in ECC read operation flows according to the MLC NAND flash storages of the utility model one embodiment
Figure；And
Figure 10 is embedded in the erasing operation stream of ECC according to the MLC NAND flash storages of the utility model one embodiment
Cheng Tu.
Figure 11 is according to the reading circuit device for NAND flash storages of the utility model one embodiment.
Figure 12 is according to the reading state machine circuit structure diagram of the utility model one embodiment.
Specific implementation mode
Specific embodiment below represents the exemplary embodiment of the utility model, and substantially merely illustrative explanation
And it is unrestricted.In the description, it is special described in the embodiment to refer to that " one embodiment " or " embodiment " means to combine
Determine feature, structure or characteristic to be included at least one embodiment of the utility model.In addition, the following embodiments and the accompanying drawings is said
In bright, to an example of the memory of the utility model, it will be appreciated by one of ordinary skill in the art that MLC NAND
Refer to a NAND Flash array in memory area in Flash (Multi-Level Cell, multi-layered unit flash memory) memory
In device cell storage can store two bits, i.e., its there are four types of threshold value be distributed.In MLC NAND flash storage cores
Piece is internally embedded ECC (Error Correcting Code, error checking and correction) circuit, for NAND flash storages
It can be corrected and compiling under the premise of meeting hardware area requirement with feature error-prone in read operation, ECC circuit programming
The data to malfunction in journey and read operation, to largely improve the reliability of MLC NAND flash storage chips.
The utility model proposes technical solution illustrated by example of the present embodiment, which not just limits MLC
NAND flash storage chips, for other kinds of NAND flash storages such as SLC (Single Level Cell, list
Layer unit flash memory) NAND Flash flash chips and TLC (Triple-Level Cell) NAND Flash flash chips be equally suitable
With.
The utility model is further described with reference to the accompanying drawings and detailed description.
In a kind of insertion ECC reading circuit devices for MLC NAND flash storages of the utility model embodiment
Memory array cell device use MLC NAND flash storage part units, in MLC NAND flash storage circuits
Middle embedded ECC programmed circuits module encodes for realizing the data come into from I/O port through ECC encoder, and controlling will be after coding
Data be programmed to memory array cell；Its programmed state machine circuit is embedded in for realizing MLC NAND flash storages
The a whole set of programming operation algorithm of ECC；ECC reading circuit modules are embedded in MLC NAND flash storages, are realized for controlling
From the page of data that memory array cell circuit is read out to caching of page circuit, and control is stored in the one of caching of page circuit
Page data into row decoding, and realizes the error correction data of a capability through ECC decoders；Reading state machine circuit control therein is real
The a whole set of read operation algorithm of I/O port is now read data to from memory array cell.To the behaviour of MLC NAND flash storages
Work includes programming operation, read operation, erasing operation, when MLC NAND flash storage programming operations, by the utility model
Insertion ECC programmed circuits module by data to be programmed after ECC encoder encodes, generate data bit and check bit it is common
It is sent to caching of page circuit, then the data in caching of page are programmed in MLC NAND flash storage arrays, realizes programming
Operation.When MLC NAND flash storage read operations, realized from array by the utility model insertion ECC reading circuit modules
The data bit of reading and check bit are sent to ECC decoder electricity by the data of reading to caching of page circuit, caching of page circuit jointly
Road is decoded by ECC decoder circuits, by decoded data transmission to I/O port.Embedded ECC coding/decoding modules are directed to
The characteristics of random error, easily occurs for MLC NAND Flash, and encoding and decoding are carried out using BCH code, realizes that every 4096 data are permissible
8 data of error correction, and hardware circuit is smaller, is being compiled to MLC NAND Flash memories to largely solve
The error-prone problem of data in journey and read operation greatly enhances MLC NAND flash storage flash chips
Reliability reduces the design difficulty of NAND Flash peripheral controllers circuits.Details are as follows：
It is the installation drawing of the MLC NAND flash storages insertion ECC circuit of the utility model embodiment referring to Fig. 1,
Including memory array cell circuit, row decoder circuits, column decoder circuitry, caching of page circuit, logic control circuit and
IO interface circuits.The memory array cell circuit, row decoder circuits, column decoder circuitry, caching of page circuit,
Logic control circuit and I/O interface circuitry are all made of integrated circuit.The memory array cell circuit is separately connected row
Decoder circuit and column decoder circuitry, memory array cell circuit be sequentially connected caching of page circuit, logic control circuit with
And I/O interface circuitry；The memory array cell circuit constitutes storage array of data unit, completes storing to finger for data
Determine the memory array cell of address；
The row decoder circuits be used for memory program, reading, erasing operation row address into row decoding, will decode
Row address afterwards is sent to the specified region of memory array cell；
The column decoder circuitry be used for memory program, reading, erasing operation column address into row decoding, will decode
Column address afterwards is sent to the specified region of memory array cell；
The caching of page circuit is connected with ECC encoder circuit, ECC decoder circuits, is used in programming operation,
After ECC encoder circuit encodes programming data, entire page data is sent to caching of page circuit, for one after coding
Page data is cached, and final page buffer circuit will brush under the programming data of whole page in memory array cell；It is grasped reading
When making, the page of data in memory array cell is stored first carries out caching into caching of page circuit, then again through ECC
It is sent to I/O interface after decoder circuit decoding；The caching of page circuit includes reading circuit, digital conversion circuit and latches electricity
Road, the reading circuit are used to read the electric current of a row memory array cell in memory array cell circuit, the number
Conversion circuit is used to the current value size of the memory array cell of reading being converted to digital logic value, and the latch cicuit is used
In the digital logic value that latched digital conversion circuit is converted to.
The logic control circuit provides embedded ECC programmed circuits module, embedded ECC reading circuits module and erasing shape
Overall logic algorithm control of the state electromechanics road to the programming operation of MLC NAND flash storages, read operation and erasing operation
System, including：Embedded ECC programmed circuits module, embedded ECC reading circuits module, erase status login module and peripheral high pressure
Control circuit module, wherein：
The embedded ECC programmed circuits module is sequentially connected with caching of page circuit and peripheral high-voltage control circuit, for real
The data now come in from IO oral instructions encode and the data after coding are programmed to memory array cell；The embedded ECC
Programmed circuit module further includes：ECC encoder circuit, programmed state machine circuit, the ECC encoder circuit and the caching of page
Circuit is connected, and coming into data from I/O port for reception is encoded, and encodes the data bit of generation and check bit is sent to page and delays
Deposit circuit caching；The programmed state machine circuit includes programming verification circuit, programmed state machine circuit and ECC encoder circuit phase
Connection, is connected with caching of page circuit, is connected with peripheral high-voltage control circuit, and the programmed state machine circuit is for controlling number
It is programmed to patrolling for caching of page circuit according to the data bit and check bit generated through ECC encoders coding, and by the data after coding
Control is collected, the programming verification circuit is programmed to for verifying different programmed state data in corresponding threshold range.
The embedded ECC reading circuits module is sequentially connected with caching of page circuit and peripheral high-voltage control circuit, for controlling
System, which is realized from the page of data that memory array cell circuit is read out to caching of page circuit and control, is stored in caching of page circuit
Page of data into row decoding；The embedded ECC reading circuits module further includes：ECC decoder circuits, reading state are electromechanical
Road, the ECC decoder circuits are connected with the caching of page circuit, are used for when reading storage operation, from caching of page electricity
The page of data of road storage is sent to ECC decoders into row decoding, and to the correcting data error of error；Reading state electromechanics road
It is connected with peripheral high-voltage control circuit, is connected with memory array cell circuit, is connected with ECC decoder circuits, institute
It states reading state electromechanics road and reads out to caching of page circuit from memory array cell for controlling data, and in memory array list
First wordline provides the logic control for reading voltage, and the whole of I/O interface circuitry is transferred data to after ECC decoder for decoding
Body logic control.The ECC decoder circuits, reading state electromechanics road are made of digital integrated circuit.
Erase status electromechanics road is connected with peripheral high-voltage control circuit, is connected with memory array cell circuit
It connects, when for memory erasing operation, control erasing high pressure is applied to memory array cell, to specified memory array
Block address realizes erasing control in unit；
The periphery high-voltage control circuit is connected with embedded ECC coding circuits, is connected with embedded ECC reading circuits,
It is connected with erase status electromechanics road, is used for when programming either reading or erasing operation to memory array cell device
Wordline and/or bit line apply the control of required high pressure and staged pulse voltage；
The I/O interface circuitry is used for external data interaction.
MLC NAND flash storage array circuits are left and right to be separately connected row decoder circuits and column decoder circuitry,
For to MLC NAND flash storages programming operation, either read operation or the row address of erasing operation, column address to carry out
Decoding, and it is sent to the specified region of MLC NAND flash storage arrays；In MLC NAND flash storages array electricity
Caching of page circuit is connected to below road, caching of page circuit is used in programming operation, through encoder circuit in ECC coding modules
Generated data bit and check bit carry out data buffer storage after being encoded to programming data, and final page buffer circuit is by the data of whole page
Position and check bit one remove in brush to MLC NAND flash storage arrays, realize that data are stored to MLC NAND Flash and dodge
In depositing；In read operation, from MLC NAND flash storage arrays using page as unit read data bit and check bit to
It is cached in caching of page circuit, then, the page of data position cached in caching of page and check bit is sent to the reading electricity of embedded ECC
The page of data (including data bit and check bit) of caching of page is decoded through ECC decoder circuits, and calls reading simultaneously by road module
It takes state machine circuit to realize that data read out to the algorithm control of I/O port whole process, finally connects the data transmission of reading to I/O
Mouthful.The programmed circuit module of embedded ECC includes in Fig. 1：ECC encoder circuit, programmed state machine circuit, wherein ECC is encoded
For being encoded to programming data, the data bit and check bit for encoding generation are sent in caching of page circuit device circuit together；
Programmed state machine circuit includes programming verification circuit, and programmed state machine circuit is connected with ECC encoder circuit, with caching of page electricity
Road is connected, and is connected with peripheral high-voltage control circuit, and the programmed state machine circuit is compiled for controlling data through ECC encoder
The data bit and check bit that code generates, and the data after coding are programmed to the logic control of caching of page circuit；The programming
Verification circuit is programmed to for verifying different programmed state data in corresponding threshold range.The reading circuit module of embedded ECC in Fig. 1
Including：ECC decoder circuits, reading state electromechanics road, wherein ECC decoder circuits are used to carry out the data in caching of page
Decoding, including correction minor counting circuit, errors present counting circuit, money search circuit, caching fifo circuit and mistake are entangled
Code word (including the number of mistake is occurred first for the possibility read in MLC NAND Flash by positive circuit, ECC decoder circuits module
According to position and check bit) it is sent to caching of page circuit, numeral is sent to syndrome counting circuit module by caching of page circuit, according to companion
The numeral for whether being all 0 judgement reading with formula has inerrancy.I/O interface is directly transferred data to if inerrancy；If having
Mistake then by errors present counting circuit, carries out hardware circuit calculating to error polynomial using BM iterative algorithms and money is searched for
(Chien search) circuit module finds number wrong within the scope of error correcting capability and position, then with caching FIFO (First in
First out) circuit caching code word comparison realize wrong data error correction, be finally completed ECC decoding；Wherein：
Correction minor circuit is sequentially connected with errors present counting circuit, money search circuit and error correcting circuit, is used for
Sub- calculating is corrected to the data bit and check bit that are come into from caching of page circuit, and minor circuit counting is corrected according to calculating
Result be sent to errors present counting circuit, be resent to money search circuit, the search result of money search circuit iteration passed
It send to error correcting circuit；The caching fifo circuit is connected with error correcting circuit, caching from caching of page circuit transmit into
The data bit and check bit come, and are sent to error correcting circuit, and error correcting circuit is by the number of itself and money search circuit
According to being compared, error data is corrected；
All operationss of the reading state machine circuit control data from MLC NAND flash storages arrays to I/O port
Algorithm controls.Logic control circuit further includes peripheral high-voltage control circuit, erase status electromechanics road in Fig. 1.Peripheral high voltage control
Circuit is used for when to MLC NAND Flash programmings, reading and erasing operation, required to MLC NAND Flash array lists
The wordline and/or bit line of component apply the control of high pressure.It realizes to specified MLC NAND on erase status electromechanics road in Fig. 1
The block region of flash storage array carries out erasing control operation, and control erasing high pressure is applied to memory array cell, to referring to
Block address realizes erasing control in fixed memory array cell.
It is MLC NAND flash storage threshold value distribution maps, programming operation is substantially exactly to store a charge in referring to Fig. 2
In floating boom, so that threshold voltage increases, since each device of MLC NAND flash storages can store 2 bit numbers
According to, therefore with 4 kinds of threshold values shown in Fig. 2 distribution.As shown in Fig. 2, E states be erasing state, D1, D2, D3 states be respectively three kinds not
Same programming thresholds state.Homomorphism has not divided MLC NAND Flash threshold regions to E states, D1 states, D2 states, D3 states this four.By
Different verifying voltage V is needed in different programmed threshold voltage rangesVFY1, VVFY2, VVFY3To verify whether to be programmed into setting
Threshold value state, the V in Fig. 2READ1Voltage, VREAD2Voltage, VREAD3Voltage is respectively the voltage for reading different data and being applied.MLC ratios
SLC capacity is big, but its narrower threshold value distribution also proposes its reliability harsh requirement, therefore is directed to the problem,
A kind of insertion ECC reading circuits device for MLC NAND flash storages of the present embodiment is embedding by ECC coding-decoding circuits
Entering into MLC NAND flash storage flash chips has high reliability.
Referring to Fig. 3, ECC programming operation circuit block diagrams are embedded in for MLC NAND flash storages, are sequentially connected in Fig. 3
It is NAND Flash arrays, caching of page circuit, programmed state machine circuit, I/O interface, wherein NAND Flash arrays or so Ge Lian
Connect row decoding circuit, array decoding circuit, the peripheral high-voltage control circuit of programmed state machine circuit connection, wherein programmed state machine circuit
Circuit is verified including programming, programming verification circuit is for verifying whether different programmed state data are programmed in corresponding threshold range.
MLC NAND flash storages program as unit of page, and page of data to be programmed is sent to embedded ECC by I/O interface circuitry
In programmed circuit module, the size of page of data is 2KB, is encoded and is generated by ECC encoder circuit module per 512Byte data
Data bit and check bit then complete the data encoding of one page by the coding of 4 512Byte data, meanwhile, it is embedding by calling
Enter ECC programmed circuit moulds programmed state machine circuit control programmed algorithm flow in the block, is effectively carried out the coding and volume of data
Journey algorithm operating.Its peripheral high-tension circuit is supplied to MLC NAND flash storage array words for required in programming operation
The control of line voltage.Meanwhile the data bit and check bit generated after ECC encoder encodes is sent to caching of page circuit together
In, the address location specified in being brushed under the page of data in caching of page circuit to MLC NAND flash storage arrays,
Complete programming operation.ECC coding modules are embedded in programmed algorithm shown in Fig. 3 to improve the reliability of programming data.Programming
State machine circuit realizes entire programmed algorithm control, calls come implementation levelization in such a way that programmed algorithm is nested, sets in this way
The advantages of meter, is to keep whole system orderliness clear and can improve efficiency.
Referring to Fig. 4, ECC programming operation flow charts are embedded in for MLC NAND flash storages, using insertion shown in FIG. 1
ECC programmed circuit modules realize that programming operation flow algorithm, MLC NAND flash storage programming operations include：
Step 1：Send the instruction of period 1 programming operation；
Step 2：The MLC NAND flash storages address to be programmed is written；
Step 3：The page data to be programmed is written, the page data of programming is sent to embedded ECC programmed circuits module, is adopted
It completes to encode the page data to be programmed with embedded ECC programmed circuit moulds ECC encoder circuit in the block；
Step 4：Send the instruction of second round programming operation；
Step 5：Page data after ECC encoder encodes is sent to the caching of page electricity of MLC NAND flash storages
The caching to page data is completed on road；
Step 6：The data stored in caching of page circuit are programmed in MLC NAND flash storage arrays.Wherein,
The embedded ECC programmed circuits module is as shown in figure 3, specifically include：
1, ECC encoder circuit is sent to the page data of the MLC of being programmed to NAND flash storage arrays；
2, ECC encoder circuit encodes page data, and generates data bit and check bit；
3, the coding of programmed state machine circuit control data and data is called to be programmed to MLC NAND flash storage battle arrays
Row.
Shown in Figure 8, MLC NAND Flash are programmed with 4 kinds of threshold value states, write low order LSB data first, will
Brush is waited for MLC NAND flash storage arrays under the low order LSB data of the page data cached in caching of page circuit
After low order LSB data program, low order LSB data are read out；It is loaded into from caching of page circuit again high effectively
The data of position MSB, that completes high significance bit MSB data is programmed to MLC NAND flash storage arrays, is finally completed MLC
The programming operation of NAND flash storages.Referring to Fig. 3, the data that are issued to instructed from a cycle programming operation are programmed to
In MLC NAND flash storage arrays, all algorithms have the programmed circuit mould programmed state machine in the block of embedded ECC
Circuit control is realized.After the data stored in the circuit by caching of page are programmed to MLC NAND flash storage arrays,
Programming includes the programming of low order LSB data and the programming of high significance bit MSB data, is specifically included：
1, the programming of low order LSB data is carried out first, by the low order of the page data cached in caching of page circuit
LSB data are programmed to MLC NAND flash storage arrays；
2, after waiting for the programming of low order LSB data, low order LSB data are read；
3, the data of high significance bit MSB are loaded into from caching of page circuit again, it, will in conjunction with the low order LSB data of reading
High significance bit MSB data is programmed to MLC NAND flash storage arrays.
Referring to Fig. 5, the LSB programming operation flow charts that ECC is embedded in for MLC NAND flash storages wait for as shown in Figure 4
Programming data is stored in caching of page circuit after ECC module encodes, and caching of page circuit splits data into low order LSB data
Programming and high significance bit MSB are programmed in MLC NAND flash storage arrays, and wherein low order LSB programmings include：
Step 1：The low order LSB data programmed will be needed to be loaded into register, and judge low order LSB data
It is 1 or 0, if it is 1, then the bit line of the array device in MLC NAND flash storages applies the electricity that size is VDD
Source voltage；If it is 0, then the bit line of the array device in MLC NAND flash storages applies the voltage that size is 0V；
Step 2：Apply initial programming voltage in the wordline of MLC NAND flash storage array devices, waits for MLC NAND
After the completion of the wordline initial voltage and bit-line voltage of array device in flash storage all apply, to MLC NAND Flash
The wordline of memory array device applies staged pulse voltage；
Step 3：Apply a staged pulse voltage, after a complete step pulse voltage to be applied, carries out one-time programming
Verification operation；
Step 4：Until whether judgement low order LSB data are programmed within the scope of low order LSB data thresholds, if compiling
Within the scope of journey to low order LSB data thresholds, then low order programs successfully, otherwise continues to execute step 3 and its later
Step.
Referring to Fig. 6, it is embedded in the MSB programming operation flow charts of ECC for MLC NAND flash storages, waits for low order
After the completion of LSB programmings, high significance bit MSB data programming is executed, including：
Step 1：Low order LSB data are read, in conjunction with the low order LSB data of reading, are loaded into be programmed
High significance bit MSB data；
Step 2：Apply staged pulse voltage in the wordline of MLC NAND flash storage array devices, wherein rank
The ladder step value of ladder type pulse voltage is controlled by STEP_CNT；
Step 3：Often apply a staged pulse voltage and carry out one-time programming verification operation, until completing to high significance bit
MSB data program.MLC NAND flash storage read operations are carried out as unit of page, as shown in Fig. 2, MLC
One device of NAND flash storages can store two bits of data, and wherein E is erasing state, and D1, D2, D3 is three kinds different
Programmed state then needs to apply three reading voltage V due to read four kinds of different threshold value statesREAD1, VREAD2, VREAD3It could read
Go out four kinds of corresponding threshold value states.MLC NAND flash storages are deposited in read operation due to reading interference and NAND Flash
The influence of memory array, it is easy to Data flipping occur, cause corrupt data.Therefore in order to solve this problem, in MLC
Embedded ECC algorithm module in NAND Flash read operations, realizes that every 4096 bit data corrects 8 bit datas.
It is shown in Figure 7, it is embedded in ECC read operation Organization Charts, MLC NAND for MLC NAND flash storages
Flash memory array circuits are left and right to be separately connected row decoder circuits and column decoder circuitry, for MLC NAND
Flash storage programming, reading, the row address of erasing operation, column address are sent to MLC NAND Flash and deposit into row decoding
The specified region of memory array；The then caching of page circuit in succession below MLC NAND flash storage array circuits, is used for
In resume studies extract operation, the page of data of MLC NAND flash storage arrays is kept in caching of page circuit.Phase successively
What is connected is embedded ECC reading circuits, and the reading circuit of embedded ECC includes ECC decoder circuits, is carried out for the data to reading
Decoding realizes that every 4096 bit data can correct 8 bit datas and reading state electromechanics road, and behaviour is read for controlling realization
Make algorithm.Peripheral high-tension circuit is used to provide the high pressure needed for reading.When read operation, when sending reading order, embedded ECC
The reading state electromechanics road of reading circuit calls and accordingly reads algorithm, and page of data in MLC NAND Flash arrays is read
Into caching of page circuit, the page of data in caching of page circuit is divided 4 times and is sent to the decoding of ECC decoder circuit module, this is translated
Code module can realize the correcting data error to reading, error correcting capability 8bits/4096bits, finally by the data transmission after decoding
To I/O mouthfuls of output end.Complete the read operation of MLC NAND Flash.
Referring to Fig. 9, ECC read operation flow charts are embedded in for MLC NAND flash storages, MLC NAND Flash's
Read operation includes reading low order LSB data and high significance bit MSB data, is had for MLC NAND Flash are low referring to Fig. 8
Position LSB and the distribution of high significance bit MSB data are imitated, it is specific as follows：
Read operation sends period 1 reading order as unit of page；
Write-in needs to read the address of MLC NAND flash storage arrays；
After address writes, the reading order of second period is sent, MLC NAND flash storages, which are called, reads shape
The data read operation in MLC NAND flash storage arrays is completed on state electromechanics road；State machine circuit to be read will be read
After operative algorithm is finished, data brush under in array to be cached in caching of page circuit；
The page data read out is sent to ECC decoder circuit modules and completes decoding by caching of page circuit, after decoding
Data transmission to MLC NAND flash storage interfaces, be finally completed the read operation of MLC NAND flash storages.
The wherein described data that read from MLC NAND flash storage arrays include reading low order LSB data and high significance bit
MSB data：Low order LSB data are read first, apply initial voltage VREAD1Voltage read erasing E states and D1 states it is low effectively
Position LSB data, then apply VREAD3Voltage reads the low order LSB data of D2 states and D3 states, completes low order LSB data
Reading；Judge whether to read high significance bit MSB data at this time, if only needing to read low order LSB data, completes MLC
NAND flash storage read operations；To read high significance bit MSB data, then V is addedREAD2Voltage reads high significance bit
MSB data completes the read operation of MLC NAND flash storages；
Referring to Figure 10, the erasing operation flow chart of ECC is embedded in for MLC NAND flash storages, details are as follows：
Erasing operation in blocks, sends period 1 erasing order；
Write-in needs to wipe the block address of MLC NAND flash storage arrays；
Send second period erasing order；
Using FN tunneling mechanisms, the erasing block in MLC NAND flash storage arrays is chosen, starts erase status machine
Circuit；Wherein, erase status electromechanics road realizes that erasing operation algorithm includes：
Step 1：Apply 0V voltages in the word line end of MLC NAND flash storage array devices, in MLC NAND
The substrate terminal of Flash memory array devices applies initial erasing voltage；
Step 2：It is wiped into row block；
Step 3：Erasing operation is verified；
Step 3：Judge whether erasing passes through, if passing through, completes erasing operation；Continue in MLC NAND if not passing through
The substrate terminal of flash storage array applies stairstepping pulse voltage and carries out erasing operation, often increases a staged pulse electricity
Pressure, erasing staged pulse voltage step value control ERS_CNT add 1；
Step 4：Into whether being the judgement for wiping staged pulse voltage step value ERS_CNT maximum values, if ERS_CNT reaches
To maximum value, then this erasing operation fails；If ERS_CNT is not up to maximum value, step 2 and its later step are continued to execute
Suddenly.Complete the erasing operation of MLC NAND flash storages insertion ECC.
Referring to Figure 11, to be filled according to the reading circuit for NAND flash storages of the utility model one embodiment
It sets, including：ECC decoder circuits, reading state electromechanics road；
The ECC decoder circuits are connected with the caching of page circuit, for when reading storage operation, page to be delayed
The page of data for depositing circuit storage is sent to ECC decoders into row decoding, and to the correcting data error of error；
Reading state electromechanics road is connected with peripheral high-voltage control circuit, is connected with memory array cell circuit
It connects, is connected with ECC decoder circuits, read out to caching of page circuit from memory array cell for controlling data, and depositing
Memory array cell word lines provide the logic control for reading voltage, and transfer data to IO after ECC decoder for decoding and connect
The overall logic control of mouth circuit；
The ECC decoder circuits include：It corrects minor counting circuit, errors present counting circuit, money search circuit, delay
Fifo circuit and error correcting circuit are deposited, correction minor circuit is entangled with errors present counting circuit, money search circuit and mistake
Positive circuit is sequentially connected, and the caching fifo circuit is connected with error correcting circuit, for being executed in MLC NAND Flash
When reading data from array, to reading data into row decoding error correction.
The caching fifo circuit caches the data bit and check bit come in from the transmission of caching of page circuit, and is transmitted
To error correcting circuit, it is compared by error correcting circuit with the data of money search circuit, corrects error data.
The ECC decoder circuits can correct 8 bit datas to every 4096 bit data.
The ECC decoder circuits include：It corrects minor counting circuit, errors present counting circuit, money search circuit, delay
Fifo circuit and error correcting circuit are deposited, reading state electromechanics road is all made of digital circuit.
Referring to Figure 12, for according to the reading state machine circuit structure diagram of the utility model one embodiment, reading state machine
Circuit includes：LSB digital independents control module, MSB data read control module, read state of a control electromechanics road, read verification
Circuit, the LSB digital independents control module, MSB data read control module, read state of a control electromechanics road, read verification
Circuit is all made of digital circuit and is made.
The LSB digital independents control module generates the first reading control signal and is sent to reading state of a control electromechanics road,
LSB logic control signals are generated, the read operation of the LSB data of MLC NAND flash storages is controlled；
The MSB data reads control module generation the second reading control signal and is sent to reading state of a control electromechanics road,
MSB volumes of control signals are patrolled in generation, control the read operation of the MSB data of MLC NAND flash storages；
Reading state of a control electromechanics road is connected to reading verification circuit, and mould is controlled by LSB digital independents for receiving
Block, MSB data read the logic control signal of control module transmission, and according to the Last status for reading state of a control machine, really
Surely next state on state of a control electromechanics road is read, the reading state of a control electromechanics routing digital circuit is made；
Reading verification circuit is connected to I/O interfaces, is patrolled for receives that reading state of a control electromechanics road sends
The state of collecting, verifies the correctness of read data, and is finally transferred to I/O interfaces.
Finally it should be noted that：Above example is only to illustrate the technical solution of the utility model rather than limits it
System, although the utility model is described in detail with reference to preferred embodiment, those skilled in the art should manage
Solution：It can still be modified or replaced equivalently the technical solution of the utility model, and these are changed or equally replace
Change the spirit and scope that cannot also make modified technical solution be detached from the technical solution of the utility model.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820051423.XU CN207742939U (en) | 2018-01-12 | 2018-01-12 | A kind of insertion ECC reading circuit devices for MLC NAND flash storages |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820051423.XU CN207742939U (en) | 2018-01-12 | 2018-01-12 | A kind of insertion ECC reading circuit devices for MLC NAND flash storages |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207742939U true CN207742939U (en) | 2018-08-17 |
Family
ID=63122785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201820051423.XU Expired - Fee Related CN207742939U (en) | 2018-01-12 | 2018-01-12 | A kind of insertion ECC reading circuit devices for MLC NAND flash storages |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN207742939U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110851381A (en) * | 2018-08-21 | 2020-02-28 | 爱思开海力士有限公司 | Memory controller, memory device and operating method thereof |
| CN111192620A (en) * | 2019-12-31 | 2020-05-22 | 山东华芯半导体有限公司 | Method for optimizing NAND Flash read reference voltage in SSD |
| CN112286716A (en) * | 2020-10-21 | 2021-01-29 | 天津津航计算技术研究所 | 1024-byte storage system error control module |
-
2018
- 2018-01-12 CN CN201820051423.XU patent/CN207742939U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110851381A (en) * | 2018-08-21 | 2020-02-28 | 爱思开海力士有限公司 | Memory controller, memory device and operating method thereof |
| CN111192620A (en) * | 2019-12-31 | 2020-05-22 | 山东华芯半导体有限公司 | Method for optimizing NAND Flash read reference voltage in SSD |
| CN111192620B (en) * | 2019-12-31 | 2023-09-08 | 山东华芯半导体有限公司 | Method for optimizing NAND Flash read reference voltage in SSD |
| CN112286716A (en) * | 2020-10-21 | 2021-01-29 | 天津津航计算技术研究所 | 1024-byte storage system error control module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101405741B1 (en) | Stripe-based non-volatile multilevel memory operation | |
| US8464135B2 (en) | Adaptive flash interface | |
| KR100902008B1 (en) | Memory system including flash memory to store multi-bit data in memory cells | |
| CN103871447B (en) | NAND gate flash memory array and chip and method for accessing, reading and managing the same | |
| TWI442222B (en) | Flash memory device and method for managing a flash memory device | |
| US20130198577A1 (en) | Memory, memory system, and error checking and correcting method for memory | |
| CN207742939U (en) | A kind of insertion ECC reading circuit devices for MLC NAND flash storages | |
| JP2018160065A (en) | Memory system | |
| CN107544748B (en) | Solid-state storage device and data writing method thereof | |
| CN102541678A (en) | Multichannel NAND flash parallel memory controller | |
| CN107068194A (en) | A kind of error correcting coding and corresponding EEPROM applied on EEPROM | |
| US20090307418A1 (en) | Multi-channel hybrid density memory storage device and control method thereof | |
| CN207611609U (en) | a memory circuit | |
| KR20210040463A (en) | Memory subsystem with an in-package sequencer to perform error correction and memory test operations | |
| US11387848B1 (en) | Hierarchical error correction code | |
| CN112420109B (en) | Non-volatile memory devices and storage systems | |
| CN113360089B (en) | Command batching for memory subsystems | |
| JP2009048680A (en) | Storage device | |
| CN109542394A (en) | Controller, semiconductor memory system and the storage system with them | |
| US9892793B1 (en) | Systems and methods for programming data to storage devices | |
| CN102103558A (en) | Multi-channel NANDflash controller with write retransmission function | |
| JP2011044200A (en) | Nonvolatile semiconductor memory | |
| CN117437957A (en) | Memory system, memory device and method of operating memory device | |
| US8036034B2 (en) | Semiconductor storage device equipped with a sense amplifier for reading data and threshold-voltage-information data | |
| CN113066519B (en) | Memory subsystem self-test operation |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180817 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |