CN207705200U - Field-effect tube - Google Patents

Abstract

The utility model relates to a field effect transistor, which adopts a vertical source, drain and grid, on which more carbon nanotubes are adhered side by side as grooves, and the carbon nanotubes are elevated to form a three-dimensional fin field effect transistor device . The use of a vertical gate can save the plane area of the substrate, and can minimize the line width of the process. Elevating carbon nanotubes can increase the ballistic velocity of carriers, and using multiple carbon nanotubes can increase the current density. These designs can significantly improve the performance of field effect transistors. Designing the electrodes into a vertical form can effectively save the plane area of the substrate, making a single field-effect transistor smaller. Ultra-small transistors can not only show quantum effects, but also allow more transistors to be placed on a chip of the same size. Improved chip performance. Elevating the carbon nanotubes so that they do not contact the substrate can increase the ballistic velocity of the carriers and make the transistor have better performance.

Description

FET

technical field

The utility model relates to a field effect tube, in particular to a fin type field effect tube using a carbon nanotube as a conductive groove and a preparation method thereof.

Background technique

In today's information age, integrated (IC) circuits play a pivotal role, and it is the foundation and core of the development of electronic information technology. The rapid development of integrated circuits and the development of modern communication, computer, Internet and multimedia technologies are mutually driven, greatly affecting all aspects of life today, among which field effect transistors used in IC circuits play a pivotal role. Field Effect Transistor (Field Effect Transistor abbreviation (FET)) is referred to as a field effect transistor, which is conducted by a majority of carriers, also known as a unipolar transistor, which belongs to a voltage-controlled semiconductor device.

Following Moore's Law, the feature size of traditional integrated circuit silicon-based transistors continues to shrink, but limited by their own material properties, their minimum size is approaching the limit. With the continuous shrinking of the size, due to the influence of many non-ideal effects, the performance of the device no longer increases proportionally with the proportional reduction of its size.

In order to break through the size limitation of traditional MOS transistors, scientists use carbon nanotubes instead of traditional silicon materials to manufacture field effect devices. Most of the existing carbon nanotube field effect transistors are in the form of two-dimensional single carbon tubes.

Zhong Hanqing et al proposed and studied an asymmetric Schottky contact single-walled carbon nanotube field-effect transistor (SWNT-FET). In this SWNTFET with asymmetric contact structure, two metals with different work functions form Schottky contacts with carbon nanotubes. One end of the carbon nanotube forms a source electrode with a metal aluminum (Al) with a low work function, and the other end forms a drain electrode with a metal palladium (Pd) with a high work function. For Pd/CNT at the drain end, applying a negative gate voltage can reduce the barrier height, facilitate the flow of carriers and increase the current. For the source Al/CNT, a positive gate voltage is applied to reduce the barrier height, which is beneficial to electron injection into the channel and the current is enhanced.

Its performance still has a lot of room for improvement.

Utility model content

Based on this, it is necessary to provide a field effect transistor with better performance for the above technical problems.

A field effect transistor, comprising:

A silicon substrate having a length of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm;

A source disposed on the silicon substrate and perpendicular to the silicon substrate, the source has a height of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm, the source Made of metallic aluminum;

A gate arranged on the silicon substrate and perpendicular to the silicon substrate, the gate has a height of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm, the gate It is made of a metal gold layer and a silicon dioxide insulating layer in contact with each other, and the thickness of the metal gold layer is 4 to 6 nanometers;

A drain disposed on the silicon substrate and perpendicular to the silicon substrate, the drain has a height of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm, the drain Made of metal palladium; and

A plurality of parallel carbon nanotubes in contact with the source electrode, the silicon dioxide insulating layer and the drain electrode, the carbon nanotubes are parallel to the silicon substrate, and the plurality of carbon nanotubes are isolated from each other. The distance between the nearest carbon nanotube of the silicon substrate and the silicon substrate is greater than or equal to 5 nanometers, and the distance between the plurality of carbon nanotubes is greater than or equal to 5 nanometers;

Wherein, the gate is located between the source and the drain; the distance between the gate and the source is greater than or equal to 50 nanometers; the distance between the gate and the drain is greater than or equal to 50 nanometers; the length, width and height of the source, the gate and the drain are equal.

The above field effect tube has the following technical effects:

Vertical electrode structure: the source, drain and gate of the transistor are designed as a columnar three-dimensional structure; this structure saves the plane area, reduces the size of the transistor, and increases the number of transistors on the chip for better performance;

Multiple carbon nanotube groove structure: multiple carbon nanotubes are used as conductive grooves to obtain higher current density than single carbon nanotubes;

Carbon nanotube overhead structure: For traditional field effect transistors, electrons will attract positive charges on the surface of the substrate during the transmission process, so the positive charges on the surface of the substrate move in a wave pattern, and the phonons on the surface of the substrate are polarized and generate heat, which affects the Performance of Field Effect Transistors. Moreover, in the process of electron transmission, due to the mutual attraction of positive charges on the surface of the substrate, the transmission speed is affected and reduced, which greatly affects its electron mobility. Surface phonon polarization and its heat generation improve electron mobility and improve transistor performance;

Carbon nanotubes as conductive trenches: For a traditional metal-oxide-semiconductor field-effect transistor, its current calculation method is where μ _eff represents the carrier mobility, Indicates the aspect ratio, C _ox (V _g -V _t ) indicates the amount of charge in the channel, and V _ds indicates the voltage applied across the source and drain. For field effect transistors with carbon nanotubes as conductive trenches, its current calculation method is Indicates the voltage applied to both ends of the source and the drain, indicates the movement speed of the carrier, indicates the transmission at the contact, and indicates the charge in the channel; it can be found that the field effect transistor using carbon nanotubes as the conductive trench can obtain higher current.

In another embodiment, the silicon substrate has a length of 500 nm, a width of 300 nm and a thickness of 100 nm.

In another embodiment, the source has a height of 500 nm, a length of 300 nm and a width of 100 nm.

In another embodiment, the gate has a height of 500 nm, a length of 300 nm and a width of 100 nm.

In another embodiment, the drain has a height of 500 nanometers, a length of 300 nanometers and a width of 100 nanometers.

In another embodiment, the number of the carbon nanotubes is 3, 4 or 5.

In another embodiment, the distances between the plurality of carbon nanotubes are equal.

In another embodiment, electron beam induced deposition is used to deposit and spot the contact parts of the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain.

In another embodiment, in "Using the electron beam induced deposition method to deposit and spot the contact parts between the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain" The number of explosion points in the electron beam induced deposition method is 1 or 2 or 3 or 4.

A method for preparing a field effect transistor described in any one of the above,

Fabrication of the grid: fix the silicon nanowires on the silicon substrate by electron beam induced deposition, oxidize the silicon nanowires to obtain a silicon dioxide insulating layer, and then apply a metal gold layer on the surface by electron beam induced deposition;

Make the source: apply photoresist on the silicon substrate, use the first mask to expose and then develop, deposit metal aluminum by deposition method, dissolve the photoresist with acetone to peel off the photoresist;

Making the drain: apply photoresist on the silicon substrate, use the second mask to expose and then develop, use the deposition method to deposit metal palladium, and use acetone to dissolve the photoresist to peel off the photoresist;

A plurality of carbon nanotubes are assembled on the surfaces of the source electrode, the silicon dioxide insulating layer and the drain electrode.

In another embodiment, electron beam induced deposition is used to deposit and spot the contact parts of the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain.

In another embodiment, in "Using the electron beam induced deposition method to deposit and spot the contact parts between the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain" The number of explosion points in the electron beam induced deposition method is 1 or 2 or 3 or 4.

Description of drawings

FIG. 1 is a schematic structural diagram of a field effect transistor provided in an embodiment of the present application.

FIG. 2 is a flow chart of a method for manufacturing a field effect transistor provided in an embodiment of the present application.

Detailed ways

In order to make the purpose, technical solution and advantages of the utility model clearer, the utility model will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the utility model, and are not intended to limit the utility model.

Referring to Fig. 1, a field effect transistor includes: a silicon substrate 100, a source electrode 200 arranged on the silicon substrate and perpendicular to the silicon substrate, a source electrode 200 arranged on the silicon substrate and perpendicular to the silicon substrate The gate 300, the drain 400 arranged on the silicon substrate and perpendicular to the silicon substrate, and a plurality of parallel carbon nanometers in contact with the source, the silicon dioxide insulating layer and the drain Tube 500.

The silicon substrate has a length of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm.

The height of the source is 450nm to 600nm, the width is 250nm to 350nm and the thickness is 75nm to 125nm, and the source is made of metal aluminum.

The gate has a height of 450 nanometers to 600 nanometers, a width of 250 nanometers to 350 nanometers and a thickness of 75 nanometers to 125 nanometers, and the gate electrode is made of a metal gold layer 310 and a silicon dioxide insulating layer 320 in contact with each other, The thickness of the metallic gold layer is 4 to 6 nanometers. Preferably, the thickness of the metallic gold layer is 5 nanometers.

The drain has a height of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm, and the drain is made of metal palladium.

The carbon nanotubes are parallel to the silicon substrate, and the distance between the carbon nanotubes closest to the silicon substrate among the plurality of carbon nanotubes is greater than or equal to 5 nanometers from the silicon substrate, and the plurality of carbon nanotubes are The distance between the nanotubes is greater than or equal to 5 nanometers.

The gate is located between the source and the drain. The distance between the gate and the source is greater than or equal to 50 nanometers. The distance between the gate and the drain is greater than or equal to 50 nanometers. The length, width and height of the source, the gate and the drain are equal.

Elevate the carbon nanotubes so that they are not in contact with the substrate. As mentioned above, the field effect transistor is conducted by the majority of carriers. Elevating the carrier can increase the ballistic velocity of the carriers, making the transistor have better performance.

The above field effect tube has the following technical effects:

Vertical electrode structure: the source, drain and gate of the transistor are designed as a columnar three-dimensional structure; this structure saves the plane area, reduces the size of the transistor, and increases the number of transistors on the chip for better performance;

Multiple carbon nanotube groove structure: multiple carbon nanotubes are used as conductive grooves to obtain higher current density than single carbon nanotubes;

Carbon nanotube overhead structure: For traditional field effect transistors, electrons will attract positive charges on the surface of the substrate during the transmission process, so the positive charges on the surface of the substrate move in a wave pattern, and the phonons on the surface of the substrate are polarized and generate heat, which affects the Performance of Field Effect Transistors. Moreover, in the process of electron transmission, due to the mutual attraction of positive charges on the surface of the substrate, the transmission speed is affected and reduced, which greatly affects its electron mobility. Surface phonon polarization and its heat generation improve electron mobility and improve transistor performance;

Carbon nanotubes as conductive trenches: For traditional metal-oxide-semiconductor field-effect transistors, its current calculation method is, where it represents the carrier mobility, the aspect ratio, the charge amount in the channel, and the source and The voltage applied across the drain. For a field effect transistor with carbon nanotubes as a conductive trench, its current calculation method is to indicate the voltage applied to both ends of the source and drain, to indicate the movement speed of the carrier, to indicate the transmission at the contact, and to indicate the charge in the channel ; It can be found that field effect transistors using carbon nanotubes as conductive trenches can obtain higher currents.

In another embodiment, the silicon substrate has a length of 500 nm, a width of 300 nm and a thickness of 100 nm.

In another embodiment, the source has a height of 500 nm, a length of 300 nm and a width of 100 nm.

In another embodiment, the gate has a height of 500 nm, a length of 300 nm and a width of 100 nm.

In another embodiment, the drain has a height of 500 nanometers, a length of 300 nanometers and a width of 100 nanometers.

In another embodiment, the number of the carbon nanotubes is 3, 4 or 5.

In another embodiment, the distances between the plurality of carbon nanotubes are equal.

In another embodiment, electron beam induced deposition is used to deposit and spot the contact parts of the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain.

In another embodiment, in "Using the electron beam induced deposition method to deposit and spot the contact parts between the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain" The number of explosion points 600 in the electron beam induced deposition method is 1 or 2 or 3 or 4.

The contact resistance between carbon nanotubes and metal electrodes is measured. When any two objects are in contact with each other, contact resistance will inevitably occur. It is mainly composed of concentrated resistance and film resistance. Among them, the concentrated resistance refers to the resistance presented due to the contraction (or concentration) of the current line when the current passes through the actual contact surface. When two objects are in contact, even if the surface is very smooth, the contact between them is not the contact of the entire surface at the microscopic level, but the point contact on the contact surface. The actual size of the contact surface is related to the smoothness of the surface of the object and the size of the contact pressure. Membrane Layer resistance refers to the resistance generated after the contamination film at the interface of two objects contacts with each other. There is no truly clean metal surface in the atmosphere. Its surface is either oxidized, absorbs gas film, or deposits dust in the atmosphere. Therefore, at the microscopic level, any contact surface is a polluted surface. When the current passes through the contaminated surface, the film layer resistance will appear. In actual measurement, the concentrated resistance and the film resistance are usually not distinguished, but the total resistance generated when the current flows through the contact surface of two objects is measured. The size of the contact resistance between the two is mainly related to the contact pressure between the carbon nanotubes (CNT) and the work function (work function) of the two materials. The larger the contact pressure and the smaller the difference in work function, the smaller the contact resistance between CNT and metal.

Electron beam induced deposition (EBID) is used to deposit and spot the contact part of carbon nanotubes and gold electrodes, which increases the contact force of CNT/metal, thereby increasing the effective contact area and reducing the contact resistance between the two .

Referring to FIG. 2 , it is a flow chart of a method for manufacturing a field effect transistor provided in an embodiment of the present application.

A method for preparing a field effect transistor described in any one of the above,

S110, fabricating the grid: fixing silicon nanowires on the silicon substrate by electron beam induced deposition, oxidizing the silicon nanowires to obtain a silicon dioxide insulating layer, and then applying a metal gold layer on the surface by electron beam induced deposition.

It can achieve high precision that cannot be achieved by traditional process methods (generation of silicon dioxide insulating layer and metal gold layer)

S120 , making the source electrode: coating photoresist on the silicon substrate, using the first mask to expose and then develop, depositing metal aluminum by deposition method, dissolving the photoresist with acetone to peel off the photoresist.

S130 , fabricating the drain electrode: coating photoresist on the silicon substrate, using a second mask to expose and then develop, depositing metal palladium using a deposition method, dissolving the photoresist with acetone to strip the photoresist.

S140, assembling a plurality of carbon nanotubes on the surfaces of the source electrode, the silicon dioxide insulating layer, and the drain electrode.

In another embodiment, electron beam induced deposition is used to deposit and spot the contact parts of the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain.

In another embodiment, in "Using the electron beam induced deposition method to deposit and spot the contact parts between the plurality of carbon nanotubes and the source, the silicon dioxide insulating layer and the drain" The number of explosion points in the electron beam induced deposition method is 1 or 2 or 3 or 4.

It can be understood that the order of forming the source, gate and drain is not limited.

Specifically, a single CNT is first picked up from the preliminarily dispersed CNT clusters by a multi-operation nanorobot. The root of the CNT is controlled to be aligned with the electrode surface by multi-operation nano-manipulators and gradually approached, and the two are adsorbed to each other under the action of van der Waals force, and the contact force between the CNT and the metal electrode is increased by the electron beam-induced deposition method to increase its contact stability. performance and reduce contact resistance. Finally, a three-dimensional finned carbon nanotube field effect transistor is formed.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the utility model, and the description thereof is relatively specific and detailed, but it should not be understood as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the utility model patent should be based on the appended claims.

Claims (9)

1. A field effect tube, characterized in that, comprising: A silicon substrate having a length of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm; A source disposed on the silicon substrate and perpendicular to the silicon substrate, the source has a height of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm, the source Made of metallic aluminum; A gate arranged on the silicon substrate and perpendicular to the silicon substrate, the gate has a height of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm, the gate It is made of a metal gold layer and a silicon dioxide insulating layer in contact with each other, and the thickness of the metal gold layer is 4 to 6 nanometers; A drain disposed on the silicon substrate and perpendicular to the silicon substrate, the drain has a height of 450 nm to 600 nm, a width of 250 nm to 350 nm and a thickness of 75 nm to 125 nm, the drain Made of metal palladium; and A plurality of parallel carbon nanotubes in contact with the source electrode, the silicon dioxide insulating layer and the drain electrode, the carbon nanotubes are parallel to the silicon substrate, and the plurality of carbon nanotubes are isolated from each other. The distance between the nearest carbon nanotube of the silicon substrate and the silicon substrate is greater than or equal to 5 nanometers, and the distance between the plurality of carbon nanotubes is greater than or equal to 5 nanometers; Wherein, the gate is located between the source and the drain; the distance between the gate and the source is greater than or equal to 50 nanometers; the distance between the gate and the drain is greater than or equal to 50 nanometers; the length, width and height of the source, the gate and the drain are equal. 2. The field effect transistor according to claim 1, wherein the silicon substrate has a length of 500 nanometers, a width of 300 nanometers and a thickness of 100 nanometers. 3 . The field effect transistor according to claim 1 , wherein the source has a height of 500 nanometers, a length of 300 nanometers and a width of 100 nanometers. 4. The field effect transistor according to claim 1, wherein the gate has a height of 500 nanometers, a length of 300 nanometers and a width of 100 nanometers. 5 . The field effect transistor according to claim 1 , wherein the drain has a height of 500 nanometers, a length of 300 nanometers and a width of 100 nanometers. 6. The field effect tube according to claim 1, characterized in that, the number of the carbon nanotubes is 3, 4 or 5. 7. The field effect tube according to claim 1, characterized in that the distances between the plurality of carbon nanotubes are equal. 8. The field effect tube according to claim 1, characterized in that, electron beam induced deposition is used between the plurality of carbon nanotubes and the source electrode, the silicon dioxide insulating layer, and the drain electrode. The contact part is deposited and dotted. 9. The field effect tube according to claim 8, characterized in that, in "using an electron beam induced deposition method, the carbon nanotubes and the source electrode, the silicon dioxide insulating layer and the drain The number of explosion points of the electron beam induced deposition method in the contact part of the electrode is 1 or 2 or 3 or 4.