CN207489447U - A kind of shift register cell, gate driving circuit, display device - Google Patents

Abstract

The embodiment of the present application provides a shift register unit, a gate drive circuit, and a display device, which relate to the field of display technology, and solve the problem that multiple different signal terminals of an OLED pixel circuit correspond to a gate drive circuit, resulting in wiring in the non-display area. Small space problem. The shift register unit includes at least two subcircuits of a first output subcircuit, a second output subcircuit, and a third output subcircuit. The first output subcircuit is used to output the voltage of the signal output terminal to the reset signal output terminal; the second output subcircuit is used to output the voltage of the signal output terminal to the gate signal output terminal; the third output subcircuit is used to output the voltage of the second output terminal to the gate signal output terminal; The voltage of the voltage terminal is output to the output terminal of the light emission control signal; or, the voltage of the first voltage terminal is output to the output terminal of the light emission control signal. The shift register unit is used to provide any two signals of reset signal, gate signal and light emission control signal to the OLED pixel circuit.

Description

A shift register unit, a gate drive circuit, and a display device

technical field

The utility model relates to the field of display technology, in particular to a shift register unit, a gate drive circuit and a display device.

Background technique

With the rapid progress of display technology, semiconductor element technology, which is the core of the display device, has also been greatly improved. For existing display devices, Organic Light Emitting Diode (OLED) is a current-type light-emitting device, because of its characteristics of self-luminescence, fast response, wide viewing angle and the ability to be fabricated on flexible substrates. And it is increasingly being used in the field of high-performance display.

A pixel circuit is arranged in a sub-pixel of an OLED display device, and the pixel circuit has a plurality of different signal terminals. In the prior art, for each signal terminal of the pixel circuit, a driving circuit connected to the signal terminal needs to be provided in the non-display area, and the driving circuit is used to provide a corresponding voltage to the signal terminal connected to it. However, in this way, the wiring space occupied by multiple different driving circuits is relatively large, which is not conducive to the design of narrow borders.

Utility model content

The embodiment of the utility model provides a shift register unit, a gate drive circuit, and a display device, which solves the problem that a plurality of different signal terminals of the OLED pixel circuit correspond to one drive circuit, resulting in a smaller wiring space in the non-display area .

In order to achieve the purpose in some embodiments, the embodiments of the present utility model adopt the following technical solutions:

In an aspect of the embodiment of the present application, a shift register unit is provided, including: at least two subcircuits in the first output subcircuit, the second output subcircuit, and the third output subcircuit; the shift register unit further includes Front-end circuit; the front-end circuit is connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first voltage terminal, the second voltage terminal and the signal output terminal, and the front-end circuit is used to receive the The voltage of the signal input terminal, and under the control of the first clock signal terminal and the second clock signal terminal, output the voltage of the second clock signal terminal or the voltage of the second voltage terminal to the signal output terminal; The first output subcircuit is configured to output the voltage of the signal output terminal to the reset signal output terminal and output the voltage of the second voltage terminal to the selected clock signal terminal under the control of the third clock signal terminal. pass signal output end; the second output subcircuit is connected to the fourth clock signal end, the second voltage end, the signal output end, the reset signal output end and the strobe signal output end; the first The second output sub-circuit is used to output the voltage of the signal output terminal to the gate signal output terminal and output the voltage of the second voltage terminal to the reset signal output under the control of the fourth clock signal terminal. terminal; the third output subcircuit is connected to the first voltage terminal, the signal output terminal, the second voltage terminal and the light-emitting control signal output terminal; the third output subcircuit is used for outputting the signal Under the control of the terminal, output the voltage of the second voltage terminal to the output terminal of the light emission control signal; or, the third output sub-circuit is used to output the voltage of the first voltage terminal under the control of the first voltage terminal The voltage is output to the light emitting control signal output terminal.

Optionally, the first output sub-circuit includes a first transistor and a second transistor; the gate of the first transistor is connected to the third clock signal terminal, the first pole is connected to the signal output terminal, and the second pole connected to the reset signal output terminal; the gate of the second transistor is connected to the third clock signal terminal, the first pole is connected to the strobe signal output terminal, and the second pole is connected to the second voltage terminal connect.

Optionally, the second output sub-circuit includes a third transistor and a fourth transistor; the gate of the third transistor is connected to the fourth clock signal terminal, the first pole is connected to the signal output terminal, and the second pole connected to the output terminal of the strobe signal; the gate of the fourth transistor is connected to the fourth clock signal terminal, the first pole is connected to the output terminal of the reset signal, and the second pole is connected to the second voltage terminal connect.

Optionally, the third output sub-circuit includes a thirteenth transistor and a fourteenth transistor; the gate and first pole of the thirteenth transistor are connected to the first voltage terminal, and the second pole is connected to the light emitting The control signal output terminal is connected; the gate of the fourteenth transistor is connected to the signal output terminal, the first pole is connected to the light emission control signal output terminal, and the second pole is connected to the second voltage terminal; wherein, A width-to-length ratio of the fourteenth transistor is greater than that of the thirteenth transistor.

Optionally, the front-end circuit includes a pull-up control subcircuit, a pull-down control subcircuit, a pull-up subcircuit, and a pull-down subcircuit; the pull-up control subcircuit is connected to a signal input terminal, a first clock signal terminal, and a pull-up node connected; the pull-up control subcircuit is used to output the voltage of the signal input terminal to the pull-up node under the control of the first clock signal terminal; the pull-up subcircuit is connected to the second clock signal terminal, The pull-up node is connected to the signal output end; the pull-up sub-circuit is used to output the voltage of the second clock signal end to the signal output end under the control of the pull-up node; the pull-down control The subcircuit is connected to the first clock signal terminal, the first voltage terminal, the pull-up node and the pull-down node; the pull-down control subcircuit is used to control the first clock signal terminal and the pull-up node Next, the voltages of the first voltage terminal and the first clock signal terminal are transmitted to the pull-down node; the pull-down sub-circuit is connected with the pull-down node, the second voltage terminal and the signal output terminal; the The pull-down sub-circuit is used to transmit the voltage of the second voltage terminal to the signal output terminal under the control of the pull-down node. Optionally, the pull-up control subcircuit includes a fifth transistor; the gate of the fifth transistor is connected to the first clock signal terminal, the first pole is connected to the signal input terminal, and the second pole is connected to the upper Pull nodes to connect.

Optionally, the pull-up control subcircuit is also connected to the first voltage terminal; the pull-up control subcircuit further includes a sixth transistor; the gate of the sixth transistor is connected to the first voltage terminal, and the first pole connected to the second pole of the fifth transistor, and the second pole is connected to the pull-up node.

Optionally, the shift register unit further includes a voltage holding subcircuit; the voltage holding subcircuit is connected to the pull-down node, the second pole of the fifth transistor, the second clock signal terminal, and the first Two voltage terminals; the voltage holding subcircuit is used to store the voltage output by the second voltage terminal under the control of the second clock signal terminal and the pull-down node, and output the stored voltage to the The second pole of the fifth transistor.

Optionally, the voltage holding sub-circuit includes a seventh transistor and an eighth transistor; the gate of the seventh transistor is connected to the second clock signal terminal, and the first pole is connected to the second pole of the fifth transistor, The second pole is connected to the first pole of the eighth transistor; the gate of the eighth transistor is connected to the pull-down node, and the second pole is connected to the second voltage terminal.

Optionally, the pull-down control subcircuit includes a ninth transistor and a tenth transistor; the gate of the ninth transistor is connected to the first clock signal terminal, the first pole is connected to the first voltage terminal, and the second pole connected to the pull-down node; the gate of the tenth transistor is connected to the pull-up node, the first pole is connected to the first clock signal terminal, and the second pole is connected to the pull-down node.

Optionally, the pull-up sub-circuit includes an eleventh transistor and a first capacitor; the gate of the eleventh transistor is connected to the pull-up node, the first pole is connected to the second clock signal terminal, and the first The pole is connected to the signal output end; one end of the first capacitor is connected to the gate of the eleventh transistor, and the other end is connected to the second pole of the eleventh transistor.

Optionally, the pull-down sub-circuit includes a twelfth transistor and a second capacitor; the gate of the twelfth transistor is connected to the pull-down node, the first pole is connected to the signal output terminal, and the second pole is connected to the The second voltage end is connected; one end of the second capacitor is connected to the gate of the twelfth transistor, and the other end is connected to the first pole of the twelfth transistor.

Another aspect of the embodiment of the present application provides a gate drive circuit, including a plurality of cascaded shift register units as described above; the signal input end of the first stage shift register unit is connected to the start signal terminal; except for the first-stage shift register unit, the signal output terminal of the upper-stage shift register unit is connected to the signal input terminal of the next-stage shift register unit.

Still another aspect of the embodiments of the present application provides a display device, including the above-mentioned gate driving circuit.

Embodiments of the present application provide a shift register unit, a gate driving circuit, and a display device. The shift register unit provided by the present application includes at least two subcircuits in the first output subcircuit, the second output subcircuit and the third output subcircuit, wherein the reset signal output terminal connected to the first output subcircuit can be connected to the OLED pixel The reset signal terminal in the circuit is connected to provide a signal to the reset signal terminal; the signal output terminal connected to the second output sub-circuit can be connected to the gate signal terminal in the OLED pixel circuit to supply the gate signal terminal Provide a signal; the light emission control signal output terminal connected to the third output sub-circuit can be connected with the light emission control signal terminal in the OLED pixel circuit, so as to provide a signal to the light emission control signal terminal. In this way, in some embodiments, the gate drive circuit formed by the shift register unit can provide at least two signal terminals (reset signal terminal, strobe signal terminal and light emission control signal terminal at least) of a pixel circuit Two) provide signals, thereby reducing the number of gate drive circuits provided in the non-display area, thereby achieving the purpose of increasing wiring space and realizing narrow borders.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are only some embodiments of the utility model, and those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a shift register unit provided in an embodiment of the present application;

FIG. 2 is a schematic structural diagram of another shift register unit provided by an embodiment of the present application;

Fig. 3a is a schematic structural diagram of an OLED pixel circuit connected to the shift register unit shown in Fig. 1 or Fig. 2 provided by the embodiment of the present application;

Fig. 3b is a timing diagram of some signal terminals in Fig. 3a;

Fig. 4 is the specific structure diagram of each sub-circuit in Fig. 1;

Fig. 5 is the specific structure diagram of each sub-circuit in Fig. 2;

Fig. 6 is a timing diagram for controlling each signal of the shift register unit shown in Fig. 5;

Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, and Fig. 12 are the shift register units shown in Fig. 5 in the first stage T1, the second stage T2, the third stage T3, the Schematic diagram of the work of the fourth stage T4, the fifth stage P5, and the sixth stage P6;

FIG. 13 is a schematic structural diagram of a gate driving circuit provided by the present application.

Reference signs:

01-front-end circuit; 10-pull-up control sub-circuit; 11-voltage holding sub-circuit; 20-pull-down control sub-circuit; 30-pull-up sub-circuit; 40-pull-down sub-circuit; 50-first output sub-circuit; 60- Second output subcircuit; 70 - third output subcircuit.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. example. Based on the embodiments of the present utility model, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of the present utility model.

Hereinafter, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

An embodiment of the present application provides a shift register unit, as shown in FIG. 1 , including at least two subcircuits of a first output subcircuit 50 , a second output subcircuit 60 and a third output subcircuit 70 .

Specifically, for example, as shown in FIG. 1 , in some embodiments, the shift register unit includes a first output subcircuit 50 and a second output subcircuit 60; for another example, as shown in FIG. 2 , the shift register unit includes The first output sub-circuit 50 , the second output sub-circuit 60 and the third output sub-circuit 70 . Alternatively, the shift register unit includes a first output subcircuit 50 and a third output subcircuit 70 ; or, the shift register unit includes a second output subcircuit 60 and a third output subcircuit 70 .

In addition, the shift register unit also includes a front-end circuit 01, the front-end circuit 01 is connected to the signal input terminal GSTV, the first clock signal terminal GCK, the second clock signal terminal GCB, the first voltage terminal VGL, the second voltage terminal VGH and the signal Output terminal Gout connection. The above-mentioned front-end circuit is used to receive the voltage of the signal input terminal GSTV, and under the control of the first clock signal terminal GCK and the second clock signal terminal GCB, output the voltage of the second clock signal terminal GCB or the voltage of the second voltage terminal VGH To the signal output terminal Gout.

Wherein, the front-end circuit 01 includes a pull-up control sub-circuit 10 , a pull-down control sub-circuit 20 , a pull-up sub-circuit 30 , and a pull-down sub-circuit 40 as shown in FIG. 1 .

Based on this, the pull-up control sub-circuit 10 is connected to the signal input terminal GSTV, the first clock signal terminal GCK, and the pull-up node PU. The pull-up control sub-circuit 10 is used to output the voltage of the signal input terminal GSTV to the pull-up node PU under the control of the first clock signal terminal GCK.

The pull-up sub-circuit 30 is connected to the second clock signal terminal GCB, the pull-up node PU and the signal output terminal Gout. The pull-up sub-circuit 30 is used to output the voltage of the second clock signal terminal GCB to the signal output terminal Gout under the control of the pull-up node PU.

The pull-down control sub-circuit 20 is connected to the first clock signal terminal GCK, the first voltage terminal VGL, the pull-up node PU and the pull-down node PD. The pull-down control sub-circuit 20 is used to transmit the voltage of the first voltage terminal VGL and the first clock signal terminal GCK to the pull-down node PD under the control of the first clock signal terminal GCK and the pull-up node PU.

The pull-down sub-circuit 40 is connected to the pull-down node PD, the second voltage terminal VGH and the signal output terminal Gout. The pull-down sub-circuit 40 is used to transmit the voltage of the second voltage terminal VGH to the signal output terminal Gout under the control of the pull-down node PD.

The first output sub-circuit 50 is connected to the third clock signal terminal GCK1, the second voltage terminal VGH, the signal output terminal Gout, and the reset signal output terminal OUT_RST. The first output sub-circuit 50 is used to output the voltage of the signal output terminal Gout to the reset signal output terminal OUT_RST under the control of the third clock signal terminal GCK1. In some embodiments, when the shift register unit includes a second output subcircuit 60, the first output subcircuit 50 is also connected to the gate signal output terminal OUT_Gate, and the first output subcircuit 50 is also used to connect the second The voltage of the voltage terminal VGH is output to the gate signal output terminal OUT_Gate.

The second output sub-circuit 60 is connected to the fourth clock signal terminal GCB1 , the second voltage terminal VGH, the signal output terminal Gout and the gate signal output terminal OUT_Gate. The second output sub-circuit 60 is used to output the voltage of the signal output terminal Gout to the gate signal output terminal OUT_Gate under the control of the fourth clock signal terminal GCB1. In some embodiments, when the shift register unit includes the first output subcircuit 50, the second output subcircuit 60 is also connected to the reset signal output terminal OUT_RST, and the second output subcircuit 60 is also used to apply the second voltage The voltage of the terminal VGH is output to the reset signal output terminal OUT_RST.

In some embodiments, when the shift register unit includes a third output module 70, the third output sub-circuit 70 is connected to the first voltage terminal VGL, the signal output terminal Gout, the second voltage terminal VGH and the light emission control signal Output terminal OUT_EMS. The third output subcircuit 70 is used to output the voltage of the second voltage terminal VGH to the light emission control signal output terminal OUT_EMS under the control of the signal output terminal Gout; Under the control of the terminal VGL, the voltage of the first voltage terminal VGL is output to the light emission control signal output terminal OUT_EMS.

Fig. 3a schematically shows a pixel driving circuit for driving OLED to emit light. The pixel circuit has a 7T1C architecture and includes a reset signal terminal RST, a gate signal terminal Gate and a light emission control signal terminal EMS.

In the prior art, for a display panel including, in some embodiments, pixel driving circuits, the non-display area needs to be provided with three different driving circuits to respectively provide signals to, in some embodiments, three signal terminals. In this embodiment, the transistors of the pixel circuit are all described by taking P-type transistors as an example, wherein the timing diagram of the reset signal terminal RST, the gate signal terminal Gate and the light emission control signal terminal EMS is shown in FIG. 3b. Specifically, in the reset phase, the reset signal terminal RST provides a low level to reset the gate g of the drive transistor Md and the anode of the OLED; in the data writing phase, the gate signal terminal Gate provides a low level to reset The data voltage Vdata is written into the drain d of the driving transistor Md through the source s of the driving transistor Md; in the light-emitting phase, the light-emitting control signal terminal EMS provides a low level to control the OLED to emit light.

In some embodiments, the shift register unit provided by the present application includes at least two subcircuits of the first output subcircuit 50, the second output subcircuit 60, and the third output subcircuit 70, wherein the first output subcircuit 50 The connected reset signal output terminal OUT_RST can be connected with the reset signal terminal RST in some embodiments, so as to provide a signal to the reset signal terminal RST; In an embodiment, the gate signal terminal Gate is connected to provide a signal to the gate signal terminal Gate; the light emission control signal output terminal OUT_EMS connected to the third output sub-circuit 70 can be connected with the light emission control signal terminal EMS in some embodiments. connected to provide signals to the light emission control signal terminal EMS.

In some embodiments, the first output subcircuit 50, the second output subcircuit 60, and the third output subcircuit 70 are all connected to the signal output terminal Gout. In some embodiments, the first output subcircuit 50 can select a signal A part of the signal output from the output terminal Gout is used as a reset signal, and is output from the reset signal output terminal OUT_RST to the reset signal terminal RST of the OLED pixel circuit; the second output sub-circuit 60 can select another part of the signal output from the signal output terminal Gout as a gate signal , and output from the strobe signal output terminal OUT_Gate to the strobe signal terminal Gate of the OLED pixel circuit; the third output sub-circuit 70 can determine the timing of the light-emitting control signal under the control of the output signal of the signal output terminal Gout, and the light-emitting control signal The output terminal OUT_EMS is output to the light emitting control signal terminal EMS of the OLED pixel circuit. In this way, in some embodiments, the gate drive circuit formed by the shift register unit can provide at least two signal terminals (reset signal terminal RST, strobe signal terminal Gate, and light emission control signal terminal EMS) of a pixel circuit. At least two of them) provide signals, thereby reducing the number of gate drive circuits provided in the non-display area, thereby achieving the purpose of increasing wiring space and realizing narrow borders.

Specifically, as shown in FIG. 4 , in some embodiments, the first output sub-circuit 50 includes a first transistor M1 and a second transistor M2 .

Wherein, the gate of the first transistor M1 is connected to the third clock signal terminal GCK1, the first pole is connected to the signal output terminal Gout, and the second pole is connected to the reset signal output terminal OUT_RST.

The gate of the second transistor M2 is connected to the third clock signal terminal GCK1, the first pole is connected to the gate signal output terminal OUT_Gate, and the second pole is connected to the second voltage terminal VGH.

In some embodiments, the second output sub-circuit 60 includes a third transistor M3 and a fourth transistor M4.

Wherein, the gate of the third transistor M3 is connected to the fourth clock signal terminal GCB1, the first pole is connected to the signal output terminal Gout, and the second pole is connected to the gate signal output terminal OUT_Gate.

The gate of the fourth transistor M4 is connected to the fourth clock signal terminal GCB1, the first pole is connected to the reset signal output terminal OUT_RST, and the second pole is connected to the second voltage terminal VGH.

In some embodiments, if the shift register unit includes a third output sub-circuit 70 , the third output sub-circuit 70 includes a thirteenth transistor M13 and a fourteenth transistor M14 as shown in FIG. 5 .

Wherein, the gate and the first pole of the thirteenth transistor M13 are connected to the first voltage terminal VGL, and the second pole is connected to the light emission control signal output terminal OUT_EMS.

The gate of the fourteenth transistor M14 is connected to the signal output terminal Gout, the first pole is connected to the light emission control signal output terminal OUT_EMS, and the second pole is connected to the second voltage terminal VGH.

Wherein, the aspect ratio of the fourteenth transistor M14 is greater than that of the thirteenth transistor M13. In this case, the driving capability of the fourteenth transistor M14 is greater than that of the thirteenth transistor M13. In this case, when both the thirteenth transistor M13 and the fourteenth transistor M14 are turned on, the potential of the light emission control signal output terminal OUT_EMS depends on the voltage potential of the second voltage terminal VGH transmitted through the fourteenth transistor M14.

On this basis, the pull-up control sub-circuit 10 includes a fifth transistor M5. Wherein, the gate of the fifth transistor M5 is connected to the first clock signal terminal GCK, the first pole is connected to the signal input terminal GSTV, and the second pole is connected to the pull-up node PU.

Based on this, in some embodiments, the shift register unit may further include a voltage holding sub-circuit 11 as shown in FIG. 5 . The voltage holding sub-circuit 11 is connected to the pull-down node PD, the second pole of the fifth transistor M5, the second clock signal terminal GCB and the second voltage terminal VGH. Wherein, the voltage holding sub-circuit 11 is used to store the voltage output from the second voltage terminal VGH under the control of the second clock signal terminal GCB and the pull-down node PD, and output the stored voltage to the fifth transistor M5. Diode. Therefore, in some embodiments, when the fifth transistor M5 is connected to the pull-up node PU in some embodiments, the voltage of the second voltage terminal VGH can be output to the pull-up node PU through the voltage holding sub-circuit 11 , to stably pull up the potential of the node PU.

Specifically, in some embodiments, the voltage holding sub-circuit 11 includes a seventh transistor M7 and an eighth transistor M8.

Wherein, the gate of the seventh transistor M7 is connected to the second clock signal terminal GCB, the first pole is connected to the second pole of the fifth transistor M5, and the second pole is connected to the first pole of the eighth transistor M8.

The gate of the eighth transistor M8 is connected to the pull-down node PD, and the second electrode is connected to the second voltage terminal VGH.

In some embodiments, the pull-up control sub-circuit 10 is also connected to the first voltage terminal VGL, and at this time, the pull-up control sub-circuit 10 also includes a sixth transistor M6.

Wherein, the gate of the sixth transistor M6 is connected to the first voltage terminal VGL, the first pole is connected to the second pole of the fifth transistor M5, and the second pole is connected to the pull-up node PU. In this case, when the sixth transistor M6 is turned on, the second pole of the fifth transistor M5 may be connected to the pull-up node PU in some embodiments through the sixth transistor M6. In this way, in some embodiments, when the sixth transistor M6 is a P-type transistor, when the voltage at the second pole of the sixth transistor M6 is greater than the gate voltage, the sixth transistor M6 can be in an off state, thereby It can prevent the leakage of the pull-up node PU.

In some embodiments, the pull-down control sub-circuit 20 includes a ninth transistor M9 and a tenth transistor M10.

Wherein, the gate of the ninth transistor M9 is connected to the first clock signal terminal GCK, the first pole is connected to the first voltage terminal VGL, and the second pole is connected to the pull-down node PD.

The gate of the tenth transistor M10 is connected to the pull-up node PU, the first pole is connected to the first clock signal terminal GCK, and the second pole is connected to the pull-down node PD.

In some embodiments, the pull-up sub-circuit 30 includes an eleventh transistor M11 and a first capacitor C1.

Wherein, the gate of the eleventh transistor M11 is connected to the pull-up node PU, the first pole is connected to the second clock signal terminal GCB, and the first pole is connected to the signal output terminal Gout.

One end of the first capacitor C1 is connected to the gate of the eleventh transistor M11, and the other end is connected to the second electrode of the eleventh transistor M11.

The pull-down sub-circuit 40 includes a twelfth transistor M12 and a second capacitor C2.

Wherein, the gate of the twelfth transistor M12 is connected to the pull-down node PD, the first pole is connected to the signal output terminal Gout, and the second pole is connected to the second voltage terminal VGH.

One end of the second capacitor C2 is connected to the gate of the twelfth transistor M12, and the other end is connected to the first electrode of the twelfth transistor M12.

It should be noted that, in some embodiments, the transistor may be an N-type transistor or a P-type transistor. Wherein, the first pole of the transistor may be a source, and the second pole may be a drain, or the first pole may be a drain, and the second pole may be a source, which is not limited in this application.

This application is described by taking the first voltage terminal VGL outputting a constant low level and the second voltage terminal VGH outputting a constant high level as an example.

Hereinafter, taking the above-mentioned transistors in the shift register unit and the transistors connected to the reset signal terminal RST, the strobe signal terminal Gate, and the light emission control signal terminal EMS in the OLED pixel circuit as examples, all of which are P-type transistors, combined with FIG. 6 The signal timing diagram shown in FIG. 5 is used to describe in detail the working conditions of the shift register unit shown in FIG. 5 at various stages within an image frame.

Wherein, as shown in Figure 6, the frequency of the output signal of the first clock signal terminal GCK and the second clock signal terminal GCB are the same, and the phases are opposite; the frequency of the output signal of the third clock signal terminal GCK1 and the fourth clock signal terminal GCB1 are the same, and the phase On the contrary; the frequency of the output signal of the first clock signal terminal GCK is 1/2 of the frequency of the output signal of the third clock signal terminal GCK1.

In some embodiments, within an image frame, the durations of the first stage T1 , the second stage T2 , the third stage T3 and the fourth stage T4 are the same. The duration of the fifth stage P5 and the sixth stage P6 is twice the duration of the fourth stage T4.

Specifically, in the first stage T1, GSTV=0; GCK=0; GCB=1; GCK1=0; GCB1=1. Among them, "0" means high level, and "1" means low level.

In this case, as shown in FIG. 7 , the first clock signal terminal GCK outputs a low level, and the fifth transistor M5 and the ninth transistor M9 are turned on. The low level output by the signal input terminal GSTV is transmitted to the node PU0 through the fifth transistor M5, and then transmitted to the pull-up node PU through the turned-on sixth transistor M6. Under the control of the node PU0, the tenth transistor M10 is turned on. The low level output from the first voltage terminal VGL is transmitted to the pull-down node PD through the ninth transistor M9, and the low level output from the first clock signal terminal GCK is transmitted to the pull-down node PD through the tenth transistor M10.

In some embodiments, the eighth transistor M8 is turned on, the seventh transistor M7 is turned off, and the high level output from the second voltage terminal VGH can be stored in the gate and source of the seventh transistor M7 after passing through the eighth transistor M8. The parasitic capacitance GS constituted by (or drain), and the parasitic capacitance GD constituted by the gate and drain (or source) of the eighth transistor M8, that is, the high level is stored at the node N1.

Under the control of the pull-up node PU, the eleventh transistor M11 is turned on, and transmits the high level output from the second clock signal terminal GCB to the signal output terminal Gout. Under the control of the pull-down node PD, the twelfth transistor M12 is turned on, and transmits the high level output from the second voltage terminal VGH to the signal output terminal Gout.

Under the control of the third clock signal terminal GCK1, the first transistor M1 and the second transistor M2 are turned on. The high level of the signal output terminal Gout is transmitted to the reset signal output terminal OUT_RST through the first transistor M1. The high level of the second voltage terminal VGH is transmitted to the gate signal output terminal OUT_Gate through the second transistor M2.

The third transistor M3, the fourth transistor M4 and the fourteenth transistor M14 are in an off state. The thirteenth transistor M13 is turned on, and transmits the low level of the first voltage terminal VGL to the light emission control signal output terminal OUT_EMS through the thirteenth transistor M13 .

At this stage, the reset signal output terminal OUT_RST outputs a high level, so the reset signal terminal RST of the OLED pixel circuit connected to the shift register unit receives a high level in some embodiments, so the OLED pixel circuit The transistor connected to the reset signal terminal RST is turned off, so the OLED pixel circuit does not enter the reset phase.

In the second phase T2, GSTV=0; GCK=0; GCB=1; GCK1=1; GCB1=0.

In this case, as shown in FIG. 8 , the signals output from the signal input terminal GSTV, the first clock signal terminal GCK and the second clock signal terminal GCB are the same as those of the first stage T1. The difference is that the third clock signal terminal GCK1 outputs a high level, and the fourth clock signal terminal GCB1 outputs a low level, so at this stage, the first transistor M1 and the second transistor M2 are turned off. The third transistor M3 and the fourth transistor M4 are turned on. The turn-on and turn-off states of the remaining transistors are the same as the first stage T1.

Based on this, through the third transistor M3 in some embodiments, the high level of the signal output terminal Gout can be transmitted to the gate signal output terminal OUT_Gate; through the fourth transistor M4 in some embodiments, the second voltage terminal VGH The high level of the signal can be transmitted to the reset signal output terminal OUT_RST; while the light emission control signal output terminal OUT_EMS maintains a low level output.

As mentioned above, at this stage, the OLED pixel circuit connected to the shift register unit has not yet entered the reset stage.

In the third phase T3, GSTV=1; GCK=1; GCB=0; GCK1=0; GCB1=1.

In this case, as shown in FIG. 9 , the first clock signal terminal GCK outputs a high level, and the fifth transistor M5 and the ninth transistor M9 are turned off. Under the bootstrap action of the first capacitor C1, the level of the pull-up node PU is further lowered. At this time, the eleventh transistor M11 is kept in a conducting state, and outputs the low level of the second clock signal terminal GCB to the signal output terminal Gout.

Under the control of the pull-up node PU, the tenth transistor M10 is turned on, and transmits the high level output from the first clock signal terminal GCK to the pull-down node PD. At this time, the eighth transistor M8 and the twelfth transistor M12 are turned off.

In some embodiments, since the sixth transistor M6 is a P-type transistor, the level of the first terminal of the sixth transistor M6 (that is, the end connected to the pull-up node PU) is further lowered at this stage, so the sixth transistor M6 The source (or drain) voltage of M6 is greater than the gate voltage, and the sixth transistor M6 is in an off state.

It should be noted that, at this stage, the node PU0 is at a low level. This is because, in the second stage T2, the low level output from the signal input terminal GSTV will be stored in the parasitic capacitance formed by the gate of the tenth transistor M10 and the active layer. The parasitic capacitance of the tenth transistor M10 is larger than the parasitic capacitance GS of the seventh transistor M7 at the node N1 and the parasitic capacitance GD of the eighth transistor M8, so in the second stage, the parasitic capacitance of the tenth transistor M10 keeps the node PU0 at The ability of the low level is greater than the ability of the parasitic capacitance at the node N1 to write the high level to the node PU0.

On this basis, the third clock signal terminal GCK1 outputs a low level, and the first transistor M1 and the second transistor M2 are turned on. The fourth clock signal terminal GCB1 outputs a high level, and the third transistor M3 and the fourth transistor M4 are turned off. The level of the signal output terminal Gout can be transmitted to the reset signal output terminal OUT_RST through the first transistor M1, and the high level of the second voltage terminal VGH can be transmitted to the gate signal output terminal OUT_Gate through the second transistor M2.

In some embodiments, the fourteenth transistor M14 is turned on. Since the driving capability of the fourteenth transistor M14 is greater than that of the thirteenth transistor M13, the high level of the second voltage terminal VGH can be transmitted to the Light emission control signal output terminal OUT_EMS.

It can be seen that the reset signal output terminal OUT_RST outputs low level, the gate signal output terminal OUT_Gate and the light emission control signal output terminal OUT_EMS output high level. In this case, the reset signal terminal RST of the OLED pixel circuit connected to the shift register unit receives a low level, so that the corresponding position in the OLED pixel circuit (for example, the gate of the drive transistor, the anode of the OLED, etc.) position) to reset the voltage, and the OLED pixel circuit is in the reset phase.

In the fourth phase T4, GSTV=1; GCK=1; GCB=0; GCK1=1; GCB=0.

In this case, as shown in FIG. 10 , the signals output from the signal input terminal GSTV, the first clock signal terminal GCK and the second clock signal terminal GCB are the same as those output in the third stage T3. The difference is that the third clock signal terminal GCK1 outputs a high level, and the fourth clock signal terminal GCB1 outputs a low level, so at this stage, the first transistor M1 and the second transistor M2 are turned off. The third transistor M3 and the fourth transistor M4 are turned on. The on and off states of the remaining transistors are the same as those in the third stage T3.

Based on this, in some embodiments, the third transistor M3, the low level of the signal output terminal Gout can be transmitted to the gate signal output terminal OUT_Gate; in some embodiments, the fourth transistor M4, the second voltage terminal VGH The high level can be transmitted to the reset signal output terminal OUT_RST; while the light emission control signal output terminal OUT_EMS maintains a high level output.

In some embodiments, the gate signal output terminal OUT_Gate outputs a low level, and the reset signal output terminal OUT_RST and the light emitting control signal output terminal OUT_EMS output a high level. In this case, the gate signal terminal Gate of the OLED pixel circuit connected to the shift register unit receives, in some embodiments, a low level, so that the data voltage Data is written into the drive transistor, and the OLED pixel circuit is in Data writing stage.

In the fifth phase P5, GSTV=1; GCK=0; GCB=1; GCK1=0,1; GCB1=1,0.

In this case, as shown in Figure 11, under the control of the low level output from the first clock signal terminal GCK, the fifth transistor M5 and the ninth transistor M9 are turned on, and the high level output from the signal input terminal GSTV is transmitted to the upper Pulling the node PU, the eleventh transistor M11 and the tenth transistor M10 are turned off.

The low level of the first voltage terminal VGL is transmitted to the pull-down node PD through the ninth transistor M9, the twelfth transistor M12 is turned on, and the eighth transistor M8 is turned on. The second voltage terminal VGH is transmitted to the signal output terminal Gout through the twelfth transistor M12, and is stored in the first node N1 through the eighth transistor M8. Under the control of the second clock signal terminal GCB, the seventh transistor M7 is turned off.

In the fifth phase P5, the third clock signal terminal GCK1 successively outputs low level and high level; the fourth clock signal terminal GCB2 successively outputs high level and low level. Based on this, when the third clock signal terminal GCK1 outputs a low level and the fourth clock signal terminal GCB1 outputs a high level, as shown in FIG. 11 , the first transistor M1 and the second transistor M2 are turned on, and the third transistor M3 and the Four transistors M4 are turned off. When the third clock signal terminal GCK1 outputs a high level and the fourth clock signal terminal GCB1 outputs a low level, the first transistor M1 and the second transistor M2 are turned off, and the third transistor M3 and the fourth transistor M4 are turned on. Regardless of the signal output from the third clock signal terminal GCK1 or the fourth clock signal terminal GCB1 , since the signal output terminal Gout is at a high level, the gate signal output terminal OUT_Gate and the reset signal output terminal OUT_RST output a high level.

In some embodiments, under the control of the signal output terminal Gout, the fourteenth transistor M14 is turned off, so the thirteenth transistor M13 transmits the low level of the first voltage terminal VGL to the light emission control signal output terminal OUT_EMS. In this case, the light emitting control signal terminal EMS of the OLED pixel circuit connected to the shift register unit receives a low level, so that the OLED emits light, and the OLED pixel circuit is in the light emitting stage.

In the sixth phase P6, GSTV=1; GCK=1; GCB=0; GCK1=0,1; GCB1=1,0.

In this case, as shown in FIG. 12 , under the control of the high level output from the first clock signal terminal GCK, the fifth transistor M5 and the ninth transistor M9 are turned off. The pull-down control node PD maintains the low level of the previous stage under the discharge of the second capacitor C2. At this time, the twelfth transistor M12 and the eighth transistor M8 are turned on. Under the control of the low level of the second clock signal terminal GCB, the seventh transistor M7 is turned on, the high level at the node N1 is transmitted to the node PU0 and the pull-up node PU, and the eleventh transistor M11 and the tenth transistor M10 are turned off.

In some embodiments, the high level of the second voltage terminal VGH is transmitted to the signal output terminal Gout through the twelfth transistor M12, and the signal output terminal Gout maintains a high level output. In this case, the light emitting control signal output terminal OUT_EMS outputs a low level.

Based on this, the signals output by the third clock signal terminal GCK1 and the fourth clock signal terminal GCB2 are the same as those in the fifth stage, so the gate signal output terminal OUT_Gate and the reset signal output terminal OUT_RST keep outputting a high level.

It should be noted that, after the sixth stage T2 and before the start of the next image frame, the shift register unit repeats the fifth stage and the sixth stage.

The above is an example where all the transistors in the shift register unit and the transistors connected to the reset signal terminal RST, the strobe signal terminal Gate and the light emission control signal terminal EMS in the OLED pixel circuit are all P-type transistors. When the transistors in the bit register unit and the transistors connected to the reset signal terminal RST, the strobe signal terminal Gate and the light emission control signal terminal EMS in the OLED pixel circuit are all N-type transistors, part of the control signals in Figure 6 need to be reversed , and the positions of the first voltage terminal VGL and the second voltage terminal VGH are exchanged, and the working process of the shift register unit can be obtained in the same way, which will not be repeated here.

An embodiment of the present application provides a gate driving circuit. As shown in FIG. 13 , the gate driving circuit includes a plurality of cascaded shift register units of any type as described above.

Wherein, the signal input terminal GSTV of the first-stage shift register unit RS1 is connected to the start signal terminal STV. When a start signal is input to the start signal terminal STV, the shift register unit starts to work.

Except for the first-stage shift register unit RS1, the signal output terminal Gout of the upper-stage shift register unit is connected to the signal input terminal GSTV of the next-stage shift register unit.

It should be noted that the first clock signal terminal GCK and the second clock signal terminal GCB of two adjacent shift register units are alternately connected to the system clock signal terminal CK1 and CK2 respectively. For example, the first clock signal terminal GCK of the first-stage shift register unit RS1 is connected to the system clock signal terminal CK1, and the second clock signal terminal GCB is connected to the system clock signal terminal CK2; the first clock signal terminal of the second-stage shift register unit RS2 GCK is connected to the system clock signal terminal CK2, and the second clock signal terminal GCB is connected to the system clock signal terminal CK1.

In some embodiments, the third clock signal terminal GCK1 and the fourth clock signal terminal GCB1 of two adjacent shift register units are alternately connected to the system clock signal terminal CK3 and CK4 respectively. For example, the third clock signal terminal GCK1 of the first-stage shift register unit RS1 is connected to the system clock signal terminal CK3, and the fourth clock signal terminal GCB1 is connected to the system clock signal terminal CK4; the third clock signal terminal of the second-stage shift register unit RS2 GCK1 is connected to the system clock signal terminal CK4, and the fourth clock signal terminal GCB1 is connected to the system clock signal terminal CK3. The connection mode of the clock signal terminals of other shift register units can be analogized by analogy.

In some embodiments, the gate driving circuit has the same technical effect as that of the shift register unit provided in the foregoing embodiments, which will not be repeated here.

An embodiment of the present application provides a display device, including any one of the above-mentioned gate driving circuits. The gate drive circuit in the display device has the same structure and beneficial effect as the gate drive circuit provided by the foregoing embodiments. Since the foregoing embodiments have described the structure and beneficial effects of the gate driving circuit in detail, details are not repeated here.

It should be noted that, in the embodiment of the present utility model, the display device can be at least an organic light emitting diode display device, for example, the display device can be any display device such as a monitor, a TV, a digital photo frame, a mobile phone, a vehicle-mounted display screen, or a tablet computer. functional product or component.

The embodiment of the present application provides a method for driving any shift register unit as described above. In an image frame, the front-end circuit 01 of the shift register unit includes a pull-up control sub-circuit 10, a pull-down control In the case of subcircuit 20, pull-up subcircuit 30, and pull-down subcircuit 40, the method includes:

In the first phase T1 and the second phase T2 as shown in FIG. 6, the pull-up control subcircuit 10 in FIG. 2 outputs the voltage of the signal input terminal GSTV to the pull-up node PU under the control of the first clock signal terminal GCK. .

The pull-up sub-circuit 30 outputs the voltage of the second clock signal terminal GCB to the signal output terminal Gout under the control of the pull-up node PU.

The pull-down control sub-circuit 20 transmits the voltages of the first voltage terminal VGL and the first clock signal terminal GCK to the pull-down node PD under the control of the first clock signal terminal GCK and the pull-up node PU.

The pull-down sub-circuit 40 transmits the voltage of the second voltage terminal VGH to the signal output terminal Gout under the control of the pull-down node PU.

In the case where the shift register unit includes a third output subcircuit 70, the third output subcircuit 70 outputs the voltage of the first voltage terminal VGL to the light emission control signal output terminal OUT_EMS under the control of the first voltage terminal VGL. .

In some embodiments, in the third stage T3 and the fourth stage T4, in some embodiments, the method includes:

The pull-up sub-circuit 30 outputs the voltage of the second clock signal terminal GCB to the signal output terminal Gout under the control of the pull-up node PU.

The pull-down control sub-circuit 20 transmits the voltage of the first clock signal terminal GCK to the pull-down node PD under the control of the pull-up node PU.

The pull-down sub-circuit 40 is in an off state under the control of the pull-down node PD.

When the shift register unit includes a third output sub-circuit 70, the third output sub-circuit 70 outputs the voltage of the second voltage terminal VGH to the light emission control signal output terminal OUT_EMS under the control of the signal output terminal Gout.

In some embodiments, when the shift register unit includes the first output sub-circuit 50 and the second output sub-circuit 60, in the first stage T1 and the third stage T3, the first output sub-circuit 50 is in the third Under the control of the clock signal terminal GCK1, the voltage of the signal output terminal Gout is output to the reset signal output terminal OUT_RST, and the voltage of the second voltage terminal VGH is output to the gate signal output terminal OUT_Gate.

In the second stage T2 and the fourth stage T4, under the control of the fourth clock signal terminal GCB1, the second output subcircuit 20 outputs the voltage of the signal output terminal Gout to the gate signal output terminal OUT_Gate, and the second voltage terminal OUT_Gate The voltage of VGH is output to the reset signal output terminal OUT_Gate.

In the fifth stage P5, the pull-down control sub-circuit 20 transmits the voltage of the first voltage terminal VGL to the pull-down node PD under the control of the first clock signal terminal GCK.

The pull-down sub-circuit 40 transmits the voltage of the second voltage terminal VGH to the signal output terminal Gout under the control of the pull-down node PD.

In the case where the pull-up control subcircuit 10 includes a voltage holding subcircuit 11, in the fifth phase P5, the voltage holding subcircuit 11, under the control of the second clock signal terminal CGB and the pull-down node PD, sets the second voltage terminal VGH to The output voltage is stored.

In the sixth phase P6, the pull-down sub-circuit 40 continuously transmits the voltage of the second voltage terminal VGH to the signal output terminal Gout.

In the case that the pull-up control subcircuit 10 includes a voltage holding subcircuit 11, in the sixth phase P6, the voltage holding subcircuit 11 outputs the storage voltage to the pull-up node under the control of the second clock signal terminal CGB and the pull-down node PD. Node PUs.

In some embodiments, in the fifth phase P5 and the sixth phase P6, in some embodiments, the first output sub-circuit 50 and the second output sub-circuit 60 alternately output the voltage of the signal output terminal Gout to the reset signal output Terminal OUT_RST and strobe signal output terminal OUT_Gate.

In the case where the shift register unit includes a third output subcircuit 70, the third output subcircuit 70 outputs the voltage of the first voltage terminal VGL to the light emission control signal output terminal OUT_EMS under the control of the first voltage terminal VGL. .

On this basis, after the sixth stage P6 and before the start of the next image frame, in some embodiments, the fifth stage P5 and the sixth stage P6 are repeated.

When each sub-circuit shown in FIG. 5 is used, at each stage of an image frame, the on-off states of each transistor in the shift register unit are as described above, and will not be repeated here. In some embodiments, the driving method has the same technical effect as that of the shift register unit provided in the foregoing embodiments, which will not be repeated here.

Those of ordinary skill in the art can understand that all or part of the steps to realize the method embodiments in this specification can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium, and the program can , executing the steps included in the method embodiments in some embodiments; and the aforementioned storage medium includes: various media capable of storing program codes such as ROM, RAM, magnetic disk or optical disk.

The above is only a specific embodiment of the present utility model, but the scope of protection of the present utility model is not limited thereto. Anyone familiar with the technical field can easily think of changes or changes within the technical scope disclosed by the utility model Replacement should be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be based on the protection scope of the claims.

Claims (14)

1. A shift register unit, characterized in that, comprising: at least two subcircuits in the first output subcircuit, the second output subcircuit and the third output subcircuit; the shift register unit also includes a front-end circuit; The front-end circuit is connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first voltage terminal, the second voltage terminal and the signal output terminal, and the front-end circuit is used to receive the voltage of the signal input terminal, And under the control of the first clock signal terminal and the second clock signal terminal, output the voltage of the second clock signal terminal or the voltage of the second voltage terminal to the signal output terminal; The first output subcircuit is connected to the third clock signal terminal, the second voltage terminal, the signal output terminal, the reset signal output terminal and the strobe signal output terminal; the first output subcircuit is used for Under the control of the third clock signal terminal, output the voltage of the signal output terminal to the reset signal output terminal, and output the voltage of the second voltage terminal to the strobe signal output terminal; The second output subcircuit is connected to the fourth clock signal terminal, the second voltage terminal, the signal output terminal, the reset signal output terminal and the gate signal output terminal; the second output subcircuit Under the control of the fourth clock signal terminal, output the voltage of the signal output terminal to the gate signal output terminal, and output the voltage of the second voltage terminal to the reset signal output terminal; The third output subcircuit is connected to the first voltage terminal, the signal output terminal, the second voltage terminal and the light emission control signal output terminal; the third output subcircuit is used to control the signal output terminal Under the control of the first voltage terminal, the voltage of the second voltage terminal is output to the output terminal of the light emission control signal; or, the third output sub-circuit is used to output the voltage of the first voltage terminal under the control of the first voltage terminal to the output terminal of the lighting control signal. 2. The shift register unit according to claim 1, wherein the first output sub-circuit comprises a first transistor and a second transistor; The gate of the first transistor is connected to the third clock signal terminal, the first pole is connected to the signal output terminal, and the second pole is connected to the reset signal output terminal; The gate of the second transistor is connected to the third clock signal terminal, the first pole is connected to the gate signal output terminal, and the second pole is connected to the second voltage terminal. 3. The shift register unit according to claim 1, wherein the second output sub-circuit comprises a third transistor and a fourth transistor; The gate of the third transistor is connected to the fourth clock signal terminal, the first pole is connected to the signal output terminal, and the second pole is connected to the gate signal output terminal; The gate of the fourth transistor is connected to the fourth clock signal terminal, the first pole is connected to the reset signal output terminal, and the second pole is connected to the second voltage terminal. 4. The shift register unit according to claim 1, wherein the third output sub-circuit comprises a thirteenth transistor and a fourteenth transistor; The gate and first pole of the thirteenth transistor are connected to the first voltage terminal, and the second pole is connected to the output terminal of the light emission control signal; The gate of the fourteenth transistor is connected to the signal output terminal, the first pole is connected to the light emission control signal output terminal, and the second pole is connected to the second voltage terminal; Wherein, the width-to-length ratio of the fourteenth transistor is greater than the width-to-length ratio of the thirteenth transistor. 5. The shift register unit according to any one of claims 1-4, wherein the front-end circuit comprises a pull-up control subcircuit, a pull-down control subcircuit, a pull-up subcircuit, and a pull-down subcircuit; The pull-up control subcircuit is connected to the signal input terminal, the first clock signal terminal, and the pull-up node; the pull-up control subcircuit is used to control the voltage of the signal input terminal under the control of the first clock signal terminal output to the pull-up node; The pull-up sub-circuit is connected to the second clock signal end, the pull-up node, and the signal output end; the pull-up sub-circuit is used to connect the second clock signal end to the The voltage is output to the signal output terminal; The pull-down control subcircuit is connected to the first clock signal terminal, the first voltage terminal, the pull-up node, and the pull-down node; the pull-down control subcircuit is used to connect the first clock signal terminal and the upper Under the control of the pull-down node, transmitting the voltages of the first voltage terminal and the first clock signal terminal to the pull-down node; The pull-down sub-circuit is connected to the pull-down node, the second voltage terminal and the signal output terminal; the pull-down sub-circuit is used to transmit the voltage of the second voltage terminal to the the signal output terminal. 6. The shift register unit according to claim 5, wherein the pull-up control subcircuit comprises a fifth transistor; the gate of the fifth transistor is connected to the first clock signal terminal, and the first pole connected to the signal input end, and the second pole is connected to the pull-up node. 7. The shift register unit according to claim 6, wherein the pull-up control subcircuit is also connected to the first voltage terminal; the pull-up control subcircuit also includes a sixth transistor; The gate of the sixth transistor is connected to the first voltage terminal, the first pole is connected to the second pole of the fifth transistor, and the second pole is connected to the pull-up node. 8. The shift register unit according to claim 6, characterized in that, the shift register unit also includes a voltage holding sub-circuit; The voltage holding sub-circuit is connected to the pull-down node, the second pole of the fifth transistor, the second clock signal terminal and the second voltage terminal; the voltage holding sub-circuit is used for Under the control of the two clock signal terminals and the pull-down node, the voltage output from the second voltage terminal is stored, and the stored voltage is output to the second electrode of the fifth transistor. 9. The shift register unit according to claim 8, wherein the voltage holding sub-circuit comprises a seventh transistor and an eighth transistor; The gate of the seventh transistor is connected to the second clock signal terminal, the first pole is connected to the second pole of the fifth transistor, and the second pole is connected to the first pole of the eighth transistor; The gate of the eighth transistor is connected to the pull-down node, and the second pole is connected to the second voltage terminal. 10. The shift register unit according to claim 5, wherein the pull-down control subcircuit comprises a ninth transistor and a tenth transistor; The gate of the ninth transistor is connected to the first clock signal terminal, the first pole is connected to the first voltage terminal, and the second pole is connected to the pull-down node; The gate of the tenth transistor is connected to the pull-up node, the first pole is connected to the first clock signal terminal, and the second pole is connected to the pull-down node. 11. The shift register unit according to claim 5, wherein the pull-up sub-circuit comprises an eleventh transistor and a first capacitor; The gate of the eleventh transistor is connected to the pull-up node, the first pole is connected to the second clock signal terminal, and the first pole is connected to the signal output terminal; One end of the first capacitor is connected to the gate of the eleventh transistor, and the other end is connected to the second pole of the eleventh transistor. 12. The shift register unit according to claim 5, wherein the pull-down subcircuit comprises a twelfth transistor and a second capacitor; The gate of the twelfth transistor is connected to the pull-down node, the first pole is connected to the signal output terminal, and the second pole is connected to the second voltage terminal; One end of the second capacitor is connected to the gate of the twelfth transistor, and the other end is connected to the first pole of the twelfth transistor. 13. A gate drive circuit, characterized in that it comprises a plurality of cascaded shift register units according to any one of claims 1-12; The signal input end of the first-stage shift register unit is connected to the start signal end; Except for the first-stage shift register unit, the signal output end of the upper-stage shift register unit is connected to the signal input end of the next-stage shift register unit. 14. A display device, comprising the gate driving circuit according to claim 13.