CN207352947U - 显示面板及其像素电路 - Google Patents
显示面板及其像素电路 Download PDFInfo
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- CN207352947U CN207352947U CN201721382534.0U CN201721382534U CN207352947U CN 207352947 U CN207352947 U CN 207352947U CN 201721382534 U CN201721382534 U CN 201721382534U CN 207352947 U CN207352947 U CN 207352947U
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Classifications
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract
本实用新型提供一种显示面板及其像素电路。像素电路包括第一晶体管、第二晶体管、电容、存储电容以及像素电容。第一晶体管的第一端耦接至源极线,其控制端耦接至栅极线。第二晶体管的第一端耦接至第一晶体管的第二端,第二晶体管的控制端耦接至栅极线。电容的第一端耦接至第一晶体管的第二端,电容的第二端接收共用电压。存储电容串接在第二晶体管的第二端以及共用电压间。像素电容串接在第二晶体管的第二端以及共用电压间。其中,电容用以维持像素电容上的电压电平,并维持显示质量。可防止像素电容的电荷产生漏电的现象,且可降低穿通电压(feed through voltage)对像素电压所造成的影响,维持显示的质量。
Description
技术领域
本实用新型涉及一种像素电路,尤其涉及一种显示面板及其像素电路。
背景技术
随着电子科技的进步,电子装置成为人们生活中的不可或缺的工具。而提供高质量显示接口,为现今电子装置的重要功能。
在现有的像素电路的架构下,在电压保持时间区间,像素电容中所存储的像素电压可能产生漏电现象,而使像素所呈现的显示强度产生失真。并且,习知的像素电路,在像素电容充电过程中,也可能因薄膜晶体管的关闭动作,而产生使像素电容上的电压产生瞬间下降的现象(即所谓的穿通电压(feed through voltage))现象,进而造成显示质量的下降。
实用新型内容
本实用新型提供一种显示面板及其像素电路。像素电路包括第一晶体管、第二晶体管、电容、存储电容以及像素电容。第一晶体管的第一端耦接至源极线,其控制端耦接至栅极线。第二晶体管的第一端耦接至第一晶体管的第二端,第二晶体管的控制端耦接至栅极线。电容的第一端耦接至第一晶体管的第二端,电容的第二端接收共用电压。存储电容串接在第二晶体管的第二端以及共用电压间。像素电容串接在第二晶体管的第二端以及共用电压间。
在本实用新型的一实施例中,上述的电容的电容值大于存储电容以及像素电容的电容值。
在本实用新型的一实施例中,上述的电容的电容值不大于存储电容以及像素电容的电容值。
在本实用新型的一实施例中,上述的第一晶体管与第二晶体管的形态相同。
在本实用新型的一实施例中,上述的第一晶体管与第二晶体管皆为N型薄膜晶体管。
在本实用新型的一实施例中,上述的电容的第一电极板与所述第一晶体管的第二端、所述第二晶体管的第一端共享同一金属层。
在本实用新型的一实施例中,上述的电容为金属-绝缘层-金属电容。
在本实用新型的一实施例中,上述的电容用以在所述像素电路的电压保持时间区间中维持第一晶体管的第二端与第二晶体管第一端上的电压。
在本实用新型的一实施例中,上述的共用电压为直流电压。
在本实用新型的一实施例中,上述的显示面板为电泳式显示面板或液晶显示面板。
本实用新型另提供一种显示面板,包括多条栅极线、多条源极线以及如前所述的多个像素电路。
本实用新型的一实施例中,上述的电容的电容值大于存储电容以及所述像素电容的电容值。
本实用新型的一实施例中,上述的电容的电容值不大于存储电容以及所述像素电容的电容值。
本实用新型的一实施例中,上述的电容的第一电极板与第一晶体管的第二端、所述第二晶体管的第一端共享同一金属层。
本实用新型的一实施例中,上述的电容用以在像素电路的电压保持时间区间中维持所述第一晶体管的第二端与所述第二晶体管第一端上的电压。
基于上述,由于本实用新型的像素电路中,通过在第一晶体管、第二晶体管连接点与共用电压间设置电容,并通过此电容以维持第一晶体管与第二晶体管连接点上的电压电平的变化量,另一方面则可防止像素电容的电荷产生漏电的现象,且可降低穿通电压(feedthrough voltage)对像素电压所造成的影响,维持显示的质量。
为让本实用新型的上述特征和优点能更明显易懂,下文特举实施例,并配合附图作详细说明如下。
附图说明
图1示出本实用新型实施例的像素电路的示意图;
图2示出本实用新型实施例中的像素电路的电容的架构的示意图;
图3示出本实用新型实施例的像素电路的动作波形图;
图4示出本实用新型实施例的显示面板的示意图。
附图标记说明:
100:像素电路;
TFT1、TFT2:晶体管;
CL:电容;
Cst:存储电容;
Cp:像素电容;
LK:端点;
COM:共用电压;
M1、M2:金属层;
I1:介电层;
D1:漏极;
S1:源极;
SS1:源极数据;
GS1:栅极驱动信号;
KP:数据保持时间区间;
WP:数据写入时间区间;
400:显示面板
GL1-GLN:栅极线;
SL1-SLM:源极线;
411-4NM:像素电路。
具体实施方式
请参照图1,图1示出本实用新型实施例的像素电路的示意图。像素电路100包括晶体管TFT1、TFT2、电容CL、存储电容Cst以及像素电容Cp。晶体管TFT1的第一端耦接至源极线SL,控制端耦接至栅极线GL,且晶体管TFT1的第二端耦接至端点LK,并通过端点LK耦接至晶体管TFT2的第一端。晶体管TFT2的控制端耦接至栅极线GL,且其第二端耦接至存储电容Cst以及像素电容Cp。此外,电容CL的一端耦接至端点LK,而电容CL的另一端接收共享电压COM。存储电容Cst以及像素电容Cp相互并联,并耦接在晶体管TFT2的第二端以及共用电压COM间。
在操作方面,像素电路100在数据写入时间区间,可通过栅极线GL传送的栅极驱动信号以使晶体管TFT1、TFT2导通。并且,源极数据通过源极线SL进行传递,并通过被导通的晶体管TFT1、TFT2被传送至存储电容Cst以及像素电容Cp。如此,源极数据可被写入存储电容Cst以及像素电容Cp中。值得一提的,在此同时,源极数据可通过被导通的晶体管TFT1,来被写入至电容CL中,如此,晶体管TFT2的第一端与第二端间的电压电平的差值,可以接近于0伏特。
在数据写入时间区间结束后,像素电路100可进入数据保持时间区间,此时,晶体管TFT1、TFT2依据栅极线GL所传送的被禁能的栅极驱动信号而被断开。基于电容CL中所存储的电荷,端点LK上的电平可维持实质上等于源极数据的电平。此时的端点LK上的电平,将不小于存储电容Cst以及像素电容Cp上的电平,并且与存储电容Cst以及像素电容Cp上(晶体管TFT2的第二端)的电平相接近。因此,存储电容Cst以及像素电容Cp上的电荷通过晶体管TFT1、TFT2而产生漏电的途径被阻隔,降低漏电现象产生的可能。
在此请注意,在本实施例中,像素电路100通过晶体管TFT1、TFT2建构较长的电流传输路径,使在当晶体管TFT1、TFT2被断开时,存储电容Cst以及像素电容Cp上的电荷通过晶体管TFT1、TFT2来产生漏电的电量以及漏电的机率可以被降低。并且,通过电容CL在端点LK上提供的电压电平,可以产生阻隔的效果,并使存储电容Cst以及像素电容Cp上的电荷通过晶体管TFT1、TFT2来产生漏电的可能性被降低。
在另一方面,在本实施例中,当像素电路100进入数据保持时间区间,晶体管TFT1、TFT2依据栅极驱动信号而被断开的瞬间,端点LK上的电压电平因穿通电压现象所造成的电压电平的瞬间变化量,也会因为电容CL的设置而被抑制。也就是说,通过电容CL所提供的稳压效果,晶体管TFT2的第一端以及第二端间的电压电平的差值,可以维持在一个很小的状态下(趋近于0伏特),并减低存储电容Cst以及像素电容Cp上的电荷产生漏电的可能。
在此请注意,为提供较佳的阻隔效果,电容CL的电容值可大于存储电容Cst以及像素电容Cp的电容值,或者,电容CL的电容值可不大于存储电容Cst以及像素电容Cp的电容值。在较佳的实施方式中,电容CL的电容值例如可约等于存储电容Cst以及像素电容Cp的电容值的5倍,但不限于此。
附带一提的,本实施例中,晶体管TFT1、TFT2可以为相同类型的薄膜晶体管,例如均为N型的薄膜晶体管。共用电压COM可以为直流电压。并且,像素电路100适用于设置在液晶显示面板或是电泳式显示面板。而关于电容CL的结构,则可以是为金属-绝缘层-金属(MIM)结构。
以下请参照图2,图2示出本实用新型实施例中的像素电路的电容的架构的示意图。电容CL通过金属层M1、介电层I1以及金属层M2来形成。其中,电容CL的上电极可以与晶体管TFT1的漏极D1以及晶体管TFT2的源极S1共享同相的金属层M1来形成,而电容CL的下电极则通过金属层M2来形成,并用以接收共用电压COM。
在这样的架构下,电容CL的设置不需要通过额外的光罩来完成。事实上,电容CL可以在晶体管TFT1、TFT2的制程过程中同步被产生。并在最少光罩的需求下,完成电容CL的设置。不会增加生产上所需要的成本。
以下请参照图3,图3示出本实用新型实施例的像素电路的动作波形图。其中,在数据写入时间区间WP中,栅极驱动信号GS1被拉高以导通晶体管TFT1、TFT2,并且,源极数据SS1通过晶体管TFT1、TFT2被写入至存储电容Cst以及像素电容Cp中,并使像素电压Vp被拉升。在数据写入时间区间WP后的数据保持时间区间KP中,像素电压Vp瞬间下降,但像素电压Vp下降的程度可以因电容CL的设置而受到抑制。并且,在数据保持时间区间KP中,像素电压Vp几乎维持在固定的电压电平上,不会因漏电而产生降低的现象。
通过软件进行模拟,在图3中,本实用新型实施例的像素电路在进入数据保持时间区间KP,并维持20毫秒后,像素电压Vp由8.6462伏特下降至7.0846伏特,仅产生1.5616伏特的下降。若将电容CL移除,并进行相同的软件模拟动作,可以发现,像素电压Vp将由8.0255伏特下降至5.8102伏特,产生2.2153伏特的下降。可以得知,电容CL的设置,有效抑制像素电压Vp的下降幅度。
以下请参照图4,图4示出本实用新型实施例的显示面板的示意图。显示面板400包括多条栅极线GL1-GLN、多条源极线SL1-SLM以及多个像素电路411-4NM。像素电路411-4NM中的每一可如图1示出的像素电路100。通过在像素电路411-4NM的每一中的端点LK与共用电压COM间设置电容CL以做为阻隔电容,像素电路411-4NM中的存储电容Cst、像素电容Cp所可能产生的漏电现象可以被减轻,操作过程中产生的穿通电压对存储电容Cst、像素电容Cp的电压电平的影响也可以被降低,维持像素电路411-4NM的显示质量。
综上所述,本实用新型中,通过在像素电路中,串接的晶体管TFT1、TFT2的连接点上设置电容,并通过这个电容所产生的阻隔作用,来使像素电路中的存储电容、像素电容中的电荷所可能产生的漏电现象有效的被减低。并且,通过电容所产生的阻隔作用,穿通电压对存储电容、像素电容所产生的图像也可以被降低,有效维持像素电路的显示质量。
最后应说明的是:以上各实施例仅用以说明本实用新型的技术方案,而非对其限制;尽管参照前述各实施例对本实用新型进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本实用新型各实施例技术方案的范围。
Claims (15)
1.一种像素电路,适用于显示面板,其特征在于,包括:
第一晶体管,其第一端耦接至源极线,所述第一晶体管的控制端耦接至栅极线;
第二晶体管,其第一端耦接至所述第一晶体管的第二端,所述第二晶体管的控制端耦接至所述栅极线;
电容,其第一端耦接至所述第一晶体管的第二端,所述电容的第二端接收共用电压;
存储电容,串接在所述第二晶体管的第二端以及所述共用电压间;以及
像素电容,串接在所述第二晶体管的第二端以及所述共用电压间。
2.根据权利要求1所述的像素电路,其特征在于,所述电容的电容值大于所述存储电容以及所述像素电容的电容值。
3.根据权利要求1所述的像素电路,其特征在于,所述电容的电容值不大于所述存储电容以及所述像素电容的电容值。
4.根据权利要求1所述的像素电路,其特征在于,所述第一晶体管与所述第二晶体管的形态相同。
5.根据权利要求4所述的像素电路,其特征在于,所述第一晶体管与所述第二晶体管皆为N型薄膜晶体管。
6.根据权利要求1所述的像素电路,其特征在于,所述电容的第一电极板与所述第一晶体管的第二端、所述第二晶体管的第一端共享同一金属层。
7.根据权利要求1所述的像素电路,其特征在于,所述电容的结构为金属-绝缘层-金属电容。
8.根据权利要求1所述的像素电路,其特征在于,所述电容用以在所述像素电路的电压保持时间区间中维持所述第一晶体管的第二端与所述第二晶体管第一端上的电压。
9.根据权利要求1所述的像素电路,其特征在于,所述共用电压为直流电压。
10.根据权利要求1所述的像素电路,其特征在于,所述显示面板为电泳式显示面板或液晶显示面板。
11.一种显示面板,其特征在于,包括:
多条栅极线;
多条源极线;以及
多个像素电路,分别耦接所述多条栅极线以及所述多条源极线,所述多个像素电路的每一包括:
第一晶体管,其第一端耦接至对应的源极线,所述第一晶体管的控制端耦接至对应的栅极线;
第二晶体管,其第一端耦接至所述第一晶体管的第二端,所述第二晶体管的控制端耦接至所述对应的栅极线;
电容,其第一端耦接至所述第一晶体管的第二端,所述电容的第二端接收共用电压;
存储电容,串接在所述第二晶体管的第二端以及所述共用电压间;以及
像素电容,串接在所述第二晶体管的第二端以及所述共用电压间。
12.根据权利要求11所述的显示面板,其特征在于,所述电容的电容值大于所述存储电容以及所述像素电容的电容值。
13.根据权利要求11所述的显示面板,其特征在于,所述电容的电容值不大于所述存储电容以及所述像素电容的电容值。
14.根据权利要求11所述的显示面板,其特征在于,所述电容的第一电极板与所述第一晶体管的第二端、所述第二晶体管的第一端共享同一金属层。
15.根据权利要求11所述的显示面板,其特征在于,所述电容用以在所述像素电路的电压保持时间区间中维持所述第一晶体管的第二端与所述第二晶体管第一端上的电压。
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2017
- 2017-10-25 CN CN201721382534.0U patent/CN207352947U/zh not_active Expired - Fee Related
- 2017-12-08 US US15/835,463 patent/US20190123072A1/en not_active Abandoned
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US11893938B2 (en) | 2020-03-16 | 2024-02-06 | Boe Technology Group Co., Ltd. | Pixel circuit, display panel and display apparatus |
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