CN207337386U - A kind of server master board test device - Google Patents

Abstract

The utility model discloses a testing device for a main board of a server, which comprises a PCB board card. The PCB board card is provided with a main board connector, a CPLD, an indicator lamp and a JTAG connector. The size of the PCB board card is the same as that of a CPU. Contacts are arranged on the connector, and the contacts are the same as the contacts on the CPU. The motherboard connector is connected to the CPLD through the contacts, and the CPLD is also respectively connected to the JTAG connector and the indicator light. The utility model can test multiple signals of the main board at the same time, saves time and improves work efficiency.

Description

A server motherboard testing device

technical field

The utility model relates to the technical field of server board card testing, in particular to a server board testing device.

Background technique

The main board is the core board of the server, and the core component CPU is located on the main board. In addition, in order to facilitate the maintenance and testing of the server, the CPU is not directly welded on the mainboard, but the socket for placing the CPU is welded on the mainboard. The CPU is installed in this socket.

The CPU has some configuration signals for configuring its working state, and the CPU collects the level of the configuration signals when it is powered on for configuration. In the motherboard design, some of these configuration signals are connected to the power supply or grounded through the resistor, and some are connected to other functional modules because they are multiplexed with other functions. In the test phase, it is necessary to test these configuration signals one by one to ensure that the CPU configuration meets the design requirements. However, this kind of test needs to continuously power on and off the system, and use an oscilloscope to test one by one, which is inefficient.

Utility model content

The purpose of the utility model is to provide a server main board testing device, which is used to solve the problem that the existing testing needs to continuously power on the system and use an oscilloscope to test one by one, and the testing efficiency is low.

The technical solution adopted by the utility model to solve the technical problems is: a server main board testing device, including a PCB board, the PCB board is provided with a main board connector, CPLD, indicator light and JTAG connector, and the PCB board The size of the CPU is the same as that of the CPU. There are contacts on the main board connector, which are the same as the contacts on the CPU. The main board connector is connected to the CPLD through the contacts. The CPLD is also connected to the JTAG connector and the indicator lamp.

Further, the contacts include a reset signal contact and a configuration signal contact, the motherboard connector is connected to the CPLD through the reset signal contact and the configuration signal contact respectively, and the CPLD is connected to the JTAG connector through the JTAG pin.

Further, there are multiple indicator lights, which are respectively connected to GPIO pins of the CPLD.

Further, the contacts also include error signal contacts, the error signal contacts are connected to the CPLD, and the CPLD is also connected to the PC through a serial port connector.

Further, the CPLD is also connected to a memory, and the memory is also connected to a signal reading device through a memory connector.

Further, the contacts also include power contacts, and the power contacts are connected to the CPLD through the ADC.

The effects provided in the content of the utility model are only the effects of the embodiments, rather than all the effects of the utility model. One of the above technical solutions has the following advantages or beneficial effects:

1. The PCB board is equipped with the same contacts as the CPU contacts, and the size of the PCB board is the same as that of the CPU, so that the PCB board can be installed in the CPU slot to simulate the presence of the CPU, and the design is flexible and ingenious.

2. Send multiple configuration signals to the CPLD through the contacts on the motherboard connector at the same time, and display the status of the configuration signals through the indicator lights, avoiding testing multiple configuration signals one by one, saving time, improving work efficiency, and testers The state of the configuration signal can be intuitively obtained through the state of the indicator light.

3. The CPLD is also connected to the memory. The memory is connected to the signal analysis device through the memory connector. The memory can store the configuration information of the test and send the configuration information to the signal analysis device, which is convenient for testers to analyze and view the configuration information.

4. The CPLD is also connected to the PC through the serial port connector, and the PC sends commands to the CPLD to make the CPLD send a specific error signal. By checking the BMC log, the reliability of the main board function is judged, so that the functional test of the main board is more comprehensive. At the same time, it overcomes the defect that it is difficult for the CPU to send an error signal in the traditional test.

Description of drawings

Fig. 1 is a schematic structural view of an embodiment of the device of the present invention.

Detailed ways

In order to clearly illustrate the technical features of this solution, the utility model will be described in detail below through specific implementation methods and in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for realizing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. It should be noted that components illustrated in the figures are not necessarily drawn to scale. The present invention omits descriptions of known components and processing techniques and processes to avoid unnecessarily limiting the present invention.

As shown in FIG. 1 , the utility model provides an embodiment of a testing device for a server main board.

The test device realizes the test purpose by designing a PCB (Printed Circuit Board, printed circuit board) board. The size of the PCB board is the same as that of the CPU, so that the PCB board can be plugged into the CPU slot. The PCB board includes a motherboard connector, which is provided with the same contacts as the CPU, which are used to contact the slot to transmit corresponding signals, and ground the in-position signal contacts on the motherboard connector to simulate the CPU in the bit.

The motherboard connector is connected to the GPIO pin of the CPLD through the reset signal contact, the configuration signal contact and the error signal contact respectively, and the power signal contact of the motherboard connector is also connected to the GPIO pin of the CPLD through the ADC. Wherein CPLD is an abbreviation of Complex Programmable Logic Device, which means a complex programmable logic device. In this embodiment, a CPLD with a model number of LCMXO2-4000HC-5TG144C can be selected. GPIO is the abbreviation of General Purpose Input Output, which means general purpose input/output. ADC is the abbreviation of Analog-to-Digital Converter, which means analog-to-digital converter. In this embodiment, an ADC whose model is ADC128 is selected. The CPLD detects whether the power supply of the PCB board is connected normally by obtaining the digital signal of the ADC, and correspondingly, detects whether the power supply of the CPU is normal.

The JTAG pins of the CPLD are connected to the JTAG connector for programming the configuration of the CPLD, that is, configuring corresponding functions for each pin of the CPLD, such as configuring the reset signal receiving function, configuring the signal receiving function, and power supply for the GPIO pins of the CPLD respectively. Signal receiving function, error signal sending function, etc. Among them, JTAG is the abbreviation of Joint Test Action Group, which means joint test working group. The JTAG connector of this embodiment can be a 2x5 header with a pin pitch of 2.45mm (that is, 2 rows of 5 pins, connected to two connectors with a pin pitch of 2.45mm).

The CPLD is also connected to the indicator light through the GPIO pin. There are multiple indicator lights, which are used to indicate whether to send a configuration signal, whether to send an error signal, whether to send a reset signal, whether to send a power signal, etc. The status signal is displayed by the light on or off.

The CPLD is also connected to the memory through the GPIO pins, and the memory is connected to the signal reading device through the memory connector. The memory is used to store configuration signals collected by the CPLD. The memory of this embodiment can be selected as the memory of AT24C64, and the memory connector can be selected as a 3pin header (connector of 3 pins), and the signal reading device reads the data in the memory through the memory connector, and the signal reading device is in Through the connection with the terminal equipment, the tester can analyze the configuration signal and so on on the terminal equipment.

The CPLD is also connected to a PC (personal computer, personal computer) through a serial port connector, and the GPIO pins of the CPLD are connected to the serial port connector. The CPLD sends an error signal, such as a CPU overheating signal. That is to say, it realizes simulating the CPU to send error signals, and overcomes the defect that it is difficult for the CPU to send error signals in the traditional test. After the CPU sends the error signal, check whether the log of the BMC (Baseboard Management Controller, baseboard management controller) detects the error signal, and test the reliability of the error signal sending function of the main board.

The process of testing with the device of the above embodiment is as follows: install the PCB board into the CPU slot and start the machine. CPLD automatically collects configuration information when the configuration signal takes effect (the configuration signal generally takes effect when the reset signal is released), stores it in the memory, indicates it through the indicator light, and prints it out through the serial port. Testers can observe any one of the outputs (indicators, serial ports, and storage information) to obtain the current CPU configuration status, and then compare it with the preset value to confirm whether there is a problem with the motherboard. At the same time, you can send commands to the CPLD through the serial port connector to make the CPLD send a specific error signal. After the CPU sends the signal, you can check the BMC log to see if such a signal is detected and verify its functional reliability.

Before testing, it is necessary to burn the configuration information for the CPLD through the JTAG connector. The burning information includes the function configuration of each pin of the CPLD, the configuration of the internal function module, etc. The CPLD mentioned above is connected to the reset signal contact through the GPIO pin. , Configure multiple components such as signal contacts, ADCs, and indicator lights. The connected GPIO pins are different GPIO pins, and each pin can process different input and output signals because the JTAG connector has a good understanding of the CPLD. The reason for pin programming configuration. Therefore, in the above description, the GPIO pins are not named separately.

The above is only a preferred embodiment of the utility model, and for those of ordinary skill in the art, without departing from the principle of the utility model, some improvements and modifications can also be made, and these improvements and modifications are also regarded as It is the protection scope of the utility model.

Claims (6)

1. a server main board testing device, it is characterized in that: comprise PCB board, be provided with main board connector, CPLD, indicator light and JTAG connector on the PCB board, the size of described PCB board is identical with the size of CPU, The motherboard connector is provided with contacts, the contacts are the same as the contacts on the CPU, the motherboard connector is connected to the CPLD through the contacts, and the CPLD is also respectively connected to the JTAG connector and the indicator light. 2. The test device according to claim 1, characterized in that: the contacts include a reset signal contact and a configuration signal contact, the motherboard connector is connected to the CPLD through the reset signal contact and the configuration signal contact respectively, and the CPLD passes through The JTAG pins connect to the JTAG connector. 3. The testing device according to claim 1 or 2, characterized in that: there are a plurality of said indicator lights, which are respectively connected to GPIO pins of the CPLD. 4 . The test device according to claim 1 , wherein the contacts further include an error signal contact, the error signal contact is connected to the CPLD, and the CPLD is also connected to the PC through a serial port connector. 5. The test device according to claim 1, characterized in that: the CPLD is also connected to a memory, and the memory is also connected to the signal reading device through a memory connector. 6 . The testing device according to claim 1 , wherein the contacts further include power contacts, and the power contacts are connected to the CPLD through the ADC.