CN207301134U - Vertical probe card and probe head for chip measurement - Google Patents

Abstract

The present disclosure provides a vertical probe card and a probe head for chip measurement. The probe head includes: an upper carrier plate, including a plurality of first openings; a lower carrier plate comprising a plurality of second openings; and a plurality of probes, wherein each probe set is assembled in one of the first openings and one of the second openings corresponding to each other, and wherein a pitch of two adjacent first openings of the upper carrier plate is different from a pitch of two adjacent second openings of the lower carrier plate.

Description

Vertical probe card and probe head for chip metrology

technical field

The disclosure relates to a probe head, in particular to a vertical probe card and a probe head for chip measurement.

Background technique

In recent years, with the development of electronic products toward precision and multi-functionality, the chip structure of integrated circuits used in electronic products also tends to become more complex. In the manufacture of chips, batch mass production is usually adopted. Therefore, in order to ensure the electrical quality of the chips, chip-level measurements are performed before the chips are packaged. In the current chip manufacturing process, a probe card is generally used to test the chip. And according to the type of probe, it can be divided into cantilever probe card and vertical probe card. In use, by electrically contacting the probe of the probe card to the contact pad of the chip, and then connecting the electrical signal to the tester (Tester) through the circuit board of the probe card, the tester can transmit test signals to the chip or receive signals from the tester. The output signal of the chip can further achieve the effect of measuring the electrical characteristics of the chip, and the user can further reject the bad chip according to the measurement result for subsequent packaging processing.

Please refer to FIG. 1 , which shows a schematic structural diagram of a conventional probe head 10 for a vertical probe card. The probe head 10 is manufactured in an assembled manner, and mainly includes an upper die 11 , a lower die 12 , a spacer 13 , and a plurality of probes 14 . A plurality of tiny openings 110 and 120 are formed on the upper carrier plate 11 and the lower plate 12, and the spacer plate 13 is a hollow structure, wherein the positions of the hollow structures correspond to the openings 110 of the upper carrier plate 11 and the lower plate 12 and 120 positions. The assembly of the probe head 10 is completed by locking the upper board 11 and the lower board 12 on the spacer board 13 respectively, and passing each probe 14 through the corresponding opening of the upper board 11 and the lower board 12 . In use, one end of the probe 14 near the upper board 11 is used for electrical contact with the test carrier board 15 of the vertical probe card, and one end of the probe 14 near the download board 12 is used for contacting the chip to be tested. W electrical contact.

As shown in FIG. 1 , in the conventional probe head 10 , the distance P1 between two adjacent openings of the upper board 11 and the lower board 12 will remain the same. However, with the miniaturization of electronic products, the size of the pitch P1 is bound to shrink accordingly, so that the thickness of the partition wall between the openings becomes thinner and thinner. Moreover, due to processing limitations, when the pitch P1 is less than 100 microns, the problem of cracking of the partition walls is likely to occur, resulting in adjacent probes contacting each other and causing a short circuit. Furthermore, due to assembly requirements, the aperture of the upper board 11 is usually larger than the aperture of the lower board 12. Therefore, the upper board 11 is more difficult to manufacture and has a higher cost. Risk of hole breaks.

In view of this, it is necessary to provide a vertical probe card and a probe head for chip measurement, so as to solve the problems existing in the prior art.

Utility model content

In order to solve the above-mentioned technical problems, the purpose of this disclosure is to provide a vertical probe card and probe head for chip measurement, by increasing the distance between the upper board of the probe head, to avoid the occurrence of broken holes and the probe The problem of contact and short circuit.

In order to achieve the above object, the present disclosure provides a probe head for chip measurement, comprising: an upper board including a plurality of first openings; a lower board including a plurality of second openings; and a plurality of probes Needles, wherein each probe is assembled in one of the first openings and one of the second openings corresponding to each other, and wherein the adjacent two first openings of the upper carrier plate The spacing is different from the spacing between two adjacent second openings of the loading board.

In one preferred embodiment of the present disclosure, the distance between two adjacent first openings of the upper carrier board is greater than the distance between two adjacent second openings of the lower board.

In one preferred embodiment of the present disclosure, the distance between two adjacent second openings of the loading plate is less than 100 microns.

In one of the preferred embodiments of the present disclosure, the probe head further includes a spacer plate, disposed between the upper carrier plate and the lower carrier plate, for separating the upper carrier plate and the lower carrier plate from each other a distance.

The present disclosure also provides a vertical probe card for chip measurement, including: a circuit board; a test carrier embedded on the circuit board, including a plurality of upper contact pads; a probe head, including : an upper carrier plate, comprising a plurality of first openings; a lower plate, comprising a plurality of second openings; and a plurality of probes, wherein each probe is assembled in one of the first openings corresponding to each other and one of the second openings; and a positioning jig, assembled on the circuit board, for positioning the probe head on the circuit board, so that all of the probe heads One end of the plurality of probes is in electrical contact with the corresponding upper contact pad on the test carrier board, wherein the distance between two adjacent first openings of the upper carrier board is different from that of the adjacent first openings of the lower carrier board. The distance between the two second openings.

In one preferred embodiment of the present disclosure, one end of the plurality of probes of the probe head close to the upper carrier board is in electrical contact with the test carrier board, and the probe head of the probe head One end of the plurality of probes close to the download board is in electrical contact with a chip to be tested.

In one preferred embodiment of the present disclosure, the distance between two adjacent upper contact pads of the test carrier board is greater than the distance between two adjacent second openings of the lower board.

Compared with the prior art, the present disclosure sets the spacing of the openings of the loading board to match the spacing of the lower contact pads of the chip to be tested, and sets the spacing of the openings of the loading board to be greater than the spacing of the openings of the loading board , so as to reduce the risk of hole breakage in the upper and lower boards, thereby avoiding the problem that adjacent probes will contact each other and cause a short circuit.

Description of drawings

FIG. 1 shows a schematic structural view of a conventional probe head for a vertical probe card;

FIG. 2 is a schematic exploded view of parts of a vertical probe card according to a preferred embodiment of the present disclosure; and FIG. 3 is a schematic structural view of the probe card of FIG. 2 .

Detailed ways

In order to make the above and other objectives, features, and advantages of the present disclosure more comprehensible, preferred embodiments of the present disclosure will be exemplified below in detail with accompanying drawings.

Please refer to FIG. 2 and FIG. 3 . FIG. 2 shows an exploded view of parts of the vertical probe card 1 according to a preferred embodiment of the present disclosure, and FIG. 3 shows a schematic structural view of the probe card in FIG. 2 . The vertical probe card 1 is mainly composed of a probe head 20 (ProbeHead), a positioning fixture 30, a circuit board 40 (PCB), a test carrier board 50 (substrate) and a matching frame support member 60, wherein the test carrier The board 50 is embedded on the circuit board 40 , and the positioning jig 30 is assembled on the circuit board 40 and is used for fixing and positioning the probe head 20 on the circuit board 40 .

As shown in FIG. 3 , the probe head 20 includes an upper die 21 , a lower die 22 , a spacer 23 , and a plurality of probes 24 . The upper board 21 is formed with a plurality of tiny first openings 210 , and the lower board 22 is formed with a plurality of tiny second openings 220 . The spacer plate 23 is a hollow structure, and is arranged between the upper carrier plate 21 and the lower plate 22 for keeping the upper carrier plate 21 and the lower plate 22 at a distance from each other. The positions of the hollow structures of the spacer plate 23 correspond to the positions of the first openings 210 and 220 of the upper carrier plate 21 and the lower plate 22. When assembling, first fix the upper board 21 and the lower board 22 on the spacer board 23 respectively, and then assemble each probe 24 and pass through one of the first openings 210 and one of the second openings corresponding to each other. hole 220 to complete the assembly of the probe head 20 .

As shown in FIG. 3 , a plurality of upper contact pads 501 are disposed on the test carrier 50 , and a plurality of lower contact pads P are also disposed on the chip W to be tested. In use, one end of each probe 24 near the upper carrier board 21 is in electrical contact with the corresponding upper contact pad 501 on the test carrier board 50 of the vertical probe card 1, and one end near the lower board 22 is in electrical contact with the test carrier board 50 to be tested. The corresponding lower contact pads P on the chip W are in electrical contact.

As shown in FIG. 3 , the pitch P2 of the adjacent first openings 210 of the upper carrier board 21 is set to meet the pitch P4 of the adjacent upper contact pads 501 of the test carrier board 50 , and the adjacent second contact pads 501 of the lower carrier board 22 The pitch P3 of the openings 220 is set to conform to the pitch of the lower contact pads P of the chip W to be tested, wherein the pitch P2 of the adjacent first openings 210 of the upper carrier board 21 and the adjacent upper contact pads 501 of the test carrier board 50 The pitch P4 of each is different from the pitch P3 of the adjacent second openings 220 of the loading plate 22 . More specifically, the pitch P1 between adjacent first openings 210 of the upper carrier board 21 and the pitch P4 between adjacent upper contact pads 501 of the test carrier board 50 are larger than the adjacent second openings 220 of the lower board 22 The pitch P2. Therefore, for the first openings 210 with a relatively large diameter, increasing the distance P1 between two adjacent first openings 210 can effectively reduce the manufacturing difficulty. It should be understood that the probe head 20 of this design is particularly suitable for use in manufacturing products in which the distance P2 between adjacent second openings 220 of the loading plate 22 is less than 100 microns.

Furthermore, in the vertical probe card 1 of the present disclosure, since the pitch P1 of the adjacent first openings 210 of the upper board 21 is increased (for example, the pitch P2 of the adjacent second openings 220 of the lower board 22 is 100 microns, the pitch P1 of the adjacent first openings 210 of the upper carrier board 21 is increased to be greater than 100 microns), so that the pitch P4 of the adjacent upper contact pads 501 of the test carrier board 50 is also correspondingly increased, so that The manufacturing difficulty of the test carrier board 50 is also reduced, thereby improving the manufacturing yield of the test carrier board 50 .

In summary, the present disclosure sets the spacing of the openings of the downloading board to match the spacing of the lower contact pads of the chip to be tested, and sets the spacing of the openings of the downloading board to be greater than the spacing of the openings of the downloading board to achieve The risk of hole breakage in the upper and lower boards is reduced, thereby avoiding the problem that adjacent probes will contact each other and cause a short circuit.

Although the disclosure has been disclosed above with preferred embodiments, it is not intended to limit the disclosure. Those skilled in the art to which the disclosure belongs can make various modifications without departing from the spirit and scope of the disclosure. and retouching, so the scope of protection of this disclosure should be defined by the appended claims.

Claims (10)

1. A probe head for chip measurement, characterized in that, comprising: an upper board, including a plurality of first openings; a download plate, including a plurality of second openings; and A plurality of probes, wherein each probe is assembled in one of the first openings and one of the second openings corresponding to each other, and wherein the adjacent two first openings of the upper carrier plate The spacing of the openings is different from the spacing of two adjacent second openings of the loading board. 2. The probe head for chip measurement as claimed in claim 1, wherein the distance between the adjacent two first openings of the upper board is greater than that of the adjacent first openings of the lower board. The distance between the two second openings. 3. The probe head for chip measurement according to claim 1, wherein the distance between two adjacent second openings of the loading board is less than 100 microns. 4. The probe head for chip measurement according to claim 1, wherein the probe head also includes a spacer plate, which is arranged between the upper board and the lower board, It is used to keep the upper board and the lower board at a distance from each other. 5. A vertical probe card for chip measurement, characterized in that it comprises: a circuit board; a test carrier, embedded on said circuit board, comprising a plurality of upper contact pads; A probe head, containing: an upper board, including a plurality of first openings; a download plate, including a plurality of second openings; and a plurality of probes, wherein each probe is assembled in one of the first openings and one of the second openings corresponding to each other; and A positioning jig, assembled on the circuit board, is used to position the probe head on the circuit board, so that one end of the plurality of probes of the probe head is aligned with the test carrier board The corresponding upper contact pads on the upper board are in electrical contact, wherein the distance between two adjacent first openings of the upper carrier board is different from the distance between two adjacent second openings of the lower board. 6. The vertical probe card for chip measurement as claimed in claim 5, wherein the distance between two adjacent first openings of the upper carrier board is greater than that of the lower carrier board. The distance between two adjacent second openings. 7. The vertical probe card for chip measurement according to claim 5, wherein the distance between two adjacent second openings of the loading board is less than 100 microns. 8. The vertical probe card for chip measurement as claimed in claim 5, wherein the probe head further comprises a spacer plate arranged between the upper board and the lower board space, used to make the upper board and the lower board a distance from each other. 9. The vertical probe card for chip measurement as claimed in claim 5, wherein one end of the plurality of probes of the probe head close to the upper carrier board is connected to the The test carrier board is in electrical contact, and one end of the plurality of probes of the probe head close to the download board is in electrical contact with a chip to be tested. 10. The vertical probe card for chip measurement as claimed in claim 5, wherein the distance between two adjacent upper contact pads of the test carrier is greater than that of the carrier board. The distance between two adjacent second openings.