CN207265044U - Pin grid array packaging structure - Google Patents

Abstract

The utility model relates to a pin grid array packaging structure, which comprises a silicon substrate with a front side and a back side which are arranged in a back-to-back manner, a chip arranged on the front side of the silicon substrate, a packaging bottom plate arranged below the silicon substrate, and a cover body surrounding the silicon substrate and the chip; the silicon substrate is arranged on the upper surface of the packaging bottom plate and comprises a rectangular lead bonding area and a chip mounting area; the wire bonding area is provided with a bonding pad; a metal lead and a conductive electrode electrically connected to the metal lead are formed on an upper surface of the silicon substrate, the metal lead including a plurality of conductor segments bonded at ends thereof with spaced apart metal terminal pads; the plurality of conductor segments includes first conductor segments extending outwardly from bond pads on the wire bond region and interleaved second conductor segments extending inwardly from bond pads on the wire bond region; the chip is inverted on the silicon substrate, the chip having a die, the die of the chip being electrically connected to the conductive electrode.

Description

Pin Grid Array Package Structure

technical field

The utility model relates to a pin grid array packaging structure, which belongs to the field of semiconductor packaging.

Background technique

In the field of CUP packaging, due to the increasing commercial demand for semiconductor integrated circuits that can perform more and more functions, the size of semiconductor integrated circuit chips is becoming very large and consumes a large amount of power. As the size and power requirements have increased, the complexity and cost of providing interconnection and packaging to semiconductor chips has also increased. To reduce cost and increase reliability, some prior art interconnect designs have provided insulator substrates such as ceramics or wiring boards on which semiconductor chips or dies are mounted.

Metallic conductors or traces on the wiring board are typically used to interconnect the bond pads on the outer lead bonding area surrounding the die to the multiple terminal pins. Traces in prior art designs are typically routed away from the outer lead bonding area toward the outside edge of the package using very long or very short interconnect traces to the various external pins. In other prior art designs, the traces are again routed away from the outer lead bond areas towards the die using either very long or very short interconnect traces to the various external terminal pins. Thus, very long trace lengths have an increase in parasitic inductance and parasitic capacitance compared to very short trace lengths. In addition, this will cause electrical signal delay problems between different traces or signal channels.

It would therefore be desirable to provide a pin grid array package with a higher packing density than conventionally available pin grid array packages. In addition, it would be advantageous to reduce the physical length of very long traces so that the difference in length of all traces is smaller than that of conventional pin grid array structures, thereby equalizing the electrical signal delay between different channels . This is accomplished in the present invention by providing a substrate or wiring board with a plurality of conductor segments, with first conductor segments extending outward from bond pads on the outer lead bonding area and alternate second conductor segments extending outward from the outer Bond pads on the wire bonding area extend inwardly. In addition, a network of delay lines (capacitive loading) is formed in the conductor segments to further equalize signal delays between different conductor segments.

In order to solve the above-mentioned problems, U.S. Patent Application No. 4887148 discloses the following: a pin grid array package structure includes: a package body member; a wiring board having a center portion for receiving a semiconductor chip; a tape lead circuit; and a cover member . A plurality of metal terminal pins extend over substantially the entire top surface and the entire bottom surface of the body member. Although this document solves the aforementioned problems, the above-mentioned documents have the following problems: 1. In terms of heat dissipation, additional heat-conducting materials need to be filled, so the manufacturing process is relatively complicated; 2. Since the wiring board is a printed circuit board (PCB), so, It is relatively difficult to manufacture adjacent conductor segments. More importantly, there is a problem of interference between adjacent conductor segments on the flexible circuit board. In addition, because the chip is square, it is necessary to use tape leads to connect The chip is electrically connected to the conductor segment on the wiring board, so the relative manufacturing process is relatively complicated.

Utility model content

The purpose of the utility model is to provide a pin grid array packaging structure, which saves cost and simplifies the production process, and reduces the problems of interference between adjacent conductor segments.

In order to achieve the above object, the utility model provides the following technical solutions: a pin grid array packaging structure, including a silicon substrate with oppositely arranged front and back sides, a chip arranged on the front side of the silicon substrate, and a a package base plate under the silicon substrate, and a cover disposed above the package base plate to surround the silicon substrate and the chip;

The package bottom plate has an upper surface and a lower surface arranged opposite to each other, and a plurality of metal terminal pins are arranged on the package bottom plate, and the metal terminal pins pass through the package bottom plate and are on the upper surface of the package bottom plate forming terminal pin ends;

The silicon substrate is arranged on the upper surface of the package bottom plate, the metal terminal pins pass through the silicon substrate, and the silicon substrate includes a rectangular wire bonding area and a chip mounting area; the wire bonding area set in a spaced relationship with the chip mounting area, the wire bonding area is formed with bonding pads; metal leads and conductive electrodes electrically connected to the metal leads are formed on the upper surface of the silicon substrate, The metal lead comprises a plurality of conductor segments junctured at their ends with spaced apart metal terminal pads vertically aligned or aligned with corresponding ends of the terminal pins a plurality of said conductor segments comprising first conductor segments extending outward from said bonding pads on a wire bonding area and interleaved second conductor segments extending inward from said bonding pads on said wire bonding area ;

The chip is inverted on the silicon substrate, the chip has a die, the die of the chip is electrically connected to the conductive electrodes.

Further: the pin grid array package structure further includes a network delay device, the network delay device is formed in the metal lead to equalize the signal delay between different conductor segments.

Further: the network delay device includes a plurality of first outwardly extending pile members integrally formed with the conductor segment.

Further: the network delay device further includes a plurality of second outwardly extending pile members integrally formed with the conductor segment, and the second outwardly extending pile members are arranged opposite to the first outwardly extending pile members .

Further: it is characterized in that each of the second outwardly extending pile member and the first outwardly extending pile member is loaded with a capacitor.

Further: the capacitor is grounded.

Further: the terminal pins are arranged in rows and columns to form a matrix array rotated by 45° relative to the package bottom plate.

Further: a decoupling capacitor network is provided on the packaging bottom plate, and the decoupling capacitor network includes a plurality of discrete capacitors. Four corner areas are formed on the package bottom plate, and a plurality of capacitors are arranged in the four corner areas.

Further: the package bottom plate is formed of a thermoplastic material in which the metal terminal pins are molded, and the cover is formed of a thermally conductive material.

The beneficial effect of the utility model is that: since the silicon substrate is used, its heat dissipation capability is excellent, so there is no need to fill the heat-conducting material in the cover body, which saves the cost and simplifies the production process, and can reduce the cost of the pin grid array packaging structure. The overall volume; and the chip can be inverted on the silicon substrate, so the installation of the chip is more convenient, and there is no need to use additional TAB tape for electrical connection; and due to the characteristics and manufacturing characteristics of the silicon substrate, the conductor segment can be set Narrower, thereby further reducing the interference between adjacent conductor segments, and the layout is also more convenient. And because the conductor segment can be set narrower, the impedance can be further effectively reduced.

The above description is only an overview of the technical solution of the utility model. In order to understand the technical means of the utility model more clearly and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiment of the utility model with accompanying drawings. back.

Description of drawings

Fig. 1 is the cross-sectional view of the semiconductor single-layer network encapsulation structure of the present utility model;

Fig. 2 is a top plan view of the semiconductor single-layer network package structure shown in Fig. 1 taken along line 2-2;

3 is a top plan view of a silicon substrate showing outwardly facing and inwardly directed conductor segments of the silicon substrate;

Figure 4 is a top plan view of a portion of a conductor segment containing a network delay device.

Detailed ways

Below in conjunction with accompanying drawing and embodiment, the specific embodiment of the utility model is described in further detail. The following examples are used to illustrate the utility model, but not to limit the scope of the utility model.

1, a pin grid array (PGA) packaging structure 10 shown in a preferred embodiment of the present invention includes a silicon substrate 14 with a front side 28 and a back side 26 arranged oppositely, arranged on the The chip 18 on the front side 28 of the silicon substrate 14, the packaging base 12 arranged below the silicon substrate 14, and the cover 22 covering the packaging base 12 to surround the silicon substrate 14 and the chip 18 .

Referring to FIG. 1 and FIG. 2 , a plurality of metal terminal pins 24 are disposed on the package base 12 . The package backplane 12 is defined in a generally diamond-shaped configuration, preferably formed from a thermoplastic material to contain a plurality of metal terminal pins 24 when IS molded, for example, using conventional injection molding equipment. The package base 12 has an upper surface (not labeled) and a lower surface (not labeled) opposite to each other, the metal terminal pins 24 penetrate through the package base 12 and are formed on the upper surface of the package base 12 terminal pin end 30 . The terminal pin portion 30 may be a protrusion protruding from the package substrate 12 . The dimensions of the four sides of the package base 12 vary depending on the number of metal terminal pins 24 , and the number of metal terminal pins 24 may range from 68 pins to 410 pins. A plurality of metal terminal pins 24 are arranged in rows and columns within the diamond-shaped package substrate 12 to provide a matrix array. The rows and columns of the metal terminal pins 24 are formed as a matrix array rotated by 45° relative to the package base 12 .

Please refer to FIG. 3 and in conjunction with FIG. 1, the silicon substrate 14 is disposed on the upper surface of the package base plate 12, the metal terminal pins 24 penetrate through the silicon substrate 14, and the silicon substrate 14 has a rectangular shape. The wire bonding area 34a and the chip mounting area (not numbered). The wire bonding area 34a is the OLB area, and the upper surface of the silicon substrate 14 includes other areas (not numbered) surrounding the wire bonding area 34a in addition to the wire bonding area 34a and the chip mounting area. The wire bonding area 34a is disposed in spaced-apart relationship to the chip mounting area, the wire bonding area 34a being formed with a bond pad 42a. Metal leads and conductive electrodes (not shown) electrically connected to the metal leads are formed on the upper surface of the silicon substrate 14 . The metal leads and conductive electrodes are manufactured through conventional silicon substrate 14 manufacturing processes such as etching and deposition. The metal lead includes a plurality of conductor segments 40, the plurality of conductor segments 40 are joined at their ends with spaced apart metal terminal pads 36, and the metal terminal pads 36 are connected to the corresponding terminal pin ends 30. Align or align vertically. The silicon substrate 14 is provided with a plurality of through holes 38 penetrating the silicon substrate 14, the through holes 38 penetrate the lower surface from the upper surface of the silicon substrate 14, and the metal terminal pins 24 pass through the through holes. 38 to be electrically connected with corresponding metal leads. Laser welding, ultrasonic welding, etc. can be used for electrical connection. The plurality of conductor segments 40 include a first conductor segment 40a extending outward from the bonding pad 42a on the wire bonding area 34a and an alternate conductor segment extending inward from the bonding pad 42a on the wire bonding area 34a. The second conductor segment 40b, wherein part of the conductor part extends into the chip mounting area to increase the packaging density. In the present invention, since the staggered portion of the first conductor segment 40a is away from the OLB region 34a, its physical length is made shorter, and the very long and long distance between the different metal terminal pads 36a in the PGA package of the prior art Very short interconnect traces are eliminated. Therefore, the difference between the physical lengths of the conductor segments 40 of the present invention is less than 50% of that of the conventional PGA package. As a result, electrical signal delays between different channels or conductors have been significantly reduced, but not eliminated. Furthermore, since the distance between any two conductor segments 40 (ie, two segments 40a ) extending in the same direction has been increased by the staggered pattern, crosstalk between these conductor segments 40 is minimized.

Referring to FIG. 4 , the PGA package structure 10 further includes a network delay device formed in the metal leads to equalize signal delays between different conductor segments 40 . The network delay device includes a plurality of first outwardly extending stake members 43 a integrally formed with the conductor segment 40 . The network delay device further includes a plurality of second outwardly extending pile members 43b integrally formed with the conductor segment 40, the second outwardly extending pile members 43b are opposite to the first outwardly extending pile members 43a . Capacitors are loaded on each of the second outwardly extending pile member 43b and the first outwardly extending pile member 43a. The capacitor is set to ground (DCC), thus achieving an open circuit setting. By setting the capacitor to ground, the impedance can be adjusted during production. The numbers of the first outwardly extending pile member 43a and the second outwardly extending pile member 43b can be set according to actual needs. By setting the time-delay network delay device, it is possible to realize the impedance matching capability and thus equalize the signal delay between different channels, thereby compensating for any discontinuities in the metal terminal pin 24, the metal lead and the package structure. influences.

Please refer to Fig. 1 and Fig. 2, the mounting area of the chip 18 is in the shape of a rectangle. The chip 18 is placed upside down on the silicon substrate 14 in a chip mounting area, the chip 18 has dies 46a, 46b, the dies 46a, 46b of the chip 18 are electrically connected to conductive electrodes. In the utility model, since the silicon substrate 14 is adopted, its heat dissipation capability is excellent, so there is no need to fill the heat-conducting material in the cover body 22, which saves cost and simplifies the production process, and the silicon substrate 14 can be inverted by the chip 18. Therefore, the installation of the chip 18 is more convenient, and there is no need to use additional TAB tape for electrical connection, and due to the inherent characteristics and manufacturing characteristics of the silicon substrate 14, the conductor segment 40 can be set narrower, thereby further reducing the adjacent Interference between the conductor segments 40, the layout is also more convenient. And because the conductor segment 40 can be set narrower, the impedance can be further effectively reduced.

Please refer to FIG. 1 and FIG. 2 , the shape and size of the silicon substrate 14 are the same as those of the package base plate 12 , and are overlapped and fixed on the package base plate 12 . A decoupling capacitor network is provided on the package base 12 , and the decoupling capacitor network includes a plurality of discrete capacitors 25 . Four first corner regions A are formed on the package base 12 . By rotating the matrix array by approximately 45° relative to the four sides of the body member 12 to have four large spatial first corner regions A. The discrete capacitors 25 that would normally be formed on the silicon substrate 14 can be effectively accommodated by the four first corner regions A. It should be noted that some of the metal terminal pins 24 (for example, the terminal pin 24 a ) are disposed within an outer lead bonding region 34 a (OLB region 34 a ) that is a part of the silicon substrate 14 . Furthermore, a certain number of other metal terminal pins 24b are arranged below the area of the dies 46a, 46b. Therefore, packing density can be increased.

Please refer to FIG. 1 , the cover body 22 is formed of a heat-conducting material. The cover 22 has a cavity 48 , and the chip 18 is accommodated in the cavity 48 . In this embodiment, the overall volume of the PGA package structure 10 is reduced because there is no need to arrange a thermally conductive material in the cover body 22, which includes the first corner on the package bottom plate 12. Area A is similar to the four second corner areas B. These second corner regions B can be effectively used to accommodate a large number of discrete electrical components 52 (eg, resistors, capacitors, inductors, etc.), which can be suitably connected to the silicon substrate 14 . The second corner area B is the four inner end corner spaces of the cavity. Lid 22 may preferably be formed of a material that conducts heat well and has side flanges 54 that may be hermetically sealed or bonded to package backplane 12 to prevent exposure to the atmosphere. Alternatively, the cover 22 may be made of a ceramic material such as aluminum nitrate. Bonding of the lid 22 to the silicon substrate 14 can be accomplished in any number of conventional ways, such as thermal bonding, ultrasonic welding, or adhesive bonding using epoxy adhesives.

To sum up: due to the use of the silicon substrate 14, its heat dissipation capability is excellent, so there is no need to fill the heat-conducting material in the cover body 22, which saves costs and simplifies the production process, and can reduce the size of the pin grid array package structure 10 The overall volume of the chip 18 can be turned upside down on the silicon substrate 14, so the installation of the chip 18 is more convenient, and there is no need to use additional TAB tape for electrical connection; The conductor segment 40 is set narrower, thereby further reducing the interference between adjacent conductor segments 40, and the layout is also more convenient. And because the conductor segment 40 can be set narrower, the impedance can be further effectively reduced.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the utility model, and the description thereof is relatively specific and detailed, but it should not be understood as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the scope of protection of the utility model patent should be based on the appended claims.

Claims (9)

1. A kind of 1. Pin-Grid Array encapsulating structure, it is characterised in that：Including the silicon lining with the front and back being disposed opposite to each other Bottom (14), the positive chip (18) for being arranged on the silicon substrate, the package floor (12) being arranged on below the silicon substrate and It is located above the package floor to surround the lid (22) of the silicon substrate, chip；

   The package floor has the upper and lower surface being disposed opposite to each other, and multiple metal terminals are provided with the package floor Pin (24), the metal terminal pin run through the package floor, and in forming terminal on the upper surface of the package floor Pin end (30)；

   The silicon substrate is arranged at the upper surface of the package floor, and the metal terminal pin runs through the silicon substrate, described Silicon substrate includes the wire bonding region (34a) and chip mounting area of rectangular shape；The wire bonding region is configured to The relation got around at interval with chip mounting area, the wire bonding region is formed with bonding pad (42a)；The silicon substrate Upper surface on formed with metal lead wire and with the metal lead wire electrical connection conductive electrode, the metal lead wire include it is more A conductor segment (40), multiple conductor segments are tied in its end with metal end subpad spaced apart, the metal end subpad with Corresponding the terminal pins end vertical alignment or alignment；Multiple conductor segments are included as described in from wire bond region Outwardly extending first conductor segment (40a) of bonding pad and the friendship to extend internally from the bonding pad on the wire bonding region Wrong the second conductor segment (40b)；

   For the chip upside down on the silicon substrate, the chip has tube core (46a, 46b), tube core and the conduction of the chip Electrode is electrically connected.
2. 2. Pin-Grid Array encapsulating structure as claimed in claim 1, it is characterised in that the Pin-Grid Array encapsulation knot Structure further includes network delay device, and the network delay device is formed in the metal lead wire between gradeization different conductor section Signal delay.
3. 3. Pin-Grid Array encapsulating structure as claimed in claim 2, it is characterised in that the network delay device include with What the conductor segment was integrally formed multiple first stretches out pile element (43a).
4. 4. Pin-Grid Array encapsulating structure as claimed in claim 3, it is characterised in that the network delay device further includes Stretch out pile element (43b) with the conductor segment is integrally formed multiple second, described second stretches out pile element and institute First pile element that stretches out is stated to be oppositely arranged.
5. 5. Pin-Grid Array encapsulating structure as claimed in claim 4, it is characterised in that each described second stretches out stake Component, first, which stretch out, is loaded with capacitance on pile element.
6. 6. Pin-Grid Array encapsulating structure as claimed in claim 5, it is characterised in that the capacity earth is set.
7. 7. Pin-Grid Array encapsulating structure as claimed in claim 1, it is characterised in that the terminal pins, which are arranged, embarks on journey And row rotate 45 ° of matrix array to be formed relative to the package floor (12).
8. 8. Pin-Grid Array encapsulating structure as claimed in claim 7, it is characterised in that solution is provided with the package floor Coupling capacitor network, includes multiple discrete capacitors in the decoupling capacitors network, formed with four in the package floor Corner regions (A), multiple capacitors are arranged on four corner regions

   (A) in.
9. 9. Pin-Grid Array encapsulating structure according to claim 1, it is characterised in that the package floor is by the gold Belonging to terminal pins, molding thermoplastic is formed wherein, and the lid is formed by Heat Conduction Material.