CN207053395U - A kind of DC decompression adjusts circuit structure - Google Patents

Abstract

The utility model relates to a DC step-down regulation circuit structure, which is characterized in that it comprises a switch circuit and a feedback regulation circuit; the switch circuit is connected to the feedback regulation circuit; the output end of the switch circuit is connected with an output capacitor; Voltage; the feedback regulation circuit includes a voltage divider power supply, a first operational amplifier and a second operational amplifier; the positive input of the first operational amplifier is connected with the first voltage divider circuit; the negative input of the first operational amplifier is connected with the output capacitor ; The connection point between the positive input terminal of the first operational amplifier and the first voltage divider circuit is connected with a pull-down circuit; the output terminal of the first operational amplifier is connected with a switch circuit; the positive input terminal of the second operational amplifier is connected with a second divider voltage circuit; the inverting input end of the second operational amplifier is connected to the inverting input end of the first operational amplifier; the output end of the second operational amplifier is connected to the switch circuit; the output end of the second operational amplifier is also connected to the pull-down circuit.

Description

A kind of DC step-down regulation circuit structure

technical field

The utility model belongs to the technical field of power supply step-down regulation, in particular to a DC step-down regulation circuit structure.

Background technique

In the existing electronic equipment, it is necessary to convert the DC power provided by the power supply into the voltage required by various chips. The existing DC step-down regulator circuit is a switching power supply that utilizes the characteristics of the choke current change of the output inductor. By changing the input power For the on and off states of the output inductor, the step-down regulation of the output voltage is realized; the step-down regulation is realized by completely relying on the characteristics of the output inductor to maintain the current constant. The speed is slow, the inductance conduction loss cannot be avoided, and the conversion efficiency is limited.

At the same time, the switching circuit keeps the output inductor in the two stages of charging and releasing energy respectively. Using the characteristics of the inductor to maintain the current direction and hinder the change of the current, the step-down adjustment of the rear-end output voltage is realized by controlling the current, which has a slow adjustment speed. The inductance conduction loss cannot be avoided, the conversion efficiency is limited, the inductance models are numerous, and the circuit structure is complicated. This is the weak point of prior art.

Utility model content

The purpose of this utility model is to provide and design a DC step-down regulation circuit structure to solve the above-mentioned technical problems in view of the above-mentioned defects in the prior art.

In order to achieve the above object, the technical scheme of the utility model is:

A DC step-down regulation circuit structure, comprising a switch circuit and a feedback regulation circuit; the switch circuit is connected to the feedback regulation circuit; the output end of the switch circuit is connected with an output capacitor;

The input terminal of the switch circuit is used for connecting the input voltage;

The feedback regulating circuit includes a voltage dividing power supply, a first operational amplifier and a second operational amplifier;

The positive input terminal of the first operational amplifier is connected with a first voltage divider circuit;

The inverting input terminal of the first operational amplifier is connected to the output capacitor;

A pull-down circuit is connected to the connection point between the positive input end of the first operational amplifier and the first voltage divider circuit;

The output end of the first operational amplifier is connected to the switch circuit;

The positive input end of the second operational amplifier is connected with a second voltage divider circuit;

The inverting input terminal of the second operational amplifier is connected with the inverting input terminal of the first operational amplifier;

The output terminal of the second operational amplifier is connected to the switch circuit;

The output terminal of the second operational amplifier is also connected to the pull-down circuit.

The voltage dividing power supply is respectively connected with the first voltage dividing circuit and the second voltage dividing circuit.

Further, the switch circuit includes a first MOS transistor and a second MOOS transistor;

The drain of the first MOS transistor is used to connect to the input voltage;

The gate of the first MOS transistor is connected to the output terminal of the second operational amplifier;

The source of the first MOS transistor is connected to the drain of the second MOS transistor through the first capacitor;

The source of the first MOS transistor is also connected to the source of the second MOS transistor through the second capacitor;

The source of the first MOS transistor is also grounded through the third capacitor;

The gate of the second MOS transistor is connected to the output terminal of the first operational amplifier.

Further, the first voltage dividing circuit includes a first resistor and a second resistor;

The voltage divider power supply is grounded through the first resistor and the second resistor in turn;

The connection point of the first resistor and the second resistor is connected to the positive input terminal of the first operational amplifier.

Further, the second voltage dividing circuit includes a third resistor and a fourth resistor;

The voltage divider power supply is grounded through the third resistor and the fourth resistor in turn;

Further, the pull-down circuit includes a fifth capacitor and a third MOS transistor;

The connection point between the positive input end of the first operational amplifier and the first voltage divider circuit is also connected to the source of the third MOS transistor through the fifth resistor;

The output terminal of the second operational amplifier is also connected to the gate of the third MOS transistor;

The drain of the third MOS transistor is grounded.

Further, the first end of the output capacitor is used as the output end of the power supply, and the second end of the output capacitor is grounded;

The connection point between the second capacitor and the source of the second MOS transistor is connected to the first end of the output capacitor;

The connection point between the inverting input terminal of the second operational amplifier and the inverting input terminal of the first operational amplifier is connected to the first terminal of the output capacitor.

Further, the voltage dividing power supply is respectively connected to the first voltage dividing circuit and the second voltage dividing circuit to generate different target voltages respectively.

Further, the ratio of the sum of the capacities of the first capacitor and the second capacitor in the circuit to the output capacitor is adjusted through the switch circuit to achieve the target output voltage.

Further, the first MOS transistor, the second MOS transistor and the third MOS transistor are all N-channel MOS transistors.

The voltage divider power supply outputs 12V voltage.

Switch circuit, the first MOS tube controls the charging of the input voltage to the first capacitor, the second capacitor, the third capacitor and the output capacitor, the second MOS tube controls whether the first capacitor is connected to the circuit, and adjusts the first capacitor and the second capacitor through the switch circuit The ratio of the sum of the capacities of the two capacitors in the circuit to the output capacitor is used to divide the voltage to achieve the target output voltage. The third capacitor is used as an energy storage capacitor to maintain the energy supply when the first MOS transistor is turned off. The output voltage is equal to the first capacitor and The ratio of the second capacitance is multiplied by the input voltage.

The feedback control circuit is composed of a first voltage divider circuit, a second voltage divider circuit, a first operational amplifier, a second operational amplifier pull-down circuit, and a voltage divider power supply. The target voltage generated by the first resistor and the second resistor divider is higher than the first resistor. The target voltage generated by the voltage division of the three resistors and the fourth resistor, the output voltage is first compared with the target voltage generated by the first resistor and the second resistor, when the output voltage is less than the target voltage generated by the first resistor and the second resistor, the first The operational amplifier outputs a high voltage, causing the second MOS tube to change from cut-off to on-state, and the first capacitor is connected to the circuit to change the proportion of the sum of the first capacitor and the second capacitor in the circuit. The first capacitor and the second capacitor The proportion of the sum of the capacitances increases, causing the output voltage to increase.

If the voltage still cannot meet the requirements at this time and trigger the target voltage divided by the third resistor and the fourth resistor, the first operational amplifier outputs a high voltage, the first MOS transistor is turned from off to on, the input voltage is connected to the circuit, and the second The first capacitor, the second capacitor, the third capacitor and the output capacitor are charged and the third MOS tube is turned from off to on, reducing the target voltage divided by the first resistor and the second resistor, so that the first operational amplifier is ahead of the second The operational amplifier outputs a low voltage, so the second MOS transistor changes from on to off before the first MOS transistor, delaying the charging time of the input voltage for the circuit, when the output voltage is higher than the target of the third resistor and the fourth resistor divider When the voltage is high, the first MOS transistor turns from on to off, the circuit completes charging, and the third capacitor supplies energy to maintain the voltage.

The output capacitor is responsible for the energy supply of the output voltage.

The beneficial effect of the utility model is that the technical scheme provided by the utility model directly adopts capacitor voltage division for step-down regulation without output inductance, and the regulation response speed is fast and the efficiency is high.

In addition, the design principle of the utility model is reliable, the structure is simple, and the utility model has a very wide application prospect.

It can be seen that, compared with the prior art, the utility model has substantive features and progress, and the beneficial effects of its implementation are also obvious.

Description of drawings

FIG. 1 is a structural block diagram of a DC step-down regulation circuit structure provided by this embodiment.

FIG. 2 is a circuit connection diagram of the DC step-down regulation circuit structure provided by this embodiment.

Among them, 1-switch circuit, 2-feedback adjustment circuit, 3-first voltage divider circuit, 4-second voltage divider circuit, 5-pull down circuit, M1-first operational amplifier, M2-second operational amplifier, Q1 -First MOS tube, Q2-second MOS tube, Q3-third MOS tube, C1-first capacitor, C2-second capacitor, C3-third capacitor, C4-fourth capacitor, R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor, VDD-divider power supply, Vin-output voltage, Vout-output voltage.

detailed description

The utility model will be described in detail below in conjunction with the accompanying drawings and through specific embodiments. The following examples are explanations of the utility model, but the utility model is not limited to the following embodiments.

As shown in Fig. 1 and Fig. 2, a DC step-down regulation circuit structure provided by this embodiment includes a switch circuit 1 and a feedback regulation circuit 2; the switch circuit 1 is connected to the feedback regulation circuit 2; the output terminal of the switch circuit 2 is connected to output capacitor C4;

The input terminal of the switch circuit 1 is used to connect the input voltage Vin;

The feedback regulating circuit 2 includes a voltage dividing power supply VDD, a first operational amplifier M1 and a second operational amplifier M2;

The positive input terminal of the first operational amplifier M1 is connected with a first voltage divider circuit 3;

The inverting input terminal of the first operational amplifier M1 is connected to the output capacitor C4;

A pull-down circuit 5 is connected to the connection point between the positive input end of the first operational amplifier M1 and the first voltage divider circuit 3;

The output end of the first operational amplifier M1 is connected to the switch circuit 1;

The positive input terminal of the second operational amplifier M2 is connected with a second voltage divider circuit 4;

The inverting input terminal of the second operational amplifier M2 is connected with the inverting input terminal of the first operational amplifier M1;

The output end of the second operational amplifier M2 is connected to the switch circuit 1;

The output terminal of the second operational amplifier M2 is also connected to the pull-down circuit 5 .

The voltage dividing power supply VDD is connected to the first voltage dividing circuit 2 and the second voltage dividing circuit 4 respectively.

The switch circuit 1 includes a first MOS transistor Q1 and a second MOS transistor Q2;

The drain of the first MOS transistor Q1 is used to connect to the input voltage Vin;

The gate of the first MOS transistor Q1 is connected to the output terminal of the second operational amplifier M2;

The source of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2 through the first capacitor C1;

The source of the first MOS transistor Q1 is also connected to the source of the second MOS transistor Q2 through the second capacitor C2;

The source of the first MOS transistor Q1 is also grounded through the third capacitor C3;

The gate of the second MOS transistor Q2 is connected to the output terminal of the first operational amplifier M1.

The first voltage dividing circuit 3 includes a first resistor R1 and a second resistor R2;

The 12V voltage output by the voltage divider power supply VDD is grounded sequentially through the first resistor R1 and the second resistor R2;

The connection point of the first resistor R1 and the second resistor R2 is connected to the positive input terminal of the first operational amplifier M1.

The second voltage dividing circuit 4 includes a third resistor R3 and a fourth resistor R4;

The voltage dividing power supply VDD is grounded sequentially through the third resistor R3 and the fourth resistor R4;

The pull-down circuit 5 includes a fifth capacitor R5 and a third MOS transistor Q3;

The connection point between the positive input terminal of the first operational amplifier M1 and the first voltage divider circuit 3 is also connected to the source of the third MOS transistor Q3 through the fifth resistor R5;

The output end of the second operational amplifier M2 is also connected to the gate of the third MOS transistor Q3;

The drain of the third MOS transistor Q3 is grounded.

The first end of the output capacitor C4 is used as the output end of the power supply, and the second end of the output capacitor C4 is grounded;

The connection point between the second capacitor C2 and the source of the second MOS transistor Q2 is connected to the first end of the output capacitor C4;

The connection point between the inverting input terminal of the second operational amplifier M2 and the inverting input terminal of the first operational amplifier M1 is connected to the first terminal of the output capacitor C4.

The voltage dividing power supply VDD is respectively connected to the first voltage dividing circuit 3 and the second voltage dividing circuit 4 to generate different target voltages respectively.

The ratio of the sum of the capacities of the first capacitor C1 and the second capacitor C2 in the circuit to the output capacitor C4 is adjusted through the switch circuit 1 to achieve the target output voltage.

The first MOS transistor Q1 , the second MOS transistor Q2 and the third MOS transistor Q3 are all N-channel MOS transistors.

The third pin of the first operational amplifier M1 is connected to 12V voltage, and the fourth pin of the first operational amplifier M1 is grounded;

The third pin of the second operational amplifier M2 is connected to 12V voltage, and the fourth pin of the second operational amplifier M2 is grounded;

The first MOS transistor Q1 of the switch circuit 1 controls the charging of the input voltage Vin to the first capacitor C1, the second capacitor C2, the third capacitor C3 and the output capacitor C4, and the second MOS transistor Q2 controls whether the first capacitor C1 is connected to the circuit, The ratio of the sum of the capacities of the first capacitor C1 and the second capacitor C2 in the circuit to the output capacitor C4 is adjusted through the switch circuit 1, and the target output voltage is achieved by using the proportional voltage division of the capacitors, and the third capacitor C3 is used as an energy storage capacitor to maintain the first MOS The energy supply when the tube Q1 is turned off, the output voltage Vout is equal to the proportion of the first capacitor C1 and the second capacitor C2 multiplied by the input voltage Vin.

Vout=Vin*(C1+C2)/(C1+C2+C4).

The feedback regulation circuit 2 is composed of a first voltage divider circuit 3, a second voltage divider circuit 4, a first operational amplifier M1, a second operational amplifier M2, a pull-down circuit 5 and a voltage divider power supply VDD, the first resistor R1 and the second resistor R1 The target voltage generated by the voltage division of R2 is higher than the target voltage generated by the voltage division of the third resistor R3 and the fourth resistor R4, the output voltage Vout is first compared with the target voltage generated by the first resistor R1 and the second resistor R2, when the output voltage Vout When it is lower than the target voltage generated by the first resistor R1 and the second resistor R2, the first operational amplifier M1 outputs a high voltage, causing the second MOS transistor Q2 to turn from off to on, and the first capacitor C1 is connected to the circuit to change the first capacitor The ratio of the sum of the capacities of C1 and the second capacitor C2 in the circuit increases, and the ratio of the sum of the first capacitor C1 and the second capacitor C2 increases, resulting in an increase of the output voltage.

If the voltage still cannot meet the requirements at this time and trigger the target voltage divided by the third resistor R3 and the fourth resistor R4, the first operational amplifier M1 outputs a high voltage, the first MOS transistor Q1 turns from off to on, and the input voltage Vin is connected to into the circuit, charge the first capacitor C1, the second capacitor C2, the third capacitor C3 and the output capacitor C4 and turn the third MOS transistor Q3 from off to on, reducing the voltage divided by the first resistor R1 and the second resistor R2 The target voltage makes the first operational amplifier M1 output a low voltage ahead of the second operational amplifier M2, so the second MOS transistor Q2 changes from on to off before the first MOS transistor Q1, delaying the charging time of the input voltage for the circuit, When the output voltage Vout is higher than the target voltage divided by the third resistor R3 and the fourth resistor R4, the first MOS transistor Q1 changes from on to off, and the circuit completes charging, and the third capacitor C3 supplies energy to maintain the voltage .

The first terminal of the output capacitor C4 is the output voltage terminal, which is responsible for the energy supply of the output voltage.

What is disclosed above is only the preferred embodiment of the present utility model, but the present utility model is not limited thereto, and any person skilled in the art can think of no creative changes, and some modifications made without departing from the principle of the present utility model. Improvement and retouching should all fall within the protection scope of the present utility model.

Claims (8)

1. a kind of DC decompression adjusts circuit structure, it is characterised in that including on-off circuit and feedback regulating circuit；On-off circuit Connected with feedback regulating circuit；Switching circuitry output is connected with output capacitance；

On-off circuit input is used to connect input voltage；

Feedback regulating circuit includes the first operational amplifier and the second operational amplifier；

The positive input of first operational amplifier is connected with the first bleeder circuit；

The reverse input end of first operational amplifier is connected with output capacitance；

The tie point of the positive input of first operational amplifier and the first bleeder circuit, which is connected with, drags down circuit；

The output end connecting valve circuit of first operational amplifier；

The positive input of second operational amplifier is connected with the second bleeder circuit；

The reverse input end of second operational amplifier is connected with the reverse input end of the first operational amplifier；

The output end connecting valve circuit of second operational amplifier；

The output end of second operational amplifier, which is also connected to, drags down circuit；

Feedback regulating circuit also includes dividing voltage supply, and the dividing voltage supply connects with the first bleeder circuit and the second bleeder circuit respectively Connect.

2. a kind of DC decompression regulation circuit structure according to claim 1, it is characterised in that the on-off circuit includes First metal-oxide-semiconductor and the 2nd MOOS pipes；

The drain electrode of first metal-oxide-semiconductor is used to connect input voltage；

The grid of first metal-oxide-semiconductor is connected to the output end of the second operational amplifier；

Drain electrode of the source electrode of first metal-oxide-semiconductor by the first capacitance connection to the second metal-oxide-semiconductor；

Source electrode of the source electrode of first metal-oxide-semiconductor also by the second capacitance connection to the second metal-oxide-semiconductor；

The source electrode of first metal-oxide-semiconductor also passes through the 3rd capacity earth；

The grid of second metal-oxide-semiconductor is connected with the output end of the first operational amplifier.

3. a kind of DC decompression regulation circuit structure according to claim 2, it is characterised in that the first bleeder circuit includes First resistor and second resistance；

Dividing voltage supply is grounded by first resistor and second resistance successively；

The tie point of first resistor and second resistance is connected to the positive input of the first operational amplifier.

A kind of 4. DC decompression regulation circuit structure according to Claims 2 or 3, it is characterised in that the second bleeder circuit Including 3rd resistor and the 4th resistance；

Dividing voltage supply passes through 3rd resistor and the 4th resistance eutral grounding successively；

The tie point of 3rd resistor and the 4th resistance is connected to the positive input of the second operational amplifier.

5. a kind of DC decompression regulation circuit structure according to claim 4, it is characterised in that dragging down circuit includes the 5th Electric capacity and the 3rd metal-oxide-semiconductor；

The positive input of first operational amplifier is also connected the 3rd MOS with the tie point of the first bleeder circuit by the 5th resistance The source electrode of pipe；

The output end of second operational amplifier is also connected to the grid of the 3rd metal-oxide-semiconductor；

The grounded drain of 3rd metal-oxide-semiconductor.

A kind of 6. DC decompression regulation circuit structure according to claim 5, it is characterised in that the first end of output capacitance As power output end, the second end of output capacitance is grounded；

The tie point of the source electrode of second electric capacity and the second metal-oxide-semiconductor is connected to the first end of output capacitance；

The reverse input end tie point of the reverse input end of second operational amplifier and the first operational amplifier is connected to output electricity The first end of appearance.

7. a kind of DC decompression regulation circuit structure according to claim 6, it is characterised in that dividing voltage supply is respectively with the One bleeder circuit and the connection of the second bleeder circuit, produce different target voltages respectively.

A kind of 8. DC decompression regulation circuit structure according to claim 7, it is characterised in that

The ratio that the first electric capacity and the second electric capacity capacity sum in circuit and output capacitance are adjusted by on-off circuit reaches Target output voltage.