[go: up one dir, main page]

CN206650065U - Semiconductor package body - Google Patents

Semiconductor package body Download PDF

Info

Publication number
CN206650065U
CN206650065U CN201621491854.5U CN201621491854U CN206650065U CN 206650065 U CN206650065 U CN 206650065U CN 201621491854 U CN201621491854 U CN 201621491854U CN 206650065 U CN206650065 U CN 206650065U
Authority
CN
China
Prior art keywords
substrate
groove
conductive coupling
coupling element
cap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201621491854.5U
Other languages
Chinese (zh)
Inventor
周建
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Italian Semiconductor International Co
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to CN201621491854.5U priority Critical patent/CN206650065U/en
Application granted granted Critical
Publication of CN206650065U publication Critical patent/CN206650065U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Packaging Frangible Articles (AREA)

Abstract

本实用新型涉及一种半导体封装体。该封装体的特征在于形成集成嵌入或集成在基底内的锁定机构的多个沟槽、多个通孔和非导电耦接元件。该封装体具有通过超声波塑料焊接而耦接至该非导电耦接元件的帽盖。该封装体保护晶粒免受外界环境或外部应力或两者影响。期望一种用于形成封装体以减少该封装体中的溢胶缺陷的方法。该封装体的制造包括:在基底中钻孔;在该基底中形成沟槽;在这些通孔和这些沟槽中形成非导电耦接元件以形成锁定机构;允许该非导电耦接元件硬化并固化;将裸片或晶粒耦接至该基底,并且将帽盖耦接至该非导电耦接元件,从而保护该裸片或晶粒免受外界环境或外部应力或两者影响。

The utility model relates to a semiconductor packaging body. The package is characterized by a plurality of grooves, a plurality of through holes and a non-conductive coupling element forming a locking mechanism integrally embedded or integrated in the substrate. The package has a cap coupled to the non-conductive coupling element by ultrasonic plastic welding. The package protects the die from the external environment or external stress or both. A method for forming a package to reduce overflow defects in the package is desired. Fabrication of the package includes: drilling holes in the substrate; forming trenches in the substrate; forming non-conductive coupling elements in the vias and the trenches to form a locking mechanism; allowing the non-conductive coupling elements to harden and curing; coupling a die or die to the substrate, and coupling a cap to the non-conductive coupling element, thereby protecting the die or die from the external environment or external stress, or both.

Description

半导体封装体semiconductor package

技术领域technical field

本披露涉及一种封装体,该封装体具有基底和通过形成在该基底中的多个耦接特征来耦接至该基底的帽盖。The present disclosure relates to a package having a base and a cap coupled to the base through coupling features formed in the base.

背景技术Background technique

封装体经常包括半导体裸片和基底,该基底提供在该基底与该半导体裸片上的触头之间的接口。该封装体可以包括封料,用于将该封装体的多个元件紧固到单个离散单元中。替代性地,封装体可以包括在该基底上将该裸片封闭在腔室中的帽盖。该帽盖由粘胶耦接至该基底。通常将该粘胶施加至该基底,并且然后将该帽盖放置在该粘胶上。然后允许该粘胶硬化并固化,从而将该帽盖耦接至该基底并且保护该裸片免受外界环境或外部应力或两者影响。Packages often include a semiconductor die and a substrate that provides an interface between the substrate and contacts on the semiconductor die. The package may include an encapsulant for securing the components of the package into a single discrete unit. Alternatively, the package may include a cap on the substrate enclosing the die in the chamber. The cap is coupled to the base by adhesive. Typically the glue is applied to the substrate, and the cap is then placed on the glue. The glue is then allowed to harden and cure, thereby coupling the cap to the substrate and protecting the die from the external environment or external stress or both.

遗憾的是,在将帽盖放置在已经被施加至基底以附接该帽盖的粘胶上时,该基底和该裸片变得易受溢胶影响。粘胶的溢出可能覆盖在该基底或该裸片上使该封装体以最大容量工作所必需的关键部件,如,覆盖接触焊盘。封装体的易碎性极大地增加了在制造工艺过程中处理这些封装体的困难。不使用粘胶增加了来自每个制造批次的可行封装体与半导体传感器的总百分比。Unfortunately, when the cap is placed over the adhesive that has been applied to the substrate to attach the cap, the substrate and the die become susceptible to adhesive spillage. Spills of adhesive may cover critical components on the substrate or the die that are necessary for the package to operate at maximum capacity, such as covering contact pads. The fragility of packages greatly increases the difficulty of handling these packages during the manufacturing process. Not using glue increases the overall percentage of viable packages and semiconductor sensors from each manufacturing lot.

实用新型内容Utility model content

一个或多个实施例提供了一种能够采用单一布局管理不同应用方案的布置。One or more embodiments provide an arrangement capable of managing different application scenarios with a single layout.

一个或多个实施例可以涉及一种包括该驱动器电路的对应装置(例如用于汽车领域的装置,例如lambda加热器)。One or more embodiments may relate to a corresponding device (such as a device for the automotive field, such as a lambda heater) comprising the driver circuit.

一个或多个实施例可以提供一种能够驱动所有各种可能配置(例如N高压侧,P高压侧,N低压侧)的电路,具有用于宽广全领域应用方案的能力。One or more embodiments may provide a circuit capable of driving all possible configurations (eg, N high side, P high side, N low side), with capabilities for a wide range of application scenarios.

与具有驱动外部部件的有限可能性的解决方案相反(例如驱动在高压侧或低压侧配置中外部NMOS,具有用于PMOS驱动的不同电路),一个或多个实施例使其能够采用单一布局驱动N型或P型MOSFETs,导致电压调节回路导通外部MOS的情形。Contrary to solutions with limited possibilities to drive external components (such as driving an external NMOS in a high-side or low-side configuration, with a different circuit for PMOS driving), one or more embodiments make it possible to drive with a single layout N-type or P-type MOSFETs, resulting in a situation where the voltage regulation loop turns on the external MOS.

一个或多个实施例可以因此能够驱动外部部件(例如MOSFETs,简称MOS)的各种(名义上全部)可能配置。One or more embodiments may thus be able to drive various (nominally all) possible configurations of external components such as MOSFETs (MOS for short).

一个或多个实施例可以通过采用可以与各种现有应用方案兼容并且由未来可能配置预期的(预)驱动器布局而免除现有解决方案的限制。One or more embodiments may avoid the limitations of existing solutions by employing a (pre-)driver layout that is compatible with various existing application solutions and anticipated by future possible configurations.

一个或多个实施例可以允许节省硅面积,使用少量管脚并且增加电路灵活性。One or more embodiments may allow for saving silicon area, using fewer pins, and increasing circuit flexibility.

一个或多个实施例可以包括用于例如耦合至外部部件诸如MOS的栅极和源极的两个输出端子或管脚。One or more embodiments may include two output terminals or pins for, for example, coupling to external components such as gate and source of a MOS.

在一个或多个实施例中一个管脚可以耦合至外部NMOS的栅极或者外部PMOS的源极,而另一个管脚耦合至外部NMOS的源极或者外部PMOS的栅极。In one or more embodiments one pin may be coupled to the gate of the external NMOS or the source of the external PMOS, while the other pin is coupled to the source of the external NMOS or the gate of the external PMOS.

根据一个方面,提供一种半导体封装体,包括:支撑基底,所述支撑基底具有第一表面和第二表面;多个非导电耦接元件,所述多个非导电耦接元件嵌入在所述基底中,所述非导电耦接元件包括:第一部分,所述第一部分具有顶表面,所述顶表面与所述基底的顶表面基本上共面,所述第一部分延伸到所述基底中;以及第二部分,所述第二部分从所述第一部分延伸穿过所述基底至所述基底的所述第二表面;第一支撑区域,所述第一支撑区域在所述基底的所述第一表面上在两个非导电耦接元件之间;第一裸片,所述第一裸片耦接至所述基底的所述第一支撑区域在所述两个非导电耦接元件之间;以及帽盖,所述帽盖耦接至所述非导电耦接元件,所述帽盖形成围绕所述第一裸片的腔室。According to one aspect, there is provided a semiconductor package comprising: a support base having a first surface and a second surface; a plurality of non-conductive coupling elements embedded in the In the substrate, the non-conductive coupling element includes: a first portion having a top surface substantially coplanar with the top surface of the substrate, the first portion extending into the substrate; and a second portion extending from the first portion through the base to the second surface of the base; a first support area on the base of the base between two non-conductive coupling elements on the first surface; a first die coupled to the first support region of the substrate between the two non-conductive coupling elements a space; and a cap coupled to the non-conductive coupling element, the cap forming a chamber surrounding the first die.

附图说明Description of drawings

在附图中,完全相同的参考标号标识相似的元件或动作,除非上下文另有指明。附图中元件的大小和相对位置不一定按比例绘制。In the drawings, identical reference numbers identify similar elements or acts, unless context dictates otherwise. The size and relative positions of elements in the drawings are not necessarily drawn to scale.

图1是半导体封装体的实施例的俯视平面图;1 is a top plan view of an embodiment of a semiconductor package;

图2是沿图1的封装体的线2-2截取的横截面视图;2 is a cross-sectional view taken along line 2-2 of the package of FIG. 1;

图3是沿图4中的封装体的线3-3截取的半导体封装体的替代性实施例的横截面视图;3 is a cross-sectional view of an alternative embodiment of a semiconductor package taken along line 3-3 of the package in FIG. 4;

图4是沿图3的半导体封装体的替代性实施例的线4-4截取的俯视平面图;4 is a top plan view taken along line 4-4 of the alternate embodiment of the semiconductor package of FIG. 3;

图5是封装体的替代性实施例的横截面视图;Figure 5 is a cross-sectional view of an alternative embodiment of a package;

图6是封装体的替代性实施例的横截面视图;6 is a cross-sectional view of an alternative embodiment of a package;

图7是针对图6的半导体封装体在附接帽盖之前的基底的替代性实施例的俯视平面图;7 is a top plan view of an alternative embodiment of a substrate for the semiconductor package of FIG. 6 prior to attachment of a cap;

图8至图18是根据所披露的实施例的封装体制造工艺的连续步骤的横截面和俯视平面图;8-18 are cross-sectional and top plan views of successive steps in a package fabrication process according to disclosed embodiments;

图19是根据针对图8至图18示出和描述的方法来制成的最终封装体的横截面视图;Figure 19 is a cross-sectional view of the final package made according to the method shown and described with respect to Figures 8-18;

图20至图21是在根据所披露的实施例的封装体制造工艺的连续步骤处封装体的替代性实施例的横截面视图;并且20-21 are cross-sectional views of an alternative embodiment of a package at successive steps in a package manufacturing process according to disclosed embodiments; and

图22是根据图20至图21的实施例的已完成封装体的横截面视图。22 is a cross-sectional view of a completed package according to the embodiment of FIGS. 20-21 .

具体实施方式detailed description

在以下描述中,阐明了某些具体细节以便提供对本披露的各个实施例的透彻了解。然而,本领域技术人员将理解的是,可以在没有这些特定细节的情况下实践本披露。在其他实例中,与电子部件和制造技术相关联的公知结构尚未被详细描述从而避免不必要地使本披露的实施例的描述变得模糊。In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

除非上下文另有要求,否则贯穿说明书和所附权利要求书,“包括(comprise)”一词及其多种变体(如,“包括(comprises)”和“包括(comprising)”)将以一种开放式的和包含性的意义来进行解释,也就是作为“包括,但不限于(including,but not limited to)”。Throughout the specification and appended claims, unless the context requires otherwise, the word "comprise" and its variations (eg, "comprises" and "comprising") will be used with a It should be interpreted in an open and inclusive sense, that is, as "including, but not limited to (including, but not limited to)".

对序数(如,第一、第二和第三)的使用不一定暗示顺序的排名意义,而是可以仅在动作或结构的多个实例之间进行区分。The use of ordinal numbers (eg, first, second, and third) does not necessarily imply a rank sense of order, but may merely distinguish between multiple instances of an action or structure.

贯穿本说明书对“一个实施例”或“实施例”的引用意味着结合该实施例所描述的具体特征、结构、或特性包括在至少一个实施例中。因而,贯穿本说明书,短语“在一个实施例中”或“在实施例中”在不同场合中的出现并不一定都是指相同的实施例。此外,在一个或多个实施例中,可以以任何适当的方式来组合特定特征、结构或特性。Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, throughout this specification, appearances of the phrase "in one embodiment" or "in an embodiment" in different instances do not necessarily all refer to the same embodiment. Furthermore, particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

如在本说明书和所附的权利要求书中所使用的,单数形式的“一种”、“一个”以及“该”包括复数对象,除非内容另外明确指明。还应注意,术语“或者”总体上所使用的意义包括“和/或”,除非内容另外明确指明。As used in this specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and/or" unless the content clearly dictates otherwise.

图1和图2涉及封装体38的一个实施例,该封装体包括基底40、非导电耦接元件42、帽盖44、裸片46和腔室48。裸片46可以是用于测量任何所需量的任何半导体传感器。FIGS. 1 and 2 relate to one embodiment of a package 38 that includes a substrate 40 , a non-conductive coupling element 42 , a cap 44 , a die 46 and a cavity 48 . Die 46 may be any semiconductor sensor for measuring any desired quantity.

在这个实施例中,基底40在制造过程中被安置在封装体38的底部作为基础层。基底40具有耦接至基底40的第一表面的裸片46。裸片46电性地且物理地耦接至支撑区域41处的基底40。支撑区域41可以具有任何形状或大小。基底40包含用于将裸片46电连接至封装体38之外的电路的电连接件和部件。这些电连接件或部件可以通过导电裸片附接膜、导电线、焊接线、导电焊盘、其组合的公知技术或半导体行业已知的任何其他技术来形成。基底40还具有形成在基底40的孔和沟槽中的非导电耦接元件42,如,塑料、聚合物、电介质材料、或任何其他绝缘或非导电材料。非导电耦接元件42形成在基底40中并且被允许在将帽盖44耦接至封装体之前在基底40内硬化并固化。非导电耦接元件42包围支撑区域41。在基底40中的非导电耦接元件42允许将帽盖44直接耦接至非导电耦接元件42,从而避免使用粘胶来将帽盖44耦接至基底40以形成封装体。帽盖44可以通过超声波塑料焊接、热处理、或半导体行业已知的在不使用粘胶的情况下用于两个聚合物的任何其他附接或耦接技术来耦接至非导电耦接元件42。帽盖44在裸片46周围形成腔室48,从而保护裸片46免于非期望地曝露在外界环境、外部应力或两者中。利用已经在基底40中形成和固化的非导电耦接元件42来附接帽盖44允许制造商避免使用粘胶。进而,避免任何可能的粘胶溢出到曝露在基底40或裸片46上的电连接件和部件上。In this embodiment, substrate 40 is disposed on the bottom of package body 38 as a base layer during fabrication. Substrate 40 has die 46 coupled to a first surface of substrate 40 . Die 46 is electrically and physically coupled to substrate 40 at support region 41 . The support area 41 may have any shape or size. Substrate 40 contains electrical connections and features for electrically connecting die 46 to circuitry outside package 38 . These electrical connections or features may be formed by known techniques of conductive die attach films, conductive lines, bond lines, conductive pads, combinations thereof, or any other technique known in the semiconductor industry. Substrate 40 also has non-conductive coupling elements 42 , such as plastic, polymer, dielectric material, or any other insulating or non-conductive material, formed in the holes and trenches of substrate 40 . The non-conductive coupling element 42 is formed in the substrate 40 and is allowed to harden and cure within the substrate 40 prior to coupling the cap 44 to the package. The non-conductive coupling element 42 surrounds the support region 41 . The non-conductive coupling element 42 in the substrate 40 allows the cap 44 to be directly coupled to the non-conductive coupling element 42, thereby avoiding the use of glue to couple the cap 44 to the substrate 40 to form the package. Cap 44 may be coupled to non-conductive coupling element 42 by ultrasonic plastic welding, heat treatment, or any other attachment or coupling technique known in the semiconductor industry for two polymers without the use of glue. . Cap 44 forms cavity 48 around die 46 , protecting die 46 from undesired exposure to the ambient environment, external stress, or both. Attaching the cap 44 with the non-conductive coupling element 42 already formed and cured in the substrate 40 allows the manufacturer to avoid the use of glue. Further, any possible spillage of adhesive onto electrical connections and components exposed on substrate 40 or die 46 is avoided.

图3和图4涉及封装体59的替代性实施例,该封装体包括基底64、非导电耦接元件42、具有壁62的帽盖52、两个裸片54、56以及两个腔室58、60。这两个裸片54、56可以是用于测量任何所需量的任何半导体传感器。3 and 4 relate to an alternative embodiment of a package 59 comprising a substrate 64, a non-conductive coupling element 42, a cap 52 with walls 62, two dies 54, 56 and two cavities 58. , 60. The two dies 54, 56 may be any semiconductor sensors for measuring any desired quantity.

在这个实施例中,基底64在制造过程中被安置在封装体59的底部作为基础层。基底64具有耦接至基底64的第一表面的两个晶粒54、56。晶粒54、56电性地且物理地耦接至基底64。基底64包含用于使晶粒54、56对外界环境可电性地获得所需的电连接件和部件。如在其他实施例中,这些电连接件和部件可以通过导电裸片附接膜、导电线、导电焊盘、或半导体行业已知的任何其他技术来形成。基底64还具有形成在基底64的孔和沟槽中的非导电耦接元件42,如,塑料、聚合物、电介质材料、或任何其他绝缘材料。在将帽盖52耦接至封装体之前已经允许非导电耦接元件42在基底64内硬化并固化。在基底中的非导电耦接元件42允许将帽盖52直接耦接至非导电耦接元件42,从而避免使用粘胶来将帽盖52耦接至基底64。帽盖52可以通过超声波塑料焊接或半导体行业已知的任何其他技术来耦接至非导电耦接元件42。帽盖52在这两个裸片54、56各自周围形成一个腔室58、60,从而保护晶粒54、56免受外界环境、外部应力或两者影响。利用已经在基底64中形成并固化的非导电耦接元件42来附接帽盖52允许制造商避免使用粘胶,并且避免任何可能的粘胶溢出到曝露在基底64或晶粒54、56上的电连接件和部件上。此外,利用已经在基底64中形成并固化的非导电耦接元件42来附接帽盖52允许将任何数量的半导体晶粒54、56快速并容易地封装在一起,从而制造保护单个半导体裸片、多个半导体晶粒、单个电子器件、或多个电子器件的封装体。In this embodiment, substrate 64 is placed on the bottom of package 59 as a base layer during fabrication. Substrate 64 has two dies 54 , 56 coupled to a first surface of substrate 64 . Dies 54 , 56 are electrically and physically coupled to substrate 64 . Substrate 64 contains the electrical connections and components needed to make dies 54, 56 electrically accessible to the external environment. As in other embodiments, these electrical connections and features may be formed by conductive die attach films, conductive lines, conductive pads, or any other technique known in the semiconductor industry. Substrate 64 also has non-conductive coupling elements 42 , such as plastic, polymer, dielectric material, or any other insulating material, formed in the holes and trenches of substrate 64 . The non-conductive coupling element 42 has been allowed to harden and cure within the substrate 64 prior to coupling the cap 52 to the package. The non-conductive coupling element 42 in the base allows for direct coupling of the cap 52 to the non-conductive coupling element 42 , thereby avoiding the use of glue to couple the cap 52 to the base 64 . Cap 52 may be coupled to non-conductive coupling element 42 by ultrasonic plastic welding or any other technique known in the semiconductor industry. The cap 52 forms a cavity 58 , 60 around each of the two die 54 , 56 , thereby protecting the die 54 , 56 from the external environment, external stress, or both. Utilizing the non-conductive coupling element 42 already formed and cured in the substrate 64 to attach the cap 52 allows the manufacturer to avoid the use of glue, and avoid any potential spillage of the glue onto the substrate 64 or the die 54, 56 exposed on electrical connections and components. Furthermore, attaching the cap 52 with the non-conductive coupling element 42 already formed and cured in the substrate 64 allows any number of semiconductor die 54, 56 to be packaged together quickly and easily, thereby fabricating a protective single semiconductor die. , multiple semiconductor dies, a single electronic device, or a package of multiple electronic devices.

图5涉及如图3和图4的封装体69的类似替代性实施例。封装体的这个替代性实施例包括基底64、非导电耦接元件42、具有壁和两个孔68的帽盖70、两个裸片72、74以及两个腔室58、60。这两个裸片72、74可以是用于测量任何所需量的任何半导体传感器或电子器件。FIG. 5 relates to a similar alternative embodiment of the package 69 as in FIGS. 3 and 4 . This alternative embodiment of the package includes a substrate 64 , a non-conductive coupling element 42 , a cap 70 with walls and two holes 68 , two dies 72 , 74 and two chambers 58 , 60 . The two die 72, 74 may be any semiconductor sensor or electronic device for measuring any desired quantity.

封装体69的这个替代性实施例类似于图3和图4,唯一的区别是在帽盖70中的这两个孔68。在帽盖70中的这两个孔68允许需要被曝露于外界环境并且被保护免受外部应力影响的接近度传感器、气体传感器和其他类似的半导体传感器、晶粒或电子器件。同样,通过利用非导电耦接元件将帽盖附接到基底上能够制造出具有任何数量的晶粒、任何数量的腔室和帽盖中的任何数量的孔的任何数量的实施例以及任何其他类似替代性实施例。例如,替代性实施例可以具有三个裸片、三个腔室以及帽盖,该帽盖具有将仅一个腔室和一个裸片曝露于外界环境的单个孔,而其他裸片保持在密封腔室中作为基准裸片。此外,替代性实施例可以具有单个裸片、单个腔室以及帽盖,该帽盖具有将该腔室和该裸片曝露于外界环境的单个孔。This alternative embodiment of the package 69 is similar to FIGS. 3 and 4 , the only difference being the two holes 68 in the cap 70 . These two holes 68 in the cap 70 allow for proximity sensors, gas sensors and other similar semiconductor sensors, die or electronics that need to be exposed to the external environment and protected from external stresses. Likewise, any number of embodiments with any number of dies, any number of cavities, and any number of holes in the cap can be fabricated by attaching the cap to the substrate using non-conductive coupling elements, as well as any other Similar alternative embodiment. For example, an alternative embodiment may have three dies, three chambers, and a cap with a single hole exposing only one chamber and one die to the external environment, while the other dies remain in the sealed chamber. chamber as a reference die. Furthermore, alternative embodiments may have a single die, a single chamber, and a cap with a single aperture exposing the chamber and the die to the external environment.

在一个实施例中,晶粒72和74是气体传感器。孔口68将这些裸片曝露于外界空气。每个裸片72和74可以感测不同的气体,如,CO2、CO、CH4等。替代性地,一个裸片可以是保持密封在基准环境气体(如,氩气、氮气、或环境空气)中的基准裸片,其中没有孔口通入其腔室76,而另一个裸片经由通入其腔室76的孔68曝露于环境气体。In one embodiment, dies 72 and 74 are gas sensors. Apertures 68 expose the die to ambient air. Each die 72 and 74 can sense a different gas, eg, CO2, CO, CH4, etc. FIG. Alternatively, one die may be a reference die kept sealed in a reference ambient gas (e.g., argon, nitrogen, or ambient air) with no vents into its chamber 76, while the other die is The hole 68 opening into its chamber 76 is exposed to ambient gas.

图6和图7涉及如图1的封装体的类似替代性实施例。封装体的这个替代性实施例包括基底80、非导电耦接元件42、不具有壁的帽盖78、两个裸片82、84以及一个腔室76。图7示出了替代性实施例,其中在基底80中形成了多个方孔86来代替圆孔。Figures 6 and 7 relate to a similar alternative embodiment of the package as in Figure 1 . This alternative embodiment of the package includes a substrate 80 , a non-conductive coupling element 42 , a cap 78 without walls, two dies 82 , 84 and a cavity 76 . Figure 7 shows an alternative embodiment in which a plurality of square holes 86 are formed in the base 80 instead of round holes.

这个替代性实施例具有类似于图1的封装体,区别是在一个腔室76中的这两个晶粒82、84以及代替圆孔的方孔86。在该一个腔室76中的这两个裸片82、84允许在帽盖壁不一定要分离每个裸片82、84时以较少的材料制造多感测封装体。同样,通过利用非导电耦接元件将帽盖附接到基底上能够制造出如三个裸片、单个腔室和没有壁的帽盖的替代性实施例以及其他类似替代性实施例。此外,该多个通孔86中的这些孔可以具有任何期望的横截面形状。例如,该多个通孔中的这些孔可以是方形、八边形、矩形、圆形或任何其他横截面形状。同样,在替代性实施例中,该多个第二沟槽中的这些第二沟槽也可以与多个通孔对齐。This alternative embodiment has a package similar to that of FIG. 1 , except for the two dies 82, 84 in one cavity 76 and a square hole 86 instead of a round hole. The two dies 82 , 84 in the one chamber 76 allow the multi-sense package to be fabricated with less material when the cap wall does not have to separate each die 82 , 84 . Also, by attaching the cap to the substrate with a non-conductive coupling element, alternative embodiments such as three die, a single chamber, and a cap with no walls can be fabricated and other similar alternative embodiments. Furthermore, the holes in the plurality of through holes 86 may have any desired cross-sectional shape. For example, the holes of the plurality of through holes may be square, octagonal, rectangular, circular, or any other cross-sectional shape. Also, in alternative embodiments, the second trenches of the plurality of second trenches may also be aligned with the plurality of via holes.

图8至图19展示了制造封装体89的步骤。图8是基底88的侧视图,并且图9是图8的俯视平面图。基底88具有第一表面89和第二表面91。基底88可以是印刷电路板(PCB)、晶片、薄硅片、二氧化硅、氧化铝、或半导体行业已知的任何这类基底材料。基底88包括需要形成将电部件耦接至基底88的电连接件的电连接件和部件。在附图中没有提供这些电连接件和部件以避免混淆。8 to 19 illustrate the steps of manufacturing the package 89 . FIG. 8 is a side view of substrate 88 and FIG. 9 is a top plan view of FIG. 8 . Substrate 88 has a first surface 89 and a second surface 91 . Substrate 88 may be a printed circuit board (PCB), wafer, thin silicon wafer, silicon dioxide, alumina, or any such substrate material known in the semiconductor industry. Substrate 88 includes the electrical connections and components needed to form the electrical connections that couple the electrical components to substrate 88 . These electrical connections and components are not provided in the figures to avoid confusion.

图10是基底88的横截面侧视图,该基底具有多个通孔90,该多个通孔已经形成从第一表面穿过基底88至第二表面或者形成在基底88中,并且图11是图10的俯视平面图。10 is a cross-sectional side view of a substrate 88 having a plurality of through holes 90 that have been formed through or in the substrate 88 from a first surface to a second surface, and FIG. 11 is Figure 10 Top plan view.

在一个实施例中,在基底中钻这些孔90以在将非导电耦接元件96(图15)放置或形成在通孔90和沟槽92、94中时创建锁定机构。可以通过任何可接受的技术形成这些通孔90,例如,用掩膜蚀刻、激光切割、机械钻孔、穿孔、或用于形成完全穿过基底的孔的许多已知方式的任何方法。In one embodiment, these holes 90 are drilled in the substrate to create a locking mechanism when a non-conductive coupling element 96 ( FIG. 15 ) is placed or formed in the through holes 90 and grooves 92 , 94 . These vias 90 may be formed by any acceptable technique, eg, masked etching, laser cutting, mechanical drilling, punching, or any of the many known ways for forming holes completely through a substrate.

形成在基底88中的这些通孔90充当锁定机构,并且非导电耦接元件96形成或放置在孔90和沟槽92、94中,这与仅将非导电耦接元件96形成在基底88中的沟槽内并且不存在通孔的情况相比允许了封装体的更大结构完整性。换言之,这允许使帽盖更紧固地耦接至封装体,从而减少了帽盖在曝露于外界环境、外部应力或两者时与封装体分离的可能性。These through-holes 90 formed in the base 88 act as a locking mechanism, and a non-conductive coupling element 96 is formed or placed in the holes 90 and grooves 92, 94, as opposed to forming only the non-conductive coupling element 96 in the base 88. This allows for greater structural integrity of the package than would be the case within the trench and the absence of vias. In other words, this allows for a more secure coupling of the cap to the package, thereby reducing the likelihood of the cap separating from the package when exposed to the external environment, external stress, or both.

图12是在基底88的第一表面89中的多个第一沟槽92的俯视平面图。该多个第一沟槽92形成在该多个通孔90的顶部上方或顶部上。该多个第一沟槽92中的每个第一沟槽与该多个通孔90中的一定数量的孔对齐。同样,该多个第一沟槽92中的每个第一沟槽基本上平行于该多个第一沟槽92中的其他第一沟槽。该多个通孔90和该多个第一沟槽92形成多个连续的T形孔97,该多个连续的T形孔为帽盖102创建非导电耦接元件96锁定机构(图14、图15和图19)。这些T形孔97允许使帽盖102更紧固地耦接至封装体,从而减少了帽盖在曝露于外界环境、或外部应力或两者时与封装体分离的可能性。FIG. 12 is a top plan view of the plurality of first trenches 92 in the first surface 89 of the substrate 88 . The plurality of first trenches 92 are formed over or on tops of the plurality of via holes 90 . Each first groove of the plurality of first grooves 92 is aligned with a certain number of holes of the plurality of through holes 90 . Likewise, each first groove of the plurality of first grooves 92 is substantially parallel to other first grooves of the plurality of first grooves 92 . The plurality of through holes 90 and the plurality of first grooves 92 form a plurality of continuous T-shaped holes 97 that create a non-conductive coupling element 96 locking mechanism for the cap 102 ( FIG. 14 , Figure 15 and Figure 19). These T-shaped holes 97 allow for a more secure coupling of the cap 102 to the package, thereby reducing the likelihood of the cap separating from the package when exposed to the external environment, or external stress, or both.

图13是横向于或基本上垂直于该多个第一沟槽92形成的多个第二沟槽94的俯视平面图。该多个第二沟槽94没有与该多个通孔90中的一定数量的孔对齐。但是该多个第二沟槽94中的每个第二沟槽可以与该多个通孔90中的至少一个通孔重叠。FIG. 13 is a top plan view of a plurality of second trenches 94 formed transversely or substantially perpendicular to the plurality of first trenches 92 . The plurality of second trenches 94 are not aligned with a certain number of the plurality of through holes 90 . But each second trench of the plurality of second trenches 94 may overlap at least one of the plurality of vias 90 .

在这个实施例中,该多个第一沟槽92和该多个第二沟槽94形成为支撑帽盖102并且允许将晶粒98、100密封在分离的腔室中(图19)。该多个第二沟槽94中的这些第二沟槽可以与对齐这些第一沟槽92的这些通孔中的至少一个通孔重叠。可以通过铣削、蚀刻或半导体行业已知的其他技术来形成该多个第一沟槽92和该多个第二沟槽94。同样,该多个第一沟槽92和该多个第二沟槽94形成第一支撑区域93和第二支撑区域95。该多个第一沟槽92和该多个第二沟槽94与该多个通孔90结合形成多个通道和多个T形孔97,这些通道和这些T形孔允许非导电耦接元件96形成贯穿整个基底88。第一支撑区域93定位在这些非导电耦接元件96中的两个非导电耦接元件之间,并且第二支撑区域95定位在这两个非导电耦接元件96中围绕该第一支撑区域93的一个非导电耦接元件与另一个非导电耦接元件96之间。利用在基底88的边缘上或者顺沿该基底的边缘的沟槽92、94允许将帽盖102耦接至基底88、允许封装体结构稳固、并且允许晶粒98、100密闭在外界环境之外、被保护免受外部应力或两者影响。In this embodiment, the plurality of first trenches 92 and the plurality of second trenches 94 are formed to support the cap 102 and allow sealing of the die 98, 100 in separate chambers (FIG. 19). The second grooves of the plurality of second grooves 94 may overlap at least one of the through holes aligned with the first grooves 92 . The plurality of first trenches 92 and the plurality of second trenches 94 may be formed by milling, etching, or other techniques known in the semiconductor industry. Likewise, the plurality of first grooves 92 and the plurality of second grooves 94 form a first support region 93 and a second support region 95 . The plurality of first grooves 92 and the plurality of second grooves 94 combine with the plurality of vias 90 to form a plurality of channels and a plurality of T-shaped holes 97 that allow for non-conductive coupling elements 96 is formed throughout the entire base 88 . A first support region 93 is positioned between two of the non-conductive coupling elements 96 and a second support region 95 is positioned around the first support region in the two non-conductive coupling elements 96 between one non-conductive coupling element 93 and the other non-conductive coupling element 96 . Utilizing the trenches 92, 94 on or along the edge of the substrate 88 allows the cap 102 to be coupled to the substrate 88, allows the package to be structurally robust, and allows the die 98, 100 to be hermetically sealed from the external environment. , be protected from external stresses, or both.

图14是在已经形成了该多个通孔90、该多个第一沟槽92、和该多个第二沟槽94之后基底88的横截面侧视图。14 is a cross-sectional side view of substrate 88 after the plurality of vias 90 , the plurality of first trenches 92 , and the plurality of second trenches 94 have been formed.

图15是基底88的横截面侧视图,其中该多个通孔90、该多个第一沟槽92、和该多个第二沟槽94填充有非导电耦接元件96。15 is a cross-sectional side view of substrate 88 with the plurality of vias 90 , the plurality of first trenches 92 , and the plurality of second trenches 94 filled with non-conductive coupling elements 96 .

在这个实施例中,非导电耦接元件96形成在该多个通孔90、该多个第一沟槽92、和该多个第二沟槽94中以针对帽盖102形成集成支撑件、耦接区域和锁定机构。可以通过从侧边、顶部、底部、或以任何其他方式将非导电耦接元件注塑模制到这些沟槽和孔90、92、94中来将非导电耦接元件96放置在这些孔和沟槽中。替代性地,非导电耦接元件96可以预先并单独地形成并且然后被压缩到这些沟槽和这些孔90、92、94中,或者这些沟槽和这些孔可以通过半导体行业已知的任何其他技术来用非导电材料填充。同样,非导电耦接元件96可以是可以被喷射、压缩或使用半导体行业已知的方法以其他方式形成在位的塑料、聚合物、电介质材料、或任何其他绝缘材料。当非导电耦接元件96形成在位时,允许非导电耦接元件96硬化并固化。利用非导电耦接元件96来将帽盖102耦接至封装体中的基底88允许制造商避免使用粘胶,这减少了溢流到基底88上或到晶粒98、100上的可能性。In this embodiment, non-conductive coupling elements 96 are formed in the plurality of vias 90 , the plurality of first grooves 92 , and the plurality of second grooves 94 to form an integral support for the cap 102 , Coupling area and locking mechanism. The non-conductive coupling elements 96 may be placed in these grooves and holes 90, 92, 94 by injection molding them from the sides, top, bottom, or in any other manner. in the slot. Alternatively, non-conductive coupling elements 96 may be pre- and separately formed and then compressed into the trenches and holes 90, 92, 94, or the trenches and holes may be formed by any other method known in the semiconductor industry. technology to fill with non-conductive material. Likewise, the non-conductive coupling element 96 may be a plastic, polymer, dielectric material, or any other insulating material that may be sprayed, compressed, or otherwise formed into place using methods known in the semiconductor industry. When the non-conductive coupling element 96 is formed in place, the non-conductive coupling element 96 is allowed to harden and cure. Utilizing the non-conductive coupling element 96 to couple the cap 102 to the substrate 88 in the package allows the manufacturer to avoid the use of glue, which reduces the possibility of overflowing onto the substrate 88 or onto the die 98 , 100 .

图16是当该多个通孔90、该多个第一沟槽92、和该多个第二沟槽94填充有然后被允许硬化并固化的非导电耦接元件96时的基底88的俯视平面图。16 is a top view of substrate 88 when the plurality of vias 90, the plurality of first trenches 92, and the plurality of second trenches 94 are filled with non-conductive coupling elements 96 that are then allowed to harden and cure. floor plan.

图17是耦接至基底88的第一表面89的两个裸片98、100的横截面侧视图。这两个裸片98、100电性地且物理地耦接至基底88的第一表面89,使得晶粒98、100可以从最终封装体之外被电性地访问。每个裸片98、100被放置在基底88的第一表面89上在由该多个通孔90、该多个第一沟槽92、和该多个第二沟槽94中的非导电耦接元件96包围或定界的第一支撑区域93或第二支撑区域95中。FIG. 17 is a cross-sectional side view of two dies 98 , 100 coupled to the first surface 89 of the substrate 88 . The two die 98, 100 are electrically and physically coupled to the first surface 89 of the substrate 88 such that the die 98, 100 can be electrically accessed from outside the final package. Each die 98 , 100 is placed on the first surface 89 of the substrate 88 by non-conductive couplings in the plurality of vias 90 , the plurality of first trenches 92 , and the plurality of second trenches 94 . In the first supporting region 93 or in the second supporting region 95 surrounded or delimited by the connection element 96 .

图18是耦接至基底88的两个裸片98、100的俯视平面图。这两个裸片98、100电性地且物理地耦接至基底88的第一表面,使得晶粒98、100可以从已完成封装体之外被电性地访问。每个裸片98、100被放置在基底88的第一表面上在由该多个通孔90、该多个第一沟槽92、和该多个第二沟槽94中的非导电耦接元件96包围或定界的第一支撑区域93或第二支撑区域95中。FIG. 18 is a top plan view of two dies 98 , 100 coupled to substrate 88 . The two die 98, 100 are electrically and physically coupled to the first surface of the substrate 88 such that the die 98, 100 can be electrically accessed from outside the completed package. Each die 98, 100 is placed on the first surface of the substrate 88 in a non-conductive coupling formed by the plurality of vias 90, the plurality of first trenches 92, and the plurality of second trenches 94. The element 96 surrounds or delimits either the first support region 93 or the second support region 95 .

图19是已完成封装体的替代性实施例的横截面侧视图。具有壁的帽盖102已经耦接至非导电耦接元件96,该非导电耦接元件已经在基底88内硬化并固化。Figure 19 is a cross-sectional side view of an alternative embodiment of a completed package. Cap 102 having walls has been coupled to non-conductive coupling element 96 which has been hardened and cured within base 88 .

在这个实施例中,已完成封装体89具有基底88,该基底被安置在封装体的底部作为基础层。基底88具有耦接至基底88的第一表面的两个裸片98、100。晶粒98、100电耦接至基底88。基底88包含用于使晶粒98、100对外界环境可电性地访问所需的电连接件和部件。这些电连接件和部件可以通过导电裸片附接膜、导电线、导电焊盘、其组合、或半导体行业已知的任何其他技术来形成。基底88还具有形成在基底88的孔90和沟槽92、94中的非导电耦接元件96,如,塑料、聚合物、电介质材料、或任何其他的绝缘材料。在将帽盖102耦接至封装体之前已经允许非导电耦接元件96在基底88内硬化并固化。在基底中的非导电耦接元件96允许将帽盖102直接耦接至非导电耦接元件96,从而避免使用粘胶来将帽盖102耦接至基底88。帽盖102在这两个裸片98、100各自周围形成一个腔室,从而保护晶粒98、102免受外界环境、外部应力或两者影响。利用已经在基底88中形成、硬化并固化的非导电耦接元件96来附接帽盖102允许制造商避免使用粘胶,并且避免任何可能的粘胶溢出到曝露在基底88或晶粒98、100上的电连接件和部件上。此外,利用已经在基底88中形成并固化的非导电耦接元件96来附接帽盖102允许将任何数量的半导体晶粒98、100快速并容易地封装在一起,从而制造保护单个裸片、多个晶粒、单个电子器件、和多个电子器件免受外界环境或外部应力影响的封装体。In this embodiment, the completed package 89 has a substrate 88 disposed on the bottom of the package as a base layer. Substrate 88 has two dies 98 , 100 coupled to a first surface of substrate 88 . Die 98 , 100 are electrically coupled to substrate 88 . Substrate 88 contains the electrical connections and components needed to make die 98, 100 electrically accessible to the external environment. These electrical connections and components may be formed by conductive die attach films, conductive lines, conductive pads, combinations thereof, or any other technique known in the semiconductor industry. Substrate 88 also has non-conductive coupling elements 96 , such as plastic, polymer, dielectric material, or any other insulating material, formed in holes 90 and trenches 92 , 94 of substrate 88 . The non-conductive coupling element 96 has been allowed to harden and cure within the substrate 88 prior to coupling the cap 102 to the package. The non-conductive coupling element 96 in the base allows the cap 102 to be coupled directly to the non-conductive coupling element 96 , thereby avoiding the use of glue to couple the cap 102 to the base 88 . The cap 102 forms a cavity around each of the two die 98, 100, thereby protecting the die 98, 102 from the external environment, external stress, or both. Attaching the cap 102 with the non-conductive coupling element 96 that has been formed, hardened and cured in the substrate 88 allows the manufacturer to avoid the use of glue and avoid any possible spillage of the glue onto the exposed substrate 88 or die 98, 100 on the electrical connections and components. In addition, attaching the cap 102 with the non-conductive coupling element 96 already formed and cured in the substrate 88 allows any number of semiconductor die 98, 100 to be packaged together quickly and easily, thereby fabricating protection for a single die, A package that protects multiple dies, single electronic devices, and multiple electronic devices from the external environment or external stress.

帽盖102和耦接元件96由可以通过不需要粘胶来形成紧密的整体结合构件的技术结合的材料制成。例如,这两者可以由可以彼此超声波焊接的聚合物制成。在放置在一起后,帽盖102和耦接元件96的接头经受使这两个构件彼此永久熔融的超声波焊接光束。可以使用其他技术,如加热该接头以将这两个构件熔化在一起、然后将其快速冷却以形成永久结合、激光焊接、或已知用于在没有粘胶的情况下使两个构件彼此附接的其他技术。可以彼此超声波焊接以形成气密密封、紧密永久结合的各种各样的塑料、其他材料和不同的聚合物在本领域是公知的,并且这些材料中的任何材料可以用于帽盖102和耦接构件96。Cap 102 and coupling element 96 are made of materials that can be bonded by techniques that do not require glue to form a tight unitary bonded member. For example, the two could be made of polymers that can be ultrasonically welded to each other. After being placed together, the joint of cap 102 and coupling element 96 is subjected to an ultrasonic welding beam which permanently fuses the two components to each other. Other techniques can be used such as heating the joint to melt the two components together and then rapidly cooling it to form a permanent bond, laser welding, or other techniques known to attach the two components to each other without glue. other technologies connected. A wide variety of plastics, other materials, and different polymers that can be ultrasonically welded to each other to form a hermetic seal, tight, permanent bond are known in the art, and any of these materials can be used for the cap 102 and coupling. connecting member 96.

图20是封装体的替代性实施例的横截面视图,该封装体包括具有多个I形孔103的基底104基础层。FIG. 20 is a cross-sectional view of an alternative embodiment of a package including a base layer of a substrate 104 having a plurality of I-shaped holes 103 .

图21是封装体的替代性实施例的横截面侧视图,该封装体包括具有填充有非导电耦接元件106的多个I形孔103的基底104基础层。该多个I形孔103由多个第一沟槽、多个第二沟槽、多个第三沟槽、多个第四沟槽和多个通孔组成。21 is a cross-sectional side view of an alternative embodiment of a package including a substrate 104 base layer with a plurality of I-shaped holes 103 filled with non-conductive coupling elements 106 . The plurality of I-shaped holes 103 are composed of a plurality of first grooves, a plurality of second grooves, a plurality of third grooves, a plurality of fourth grooves and a plurality of through holes.

在这个实施例中,在基底104的第一表面中已经形成了多个通孔和若干多个沟槽。然而,在基底104的第二表面上已经形成了若干多个沟槽。在基底104的第二表面上已经形成了与在基底104的第一表面上的该多个第一沟槽中的对应第一沟槽相反的多个第三沟槽。同样,在基底104的第二表面上已经形成了与在基底104的第一表面上的该多个第二沟槽中的对应第二沟槽相反的多个第四沟槽。这些多个第一、第二、第三、和第四沟槽用于将非导电耦接元件106进一步集成在基底104中并且用于形成更强的锁定机构。该多个第一沟槽和该多个第三沟槽与该多个通孔中的多个通孔对齐。该多个第二沟槽中的这些第二沟槽和该多个第四沟槽中的这些第四沟槽可以与对齐这些第一沟槽和这些第三沟槽的这些通孔中的至少一个通孔重叠。这是因为该多个第一、第二、第三、和第四沟槽以及该多个通孔形成多个连续的I形孔103。这些I形孔103允许非导电耦接元件106在基底104的第二表面上硬化并固化,从而创建与以上替代性实施例中讨论的T形孔97相比更强并更加集成的锁定机构。In this embodiment, a plurality of via holes and a plurality of trenches have been formed in the first surface of the substrate 104 . However, several trenches have been formed on the second surface of the substrate 104 . A plurality of third grooves opposite to corresponding first grooves of the plurality of first grooves on the first surface of the substrate 104 have been formed on the second surface of the substrate 104 . Likewise, a plurality of fourth grooves opposite to corresponding second grooves of the plurality of second grooves on the first surface of the substrate 104 have been formed on the second surface of the substrate 104 . These plurality of first, second, third, and fourth grooves are used to further integrate the non-conductive coupling element 106 in the base 104 and to form a stronger locking mechanism. The plurality of first trenches and the plurality of third trenches are aligned with a plurality of vias of the plurality of vias. The second grooves of the second grooves and the fourth grooves of the fourth grooves may be aligned with at least one of the via holes of the first grooves and the third grooves. One via overlaps. This is because the plurality of first, second, third, and fourth grooves and the plurality of through holes form a plurality of continuous I-shaped holes 103 . These I-shaped holes 103 allow the non-conductive coupling element 106 to harden and cure on the second surface of the substrate 104, thereby creating a stronger and more integrated locking mechanism than the T-shaped holes 97 discussed in the alternative embodiment above.

图22是已完成封装体91的替代性实施例的横截面侧视图,该已完成封装体包括耦接至非导电耦接元件106的帽盖108,该非导电耦接元件形成在基底104中的多个I形孔103中。22 is a cross-sectional side view of an alternative embodiment of a completed package 91 including a cap 108 coupled to a non-conductive coupling element 106 formed in a substrate 104 In the plurality of I-shaped holes 103.

以上所描述的各实施例可以被组合以提供进一步的实施例。在本说明书中所提及的和/或在申请资料表中所列出的所有美国专利、美国专利申请出版物、美国专利申请、国外专利、国外专利申请和非专利出版物都以其全文通过引用并入本文。如果有必要,可以对实施例的各方面进行修改,以采用各专利、申请和公开的概念来提供更进一步的实施例。The various embodiments described above may be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are adopted in their entirety Incorporated herein by reference. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various patents, applications and publications to provide yet further embodiments.

鉴于以上详细说明,可以对实施例做出这些和其他改变。总之,在以下权利要求书中,所使用的术语不应当被解释为将权利要求书局限于本说明书和权利要求书中所披露的特定实施例,而是应当被解释为包括所有可能的实施例、连同这些权利要求有权获得的等效物的整个范围。因此,权利要求书并不受本披露的限制。These and other changes can be made to the embodiments in light of the above detailed description. In conclusion, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments, Along with the full range of equivalents to which these claims are entitled. Accordingly, the claims are not limited by this disclosure.

Claims (12)

  1. A kind of 1. semiconductor package body, it is characterised in that including:
    Support substrate, the support substrate have first surface and second surface;
    Multiple non-conductive coupling elements, the multiple non-conductive coupling element are embedded in the substrate, the non-conductive coupling Element includes:
    Part I, the Part I have top surface, and the top surface and the top surface of the substrate are substantially coplanar, institute Part I is stated to extend in the substrate;And
    Part II, the Part II extend through the substrate to second table of the substrate from the Part I Face;
    First supporting zone, first supporting zone is on the first surface of the substrate in two non-conductive coupling members Between part;
    First nude film, first nude film are coupled to first supporting zone of the substrate in described two non-conductive couplings Between element;And
    Cap, the cap are coupled to the non-conductive coupling element, and the cap forms the chamber around first nude film.
  2. 2. semiconductor package body as claimed in claim 1, it is characterised in that further comprise:
    Second supporting zone, second supporting zone is on the first surface of the substrate in described two non-conductive members Between one of part and the 3rd non-conductive component;And
    Second nude film, second nude film are coupled to second supporting zone.
  3. 3. semiconductor package body as claimed in claim 2, it is characterised in that be coupled to the substrate first nude film and Second nude film is electrically coupled to the substrate.
  4. 4. semiconductor package body as claimed in claim 3, it is characterised in that further comprise the cap with wall, the cap Lid is coupled to the non-conductive coupling element to form first chamber and second chamber, and it is naked that the first chamber surrounds described first Piece, and the second chamber surrounds second nude film.
  5. 5. semiconductor package body as claimed in claim 1, it is characterised in that further comprise:
    Part III of the multiple non-conductive coupling element in the second surface of the substrate, each Part III with The corresponding Part I of the multiple non-conductive coupling element is opposite;And
    Multiple continuous non-conductive coupling elements of I shapes, the multiple continuous non-conductive coupling element of I shapes non-are led by the multiple The Part I of electric coupling element, the multiple non-conductive coupling element the Part II and these are non-conductive The Part III of coupling element is formed.
  6. A kind of 6. semiconductor package body, it is characterised in that including:
    Substrate, the substrate have first surface and second surface;
    Multiple through holes, the multiple through hole pass through the substrate;
    Multiple first grooves, for the multiple first groove in the first surface of the substrate, each first groove is basic Go up parallel to each other and alignd with a number of through hole in the multiple through hole;
    Multiple second grooves, for the multiple second groove in the first surface of the substrate, each second groove is horizontal In the multiple first groove and overlapping with least one through hole in the through hole;And
    Non-conducting material, the non-conducting material are positioned at the multiple through hole, the multiple first groove and the multiple In second groove.
  7. 7. semiconductor package body as claimed in claim 6, it is characterised in that the multiple first groove and the multiple through hole Form multiple continuous T-shaped holes.
  8. 8. semiconductor package body as claimed in claim 6, it is characterised in that further comprise:
    Multiple 3rd grooves, the multiple 3rd groove is in the second surface of the substrate, each 3rd groove and institute State a number of through hole alignment in multiple through holes.
  9. 9. semiconductor package body as claimed in claim 8, it is characterised in that the multiple first groove, the multiple through hole And the multiple 3rd groove forms multiple continuous I shapes holes.
  10. 10. semiconductor package body as claimed in claim 9, it is characterised in that further comprise the institute in the multiple I shapes hole State the non-conducting material in I shapes hole.
  11. 11. semiconductor package body as claimed in claim 10, it is characterised in that further comprise:
    Multiple 4th grooves, the multiple 4th groove is in the second surface of the substrate, each 4th channel lateral In the multiple 3rd groove and overlapping with least one through hole in the through hole.
  12. 12. semiconductor package body as claimed in claim 7, it is characterised in that further comprise
    Cap, the cap are coupled to the non-conducting material in the T-shaped hole and the multiple second groove;
    Supporting zone, the supporting zone is by two first grooves in the multiple first groove and the multiple second groove In two second grooves surround;And
    Nude film, the nude film are coupled to the supporting zone, and the nude film is electrically coupled to the supporting zone.
CN201621491854.5U 2016-12-30 2016-12-30 Semiconductor package body Active CN206650065U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201621491854.5U CN206650065U (en) 2016-12-30 2016-12-30 Semiconductor package body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201621491854.5U CN206650065U (en) 2016-12-30 2016-12-30 Semiconductor package body

Publications (1)

Publication Number Publication Date
CN206650065U true CN206650065U (en) 2017-11-17

Family

ID=60283175

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201621491854.5U Active CN206650065U (en) 2016-12-30 2016-12-30 Semiconductor package body

Country Status (1)

Country Link
CN (1) CN206650065U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019096797A (en) * 2017-11-27 2019-06-20 三菱電機株式会社 Semiconductor device and power conversion apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019096797A (en) * 2017-11-27 2019-06-20 三菱電機株式会社 Semiconductor device and power conversion apparatus

Similar Documents

Publication Publication Date Title
US10483133B2 (en) Method for fabricating a semiconductor chip panel
KR20110057252A (en) Laminated Quad Pre-Molded Component Packages, Systems Using the Same, and Methods of Manufacturing the Same
CN206650065U (en) Semiconductor package body
JP2021072329A (en) Power semiconductor device
CN108269765B (en) Semiconductor sensor package
TW201344994A (en) Semiconductor laser chip package with encapsulated recess molded on substrate and method for forming same
US7476811B2 (en) Semiconductor device and manufacturing method therefor
US7135768B2 (en) Hermetic seal
WO2023142539A1 (en) Cover plate, power module and electronic device
JPH047589B2 (en)
JP2014093451A (en) Manufacturing method for mold package
US6707151B2 (en) Semiconductor device
KR20160051145A (en) Sensor package and manufacturing method thereof
CN1881570A (en) Integrated circuit package encapsulating a hermetically sealed device
US10431514B2 (en) Semiconductor packages having dual encapsulation material
KR101364020B1 (en) Semiconductor package and the fabriation method thereof
JPH05267503A (en) Semiconductor device
JP5261851B2 (en) Manufacturing method of semiconductor device
CN101118861A (en) Chip package structure and method for manufacturing the same
CN211295087U (en) power module
TWI236716B (en) Window ball grid array semiconductor package with substrate having opening and method for fabricating the same
TWM567953U (en) Semiconductor package structure with spaced protrusions
US8552544B2 (en) Package structure
KR100362225B1 (en) electronic semiconductor module
KR100387395B1 (en) Plastic package having air-cavity and method of manufacturing the same

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20240812

Address after: Geneva, Switzerland

Patentee after: Italian Semiconductor International Co.

Country or region after: Netherlands

Address before: Singapore

Patentee before: STMicroelectronics S.A.

Country or region before: Singapore