CN206649376U - One kind is applied in the road server PCH configuration structures of purley platforms eight - Google Patents

Abstract

The utility model provides an eight-way server PCH configuration structure applied on the purley platform, including: a main board, four computing nodes and a back board are arranged on the main board; the four computing nodes are respectively connected to the back board, and the four computing nodes pass through the back board Mutual connection; BMC management module, storage module, and the first CPU are respectively connected to the PCH module, and the PCH module and the backplane are connected by USB protocol communication; the BMC management module is connected to the backplane through the PHY module; between the first CPU and the second CPU Using UPI protocol and PCIE protocol communication connection, the first CPU uses UPI protocol and PCIE protocol to connect and communicate with the backplane. The main board in the 8-way server system is designed with four computing nodes, which can be freely switched to 2, 4, 8 through switches. road.

Description

One kind is applied in the road server PCH configuration structures of purley platforms eight

Technical field

Server field is the utility model is related to, more particularly to one kind is applied and matched somebody with somebody in the road server PCH of purley platforms eight Put structure.

Background technology

The PCH for the Purley platforms compatibility that Intel is newly released is LBG (Lewiburg) series, except being opened with traditional PCH Outside machine and external I/O function, inside is also integrated with 10G networks can be directly by external I/O to interchanger, while also has QAT (Quick Assist Technology) function, data can be encrypted and accelerate to play the mesh to processor Reduction of Students' Study Load 's.The signal that new LBG interacts with CPU does not only have DMI, while also X16 PCIE3.0 and optional X8PCIE 3.0.This LBG compared with traditional PCH, itself also corresponds to a PCIE device in fact from the point of view of sample, and the FW of the PCIE device is equally existed In Flash and BIOS is in different regions.

In high-end server design, four calculate nodes realize the design of 8 road servers by backboard QPI interconnections.Often Individual calculate node has a PCH to be responsible for switching on and shutting down and just determined to external expansion IO, such PCH quantity by the quantity of calculate node It is fixed.When 8 tunnel systems are opened, it is only necessary to a PCH, can so cause the waste of PCH resources on other computing board, only 8 tunnels When being downgraded to 2 tunnel, the PCH of each calculate node can just make full use of.

The content of the invention

In order to overcome above-mentioned deficiency of the prior art, the utility model provides one kind and applied in the road of purley platforms eight clothes Business device PCH configuration structures, including：Mainboard, mainboard are provided with four calculate nodes and backboard；

Four calculate nodes are connected with backboard respectively, and four calculate nodes are connected with each other by backboard；

Calculate node includes：Support plate, support plate are provided with PHY modules, BMC management modules, PCH modules, storage module, and first CPU, the 2nd CPU, the first memory bar group, the second memory bar group；

BMC management modules, storage module, the first CPU are connected with PCH modules respectively, and PCH modules are assisted with backboard using USB View communication connection；

BMC management modules are connected by PHY modules with backboard；Between first CPU and the 2nd CPU using UPI agreements and PCIE protocol communications are connected, and the first CPU is assisted using UPI agreements and PCIE agreements and backboard connection communication, the 2nd CPU using UPI View and PCIE agreements and backboard connection communication, the first memory bar group are connected with the first CPU, and the second memory bar group connects with the 2nd CPU Connect.

Preferably, calculate node also includes：CPLD modules and for debugging calculate node internal module running status XDP debugging modules.

Preferably, connected between the first CPU and PCH modules using DMI agreements and PCIE protocol communications.

Preferably, storage module uses at least two SSD hard disks, and PCIE agreements are used between storage module and PCH modules Communication connection.

Preferably, BMC management modules use NCSI agreements, PCIE agreements, LPC agreements, usb protocol communication with PCH modules Connection.

Preferably, BMC management modules are connected with PHY modules using RGMII protocol communications, and PHY modules use with backboard SERDES mode data transfers.

Preferably, calculate node also includes：For the power module to power elements on overall calculation node；Power module Provided with P12V pins.

As can be seen from the above technical solutions, the utility model has advantages below：

Not only there is the PCH modules that the utility model is newly released based on Intel traditional PCH to be responsible for switching on and shutting down and external IO Function, while be internally integrated 10G networks and QAT functions, itself equipment equivalent to a PCIE, its FW exists and Flash In.Communicated by PCIE and CPU.Motherboard design in the utility model in 8 road server systems four calculates section Point, 2,4,8 tunnels freely can be switched to by switch.

Brief description of the drawings

In order to illustrate more clearly of the technical solution of the utility model, the required accompanying drawing used in description will be made below Simply introduce, it should be apparent that, drawings in the following description are only some embodiments of the utility model, for this area For those of ordinary skill, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.

Fig. 1 is to apply the overall schematic in the road server PCH configuration structures of purley platforms eight；

Fig. 2 is calculate node schematic diagram.

Embodiment

It is specific below in conjunction with this to enable the purpose of this utility model, feature, advantage more obvious and understandable Accompanying drawing in embodiment, the technical scheme in the utility model is clearly and completely described, it is clear that disclosed below Embodiment is only the utility model part of the embodiment, and not all embodiment.Based on the embodiment in this patent, ability All other embodiment that domain those of ordinary skill is obtained under the premise of creative work is not made, belong to this patent guarantor The scope of shield.

The utility model provides one kind and applied in the road server PCH configuration structures of purley platforms eight, such as Fig. 1 and Fig. 2 It is shown, including：Mainboard 13, mainboard 13 are provided with four calculate nodes 12 and backboard 11；

Four calculate nodes 12 are connected with backboard 11 respectively, and four calculate nodes 12 are connected with each other by backboard 11；

Calculate node 12 includes：Support plate, support plate are provided with PCH modules 1, BMC management modules 2, PHY modules 4, storage module The memory bar group 7 of 3, the first CPU5, the 2nd CPU6, first, the second memory bar group 8；

BMC management modules 2, storage module 3, the first CPU5 are connected with PCH modules 1 respectively, and PCH modules 1 are adopted with backboard 11 Communicated to connect with usb protocol；

BMC management modules 2 are connected by PHY modules 4 with backboard 11；Assisted between first CPU5 and the 2nd CPU6 using UPI View and the connection of PCIE protocol communications, the first CPU5 are adopted using UPI agreements and PCIE agreements and the connection communication of backboard 11, the 2nd CPU6 It is connected with UPI agreements and PCIE agreements and the connection communication of backboard 11, the first memory bar group 7 with the first CPU5, the second memory bar group 8 It is connected with the 2nd CPU6.

PCH (platform controller Hub) is the integrated south bridge of an intel company.Calculate node 12 is also wrapped Include：CPLD modules 9 and the XDP debugging modules 10 for debugging calculate node internal module running status.

Connected between first CPU5 and PCH modules 1 using DMI agreements and PCIE protocol communications.Storage module 3 is using at least Two SSD hard disks, connected between storage module 3 and PCH modules 1 using PCIE protocol communications.BMC management modules 2 and PCH modules 1 uses NCSI agreements, PCIE agreements, LPC agreements, usb protocol communication connection.BMC management modules 2 and PHY modules 4 use RGMII protocol communications connect, and PHY modules 4 use SERDES mode data transfers with backboard 11.Calculate node 12 also includes：With The power module 20 of power elements on to overall calculation node；Power module 20 is provided with P12V pins.

First memory bar group 7 includes at least one memory bar, and the second memory bar group 8 includes at least one memory bar.

In the utility model, not only there is traditional PCH to be responsible for switching on and shutting down and externally for the PCH modules 1 newly released based on Intel IO function, while be internally integrated 10G networks and QAT functions, itself equipment equivalent to a PCIE, its FW exist with In Flash.Communicated by PCIE and CPU.Four meters of motherboard design in the utility model in 8 road server systems Operator node, 2,4,8 tunnels freely can be switched to by switch.In the entire system, if user is it is desirable that 2 tunnels service Device, then by the shared signal of each calculate node of switch cutoff, make the work of each calculate node independence, so each meter The PCH modules of operator node are normal mode of operation.When user prepare open 8 road servers in, by switch make all meters Operator node shares signal communication, while the PCH modules of only first calculate node are responsible for the start sequential of whole system, then BIOS information is read to initialize the equipment of system.The PCH modules disabling of other three calculate nodes falls DMI functions, only EPO (Endpoint Only) pattern of PCH modules is operated in, is no longer responsible for starting shooting sequential and reads BIOS, only in start FW needed for loading 10G networks and QAT functions.So all PCH module resources can make full use of in the entire system, together When add the quantity of external I/O device, lift the performance of whole system.

UPI:Ultra Path Interconnect are the interconnect high-speed agreements between the how individual CPU of intel. PCIE:A kind of agreements of high-speed communication of Peripheral Component Interconnect Express.DMI:Direct Media Interface are that intel simplifies a kind of communication protocol that PCIE is done.RGMII ReducedGigabit Media A kind of network transmission protocols of Independent Interface.

SERDES SERializer (serializer)/DESerializer (deserializer) abbreviation is a kind of transmission means. CPLD modules are PLD.LPC：A kind of low speed transmissions agreements of Low Pin Count.NCSI：Network A kind of network transmission protocols of Controller Sideband Interface.BMC(Baseboard Management Controller, baseboard management controller).PCIe is the EBI of a new generation, and X16, X8 are to represent the two-way processing speed of slot Degree.I2C buses are used inside overall board.I2C buses (I2C bus, Inter-IC bus) are that a two two-way lines are continuous Bus, there is provided the communication line between integrated circuit (ICs).

Claims (7)

1. An eight-way server PCH configuration structure applied to the purley platform, is characterized in that it comprises: a main board, on which four computing nodes and a backplane are arranged; The four computing nodes are respectively connected to the backplane, and the four computing nodes are connected to each other through the backplane; The computing node includes: a carrier board with a PHY module, a BMC management module, a PCH module, a storage module, a first CPU, a second CPU, a first memory stick group, and a second memory stick group; The BMC management module, the storage module, and the first CPU are respectively connected to the PCH module, and the PCH module and the backplane are connected by USB protocol; The BMC management module is connected to the backplane through the PHY module; the first CPU and the second CPU use the UPI protocol and the PCIE protocol for communication connection, the first CPU uses the UPI protocol and the PCIE protocol to communicate with the backplane, and the second CPU uses the UPI protocol and the PCIE protocol to communicate with the backplane, the first memory stick group is connected to the first CPU, and the second memory stick group is connected to the second CPU. 2. application according to claim 1 is characterized in that in purley platform eight-way server PCH configuration structure, The computing node also includes: a CPLD module and an XDP debugging module for debugging the running status of internal modules of the computing node. 3. application according to claim 1 is characterized in that in purley platform eight-way server PCH configuration structure, The communication connection between the first CPU and the PCH module adopts DMI protocol and PCIE protocol. 4. application according to claim 1 is characterized in that in purley platform eight-way server PCH configuration structure, The storage module adopts at least two SSD hard disks, and the storage module and the PCH module adopt PCIE protocol communication connection. 5. application according to claim 1 is characterized in that in purley platform eight-way server PCH configuration structure, BMC management module and PCH module adopt NCSI agreement, PCIE agreement, LPC agreement, USB agreement communication connection. 6. application according to claim 1 is characterized in that in purley platform eight-way server PCH configuration structure, The BMC management module and the PHY module are connected by RGMII protocol, and the PHY module and the backplane use SERDES data transmission. 7. application according to claim 1 is characterized in that in purley platform eight-way server PCH configuration structure, The computing node also includes: a power module for supplying power to components on the overall computing node; the power module is provided with a P12V pin.